mirror of https://gitee.com/openkylin/linux.git
x86: Fix CPU llc_shared_map information for AMD Magny-Cours
Construct entire NodeID and use it as cpu_llc_id. Thus internal node siblings are stored in llc_shared_map. Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
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@ -95,6 +95,7 @@
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#define X86_FEATURE_NONSTOP_TSC (3*32+24) /* TSC does not stop in C states */
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#define X86_FEATURE_CLFLUSH_MONITOR (3*32+25) /* "" clflush reqd with monitor */
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#define X86_FEATURE_EXTD_APICID (3*32+26) /* has extended APICID (8 bits) */
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#define X86_FEATURE_AMD_DCM (3*32+27) /* multi-node processor */
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/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
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#define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */
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@ -250,6 +250,64 @@ static int __cpuinit nearby_node(int apicid)
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}
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#endif
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/*
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* Fixup core topology information for AMD multi-node processors.
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* Assumption 1: Number of cores in each internal node is the same.
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* Assumption 2: Mixed systems with both single-node and dual-node
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* processors are not supported.
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*/
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#ifdef CONFIG_X86_HT
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static void __cpuinit amd_fixup_dcm(struct cpuinfo_x86 *c)
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{
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#ifdef CONFIG_PCI
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u32 t, cpn;
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u8 n, n_id;
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int cpu = smp_processor_id();
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/* fixup topology information only once for a core */
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if (cpu_has(c, X86_FEATURE_AMD_DCM))
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return;
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/* check for multi-node processor on boot cpu */
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t = read_pci_config(0, 24, 3, 0xe8);
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if (!(t & (1 << 29)))
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return;
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set_cpu_cap(c, X86_FEATURE_AMD_DCM);
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/* cores per node: each internal node has half the number of cores */
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cpn = c->x86_max_cores >> 1;
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/* even-numbered NB_id of this dual-node processor */
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n = c->phys_proc_id << 1;
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/*
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* determine internal node id and assign cores fifty-fifty to
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* each node of the dual-node processor
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*/
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t = read_pci_config(0, 24 + n, 3, 0xe8);
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n = (t>>30) & 0x3;
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if (n == 0) {
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if (c->cpu_core_id < cpn)
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n_id = 0;
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else
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n_id = 1;
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} else {
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if (c->cpu_core_id < cpn)
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n_id = 1;
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else
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n_id = 0;
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}
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/* compute entire NodeID, use llc_shared_map to store sibling info */
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per_cpu(cpu_llc_id, cpu) = (c->phys_proc_id << 1) + n_id;
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/* fixup core id to be in range from 0 to cpn */
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c->cpu_core_id = c->cpu_core_id % cpn;
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#endif
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}
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#endif
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/*
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* On a AMD dual core setup the lower bits of the APIC id distingush the cores.
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* Assumes number of cores is a power of two.
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@ -267,6 +325,9 @@ static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
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c->phys_proc_id = c->initial_apicid >> bits;
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/* use socket ID also for last level cache */
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per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
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/* fixup topology information on multi-node processors */
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if ((c->x86 == 0x10) && (c->x86_model == 9))
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amd_fixup_dcm(c);
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#endif
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}
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@ -277,7 +338,8 @@ static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
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int node;
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unsigned apicid = cpu_has_apic ? hard_smp_processor_id() : c->apicid;
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node = c->phys_proc_id;
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node = per_cpu(cpu_llc_id, cpu);
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if (apicid_to_node[apicid] != NUMA_NO_NODE)
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node = apicid_to_node[apicid];
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if (!node_online(node)) {
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