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i2c-bfin-twi: abort transfer is MEM bit is reset unexpectedly 

Sometimes, the first I2C transmit interrupt is not serviced in time (like
when higher priority interrupts take too long).  Since the RESTART bit is
not set before the next I2C clock, when the TWI handler is finally called,
the I2C session is aborted (MEM bit is reset) and both SMITSERV and MCOMP
int status bits are set.

So when this happens, abort the transfer.

Reported-by: Isabelle Leonardi <i.leonardi@detracom.fr>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
This commit is contained in:
Sonic Zhang 2011-06-23 17:07:54 -04:00 committed by Ben Dooks
parent af4087e0e6
commit 4a65163e3b
1 changed files with 7 additions and 1 deletions
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8
drivers/i2c/busses/i2c-bfin-twi.c
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@ -193,7 +193,13 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface,
return;
}
if (twi_int_status & MCOMP) {
if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
if ((read_MASTER_CTL(iface) & MEN) == 0 &&
(iface->cur_mode == TWI_I2C_MODE_REPEAT ||
iface->cur_mode == TWI_I2C_MODE_COMBINED)) {
iface->result = -1;
write_INT_MASK(iface, 0);
write_MASTER_CTL(iface, 0);
} else if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
if (iface->readNum == 0) {
/* set the read number to 1 and ask for manual
* stop in block combine mode