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arm64: socfpga: merge Agilex and N5X into ARCH_INTEL_SOCFPGA 

Agilex, N5X and Stratix 10 share all quite similar arm64 hard cores and
SoC-part.  Up to a point that N5X uses the same DTSI as Agilex.  From
the Linux kernel point of view these are flavors of the same
architecture so there is no need for three top-level arm64
architectures.  Simplify this by merging all three architectures into
ARCH_INTEL_SOCFPGA and dropping the other ARCH* arm64 Kconfig entries.

The side effect is that the INTEL_STRATIX10_SERVICE will now be
available for both 32-bit and 64-bit Intel SoCFPGA, even though it is
used only for 64-bit.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
This commit is contained in:
Krzysztof Kozlowski 2021-03-11 16:25:38 +01:00 committed by Dinh Nguyen
parent 098da961d8
commit 4a9a1a5602
8 changed files with 13 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
arch/arm64/Kconfig.platforms
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@ -8,16 +8,6 @@ config ARCH_ACTIONS
help
This enables support for the Actions Semiconductor S900 SoC family.
config ARCH_AGILEX
bool "Intel's Agilex SoCFPGA Family"
help
This enables support for Intel's Agilex SoCFPGA Family.
config ARCH_N5X
bool "Intel's eASIC N5X SoCFPGA Family"
help
This enables support for Intel's eASIC N5X SoCFPGA Family.
config ARCH_SUNXI
bool "Allwinner sunxi 64-bit SoC Family"
select ARCH_HAS_RESET_CONTROLLER
@ -254,14 +244,11 @@ config ARCH_SEATTLE
help
This enables support for AMD Seattle SOC Family
config ARCH_STRATIX10
bool "Altera's Stratix 10 SoCFPGA Family"
select ARCH_INTEL_SOCFPGA
help
This enables support for Altera's Stratix 10 SoCFPGA Family.
config ARCH_INTEL_SOCFPGA
bool
bool "Intel's SoCFPGA ARMv8 Families"
help
This enables support for Intel's SoCFPGA ARMv8 families:
Stratix 10 (ex. Altera), Agilex and eASIC N5X.
config ARCH_SYNQUACER
bool "Socionext SynQuacer SoC Family"

6
arch/arm64/boot/dts/intel/Makefile
View File

@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-only
dtb-$(CONFIG_ARCH_AGILEX) += socfpga_agilex_socdk.dtb \
socfpga_agilex_socdk_nand.dtb
dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_socdk.dtb \
socfpga_agilex_socdk_nand.dtb \
socfpga_n5x_socdk.dtb
dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
dtb-$(CONFIG_ARCH_N5X) += socfpga_n5x_socdk.dtb

2
arch/arm64/configs/defconfig
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@ -50,7 +50,7 @@ CONFIG_ARCH_RENESAS=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_ARCH_S32=y
CONFIG_ARCH_SEATTLE=y
CONFIG_ARCH_STRATIX10=y
CONFIG_ARCH_INTEL_SOCFPGA=y
CONFIG_ARCH_SYNQUACER=y
CONFIG_ARCH_TEGRA=y
CONFIG_ARCH_SPRD=y

2
drivers/clk/Makefile
View File

@ -105,8 +105,6 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/
obj-$(CONFIG_CLK_SIFIVE) += sifive/
obj-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga/
obj-$(CONFIG_ARCH_AGILEX) += socfpga/
obj-$(CONFIG_ARCH_N5X) += socfpga/
obj-$(CONFIG_PLAT_SPEAR) += spear/
obj-y += sprd/
obj-$(CONFIG_ARCH_STI) += st/

4
drivers/clk/socfpga/Kconfig
View File

@ -2,5 +2,5 @@
config CLK_INTEL_SOCFPGA64
bool
# Intel Stratix / Agilex / N5X clock controller support
default (ARCH_AGILEX || ARCH_N5X || ARCH_STRATIX10)
depends on ARCH_AGILEX || ARCH_N5X || ARCH_STRATIX10
default ARM64 && ARCH_INTEL_SOCFPGA
depends on ARM64 && ARCH_INTEL_SOCFPGA

2
drivers/firmware/Kconfig
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@ -206,7 +206,7 @@ config FW_CFG_SYSFS_CMDLINE
config INTEL_STRATIX10_SERVICE
tristate "Intel Stratix10 Service Layer"
depends on (ARCH_STRATIX10 || ARCH_AGILEX) && HAVE_ARM_SMCCC
depends on ARCH_INTEL_SOCFPGA && HAVE_ARM_SMCCC
default n
help
Intel Stratix10 service layer runs at privileged exception level,

2
drivers/fpga/Kconfig
View File

@ -60,7 +60,7 @@ config FPGA_MGR_ZYNQ_FPGA
config FPGA_MGR_STRATIX10_SOC
tristate "Intel Stratix10 SoC FPGA Manager"
depends on (ARCH_STRATIX10 && INTEL_STRATIX10_SERVICE)
depends on (ARCH_INTEL_SOCFPGA && INTEL_STRATIX10_SERVICE)
help
FPGA manager driver support for the Intel Stratix10 SoC.

2
drivers/reset/Kconfig
View File

@ -183,7 +183,7 @@ config RESET_SCMI
config RESET_SIMPLE
bool "Simple Reset Controller Driver" if COMPILE_TEST
default ARCH_AGILEX || ARCH_ASPEED || ARCH_BCM4908 || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARC
default ARCH_ASPEED || ARCH_BCM4908 || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC
help
This enables a simple reset controller driver for reset lines that
that can be asserted and deasserted by toggling bits in a contiguous,