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drm/amd/display: Add dp_set_dsc_pps_info_packet to virtual stream encoder 

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Eric Bernstein 2020-09-25 10:54:48 -04:00 committed by Alex Deucher
parent 4a3dea8932
commit 4ab1edbc9d
2 changed files with 17 additions and 9 deletions
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19
drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
View File

@ -493,13 +493,15 @@ void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
OPTC_DSC_DISABLED, 0, 0); OPTC_DSC_DISABLED, 0, 0);
/* disable DSC in stream encoder */ /* disable DSC in stream encoder */
if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { if (dc_is_dp_signal(stream->signal)) {
pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(
pipe_ctx->stream_res.stream_enc,
OPTC_DSC_DISABLED, 0, 0);
pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
pipe_ctx->stream_res.stream_enc, false, NULL); pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(
pipe_ctx->stream_res.stream_enc,
OPTC_DSC_DISABLED, 0, 0);
pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
pipe_ctx->stream_res.stream_enc, false, NULL);
}
} }
/* disable DSC block */ /* disable DSC block */
@ -536,7 +538,6 @@ bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable)
bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable) bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable)
{ {
struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
struct dc *dc = pipe_ctx->stream->ctx->dc;
struct dc_stream_state *stream = pipe_ctx->stream; struct dc_stream_state *stream = pipe_ctx->stream;
if (!pipe_ctx->stream->timing.flags.DSC || !dsc) if (!pipe_ctx->stream->timing.flags.DSC || !dsc)
@ -559,7 +560,7 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable)
DC_LOG_DSC(" "); DC_LOG_DSC(" ");
dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]); dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]);
if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { if (dc_is_dp_signal(stream->signal)) {
DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id); DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id);
pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
pipe_ctx->stream_res.stream_enc, pipe_ctx->stream_res.stream_enc,
@ -568,7 +569,7 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable)
} }
} else { } else {
/* disable DSC PPS in stream encoder */ /* disable DSC PPS in stream encoder */
if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { if (dc_is_dp_signal(stream->signal)) {
pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
pipe_ctx->stream_res.stream_enc, false, NULL); pipe_ctx->stream_res.stream_enc, false, NULL);
} }

7
drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c
View File

@ -99,6 +99,12 @@ static void virtual_setup_stereo_sync(
bool enable) bool enable)
{} {}
static void virtual_stream_encoder_set_dsc_pps_info_packet(
struct stream_encoder *enc,
bool enable,
uint8_t *dsc_packed_pps)
{}
static const struct stream_encoder_funcs virtual_str_enc_funcs = { static const struct stream_encoder_funcs virtual_str_enc_funcs = {
.dp_set_odm_combine = .dp_set_odm_combine =
virtual_enc_dp_set_odm_combine, virtual_enc_dp_set_odm_combine,
@ -128,6 +134,7 @@ static const struct stream_encoder_funcs virtual_str_enc_funcs = {
.hdmi_reset_stream_attribute = virtual_stream_encoder_reset_hdmi_stream_attribute, .hdmi_reset_stream_attribute = virtual_stream_encoder_reset_hdmi_stream_attribute,
.dig_connect_to_otg = virtual_dig_connect_to_otg, .dig_connect_to_otg = virtual_dig_connect_to_otg,
.setup_stereo_sync = virtual_setup_stereo_sync, .setup_stereo_sync = virtual_setup_stereo_sync,
.dp_set_dsc_pps_info_packet = virtual_stream_encoder_set_dsc_pps_info_packet,
}; };
bool virtual_stream_encoder_construct( bool virtual_stream_encoder_construct(