mirror of https://gitee.com/openkylin/linux.git
drm/amdgpu: use kernel submit helper in vm
Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian K?nig <christian.koenig@amd.com>
This commit is contained in:
parent
953e8fd4e7
commit
4af9f07ccd
drivers/gpu/drm/amd/amdgpu
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@ -1235,19 +1235,6 @@ struct amdgpu_cs_chunk {
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void __user *user_ptr;
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};
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union amdgpu_sched_job_param {
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struct {
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struct amdgpu_vm *vm;
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uint64_t start;
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uint64_t last;
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struct fence **fence;
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} vm_mapping;
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struct {
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struct amdgpu_bo *bo;
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} vm;
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};
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struct amdgpu_cs_parser {
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struct amdgpu_device *adev;
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struct drm_file *filp;
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@ -1272,7 +1259,6 @@ struct amdgpu_cs_parser {
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struct mutex job_lock;
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struct work_struct job_work;
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int (*prepare_job)(struct amdgpu_cs_parser *sched_job);
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union amdgpu_sched_job_param job_param;
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int (*run_job)(struct amdgpu_cs_parser *sched_job);
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int (*free_job)(struct amdgpu_cs_parser *sched_job);
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};
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@ -121,7 +121,7 @@ int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev,
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uint64_t v_seq;
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struct amdgpu_cs_parser *sched_job =
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amdgpu_cs_parser_create(adev, owner, &adev->kernel_ctx,
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ibs, 1);
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ibs, num_ibs);
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if(!sched_job) {
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return -ENOMEM;
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}
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@ -139,7 +139,7 @@ int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev,
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if (r)
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WARN(true, "emit timeout\n");
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} else
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r = amdgpu_ib_schedule(adev, 1, ibs, owner);
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r = amdgpu_ib_schedule(adev, num_ibs, ibs, owner);
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if (r)
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return r;
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*f = &ibs[num_ibs - 1].fence->base;
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@ -316,14 +316,6 @@ static int amdgpu_vm_free_job(
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return 0;
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}
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static int amdgpu_vm_run_job(
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struct amdgpu_cs_parser *sched_job)
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{
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amdgpu_bo_fence(sched_job->job_param.vm.bo,
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&sched_job->ibs[sched_job->num_ibs -1].fence->base, true);
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return 0;
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}
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/**
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* amdgpu_vm_clear_bo - initially clear the page dir/table
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*
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@ -334,7 +326,7 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
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struct amdgpu_bo *bo)
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{
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struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring;
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struct amdgpu_cs_parser *sched_job = NULL;
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struct fence *fence = NULL;
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struct amdgpu_ib *ib;
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unsigned entries;
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uint64_t addr;
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@ -368,38 +360,16 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
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amdgpu_vm_update_pages(adev, ib, addr, 0, entries, 0, 0, 0);
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amdgpu_vm_pad_ib(adev, ib);
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WARN_ON(ib->length_dw > 64);
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r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
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&amdgpu_vm_free_job,
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AMDGPU_FENCE_OWNER_VM,
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&fence);
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if (!r)
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amdgpu_bo_fence(bo, fence, true);
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if (amdgpu_enable_scheduler) {
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int r;
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uint64_t v_seq;
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sched_job = amdgpu_cs_parser_create(adev, AMDGPU_FENCE_OWNER_VM,
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&adev->kernel_ctx, ib, 1);
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if(!sched_job)
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goto error_free;
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sched_job->job_param.vm.bo = bo;
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sched_job->run_job = amdgpu_vm_run_job;
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sched_job->free_job = amdgpu_vm_free_job;
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v_seq = atomic64_inc_return(&adev->kernel_ctx.rings[ring->idx].entity.last_queued_v_seq);
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ib->sequence = v_seq;
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amd_sched_push_job(ring->scheduler,
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&adev->kernel_ctx.rings[ring->idx].entity,
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sched_job);
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r = amd_sched_wait_emit(&adev->kernel_ctx.rings[ring->idx].entity,
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v_seq,
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false,
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-1);
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if (r)
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DRM_ERROR("emit timeout\n");
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amdgpu_bo_unreserve(bo);
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return 0;
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} else {
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r = amdgpu_ib_schedule(adev, 1, ib, AMDGPU_FENCE_OWNER_VM);
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if (r)
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goto error_free;
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amdgpu_bo_fence(bo, &ib->fence->base, true);
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}
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error_free:
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amdgpu_ib_free(adev, ib);
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kfree(ib);
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@ -456,7 +426,7 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
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uint64_t last_pde = ~0, last_pt = ~0;
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unsigned count = 0, pt_idx, ndw;
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struct amdgpu_ib *ib;
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struct amdgpu_cs_parser *sched_job = NULL;
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struct fence *fence = NULL;
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int r;
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@ -518,37 +488,13 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
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amdgpu_vm_pad_ib(adev, ib);
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amdgpu_sync_resv(adev, &ib->sync, pd->tbo.resv, AMDGPU_FENCE_OWNER_VM);
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WARN_ON(ib->length_dw > ndw);
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if (amdgpu_enable_scheduler) {
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int r;
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uint64_t v_seq;
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sched_job = amdgpu_cs_parser_create(adev, AMDGPU_FENCE_OWNER_VM,
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&adev->kernel_ctx,
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ib, 1);
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if(!sched_job)
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goto error_free;
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sched_job->job_param.vm.bo = pd;
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sched_job->run_job = amdgpu_vm_run_job;
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sched_job->free_job = amdgpu_vm_free_job;
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v_seq = atomic64_inc_return(&adev->kernel_ctx.rings[ring->idx].entity.last_queued_v_seq);
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ib->sequence = v_seq;
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amd_sched_push_job(ring->scheduler,
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&adev->kernel_ctx.rings[ring->idx].entity,
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sched_job);
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r = amd_sched_wait_emit(&adev->kernel_ctx.rings[ring->idx].entity,
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v_seq,
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false,
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-1);
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if (r)
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DRM_ERROR("emit timeout\n");
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} else {
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r = amdgpu_ib_schedule(adev, 1, ib, AMDGPU_FENCE_OWNER_VM);
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if (r) {
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amdgpu_ib_free(adev, ib);
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return r;
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}
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amdgpu_bo_fence(pd, &ib->fence->base, true);
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}
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r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
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&amdgpu_vm_free_job,
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AMDGPU_FENCE_OWNER_VM,
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&fence);
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if (r)
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goto error_free;
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amdgpu_bo_fence(pd, fence, true);
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}
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if (!amdgpu_enable_scheduler || ib->length_dw == 0) {
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@ -559,11 +505,9 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
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return 0;
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error_free:
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if (sched_job)
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kfree(sched_job);
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amdgpu_ib_free(adev, ib);
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kfree(ib);
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return -ENOMEM;
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return r;
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}
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/**
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@ -748,20 +692,6 @@ static void amdgpu_vm_fence_pts(struct amdgpu_vm *vm,
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amdgpu_bo_fence(vm->page_tables[i].bo, fence, true);
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}
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static int amdgpu_vm_bo_update_mapping_run_job(
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struct amdgpu_cs_parser *sched_job)
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{
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struct fence **fence = sched_job->job_param.vm_mapping.fence;
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amdgpu_vm_fence_pts(sched_job->job_param.vm_mapping.vm,
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sched_job->job_param.vm_mapping.start,
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sched_job->job_param.vm_mapping.last + 1,
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&sched_job->ibs[sched_job->num_ibs -1].fence->base);
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if (fence) {
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fence_put(*fence);
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*fence = fence_get(&sched_job->ibs[sched_job->num_ibs -1].fence->base);
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}
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return 0;
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}
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/**
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* amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
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*
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@ -787,7 +717,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
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unsigned nptes, ncmds, ndw;
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uint32_t flags = gtt_flags;
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struct amdgpu_ib *ib;
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struct amdgpu_cs_parser *sched_job = NULL;
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struct fence *f = NULL;
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int r;
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/* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
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@ -869,56 +799,29 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
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amdgpu_vm_pad_ib(adev, ib);
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WARN_ON(ib->length_dw > ndw);
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r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
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&amdgpu_vm_free_job,
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AMDGPU_FENCE_OWNER_VM,
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&f);
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if (r)
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goto error_free;
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if (amdgpu_enable_scheduler) {
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int r;
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uint64_t v_seq;
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sched_job = amdgpu_cs_parser_create(adev, AMDGPU_FENCE_OWNER_VM,
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&adev->kernel_ctx, ib, 1);
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if(!sched_job)
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goto error_free;
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sched_job->job_param.vm_mapping.vm = vm;
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sched_job->job_param.vm_mapping.start = mapping->it.start;
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sched_job->job_param.vm_mapping.last = mapping->it.last;
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sched_job->job_param.vm_mapping.fence = fence;
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sched_job->run_job = amdgpu_vm_bo_update_mapping_run_job;
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sched_job->free_job = amdgpu_vm_free_job;
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v_seq = atomic64_inc_return(&adev->kernel_ctx.rings[ring->idx].entity.last_queued_v_seq);
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ib->sequence = v_seq;
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amd_sched_push_job(ring->scheduler,
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&adev->kernel_ctx.rings[ring->idx].entity,
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sched_job);
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r = amd_sched_wait_emit(&adev->kernel_ctx.rings[ring->idx].entity,
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v_seq,
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false,
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-1);
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if (r)
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DRM_ERROR("emit timeout\n");
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} else {
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r = amdgpu_ib_schedule(adev, 1, ib, AMDGPU_FENCE_OWNER_VM);
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if (r) {
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amdgpu_ib_free(adev, ib);
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return r;
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}
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amdgpu_vm_fence_pts(vm, mapping->it.start,
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mapping->it.last + 1, &ib->fence->base);
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if (fence) {
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fence_put(*fence);
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*fence = fence_get(&ib->fence->base);
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}
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amdgpu_vm_fence_pts(vm, mapping->it.start,
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mapping->it.last + 1, f);
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if (fence) {
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fence_put(*fence);
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*fence = fence_get(f);
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}
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if (!amdgpu_enable_scheduler) {
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amdgpu_ib_free(adev, ib);
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kfree(ib);
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}
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return 0;
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error_free:
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if (sched_job)
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kfree(sched_job);
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amdgpu_ib_free(adev, ib);
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kfree(ib);
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return -ENOMEM;
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return r;
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}
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/**
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