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Merge branch 'next/deletion' of git+ssh://master.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc 

* 'next/deletion' of git+ssh://master.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc:
  ARM: mach-loki: delete
  ARM: mach-s3c2400: delete
  ARM: mach-s3c24a0: delete
This commit is contained in:
Linus Torvalds 2011-07-25 12:43:28 -07:00
parent ae4c42e4e4 c8b7d43b6d
commit 4b478cedcd
54 changed files with 9 additions and 2133 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
Documentation/arm/Samsung-S3C24XX/Overview.txt
View File

@ -8,10 +8,13 @@ Introduction
The Samsung S3C24XX range of ARM9 System-on-Chip CPUs are supported
by the 's3c2410' architecture of ARM Linux. Currently the S3C2410,
S3C2412, S3C2413, S3C2416 S3C2440, S3C2442, S3C2443 and S3C2450 devices
S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 and S3C2450 devices
are supported.
Support for the S3C2400 and S3C24A0 series are in progress.
Support for the S3C2400 and S3C24A0 series was never completed and the
corresponding code has been removed after a while. If someone wishes to
revive this effort, partial support can be retrieved from earlier Linux
versions.
The S3C2416 and S3C2450 devices are very similar and S3C2450 support is
included under the arch/arm/mach-s3c2416 directory. Note, whilst core

11
arch/arm/Kconfig
View File

@ -493,14 +493,6 @@ config ARCH_KIRKWOOD
Support for the following Marvell Kirkwood series SoCs:
88F6180, 88F6192 and 88F6281.
config ARCH_LOKI
bool "Marvell Loki (88RC8480)"
select CPU_FEROCEON
select GENERIC_CLOCKEVENTS
select PLAT_ORION
help
Support for the Marvell Loki (88RC8480) SoC.
config ARCH_LPC32XX
bool "NXP LPC32XX"
select CLKSRC_MMIO
@ -937,8 +929,6 @@ source "arch/arm/mach-kirkwood/Kconfig"
source "arch/arm/mach-ks8695/Kconfig"
source "arch/arm/mach-loki/Kconfig"
source "arch/arm/mach-lpc32xx/Kconfig"
source "arch/arm/mach-msm/Kconfig"
@ -982,7 +972,6 @@ source "arch/arm/plat-spear/Kconfig"
source "arch/arm/plat-tcc/Kconfig"
if ARCH_S3C2410
source "arch/arm/mach-s3c2400/Kconfig"
source "arch/arm/mach-s3c2410/Kconfig"
source "arch/arm/mach-s3c2412/Kconfig"
source "arch/arm/mach-s3c2416/Kconfig"

4
arch/arm/Makefile
View File

@ -150,7 +150,6 @@ machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx
machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx
machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood
machine-$(CONFIG_ARCH_KS8695) := ks8695
machine-$(CONFIG_ARCH_LOKI) := loki
machine-$(CONFIG_ARCH_LPC32XX) := lpc32xx
machine-$(CONFIG_ARCH_MMP) := mmp
machine-$(CONFIG_ARCH_MSM) := msm
@ -172,8 +171,7 @@ machine-$(CONFIG_ARCH_PNX4008) := pnx4008
machine-$(CONFIG_ARCH_PXA) := pxa
machine-$(CONFIG_ARCH_REALVIEW) := realview
machine-$(CONFIG_ARCH_RPC) := rpc
machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2416 s3c2440 s3c2443
machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0
machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2412 s3c2416 s3c2440 s3c2443
machine-$(CONFIG_ARCH_S3C64XX) := s3c64xx
machine-$(CONFIG_ARCH_S5P64X0) := s5p64x0
machine-$(CONFIG_ARCH_S5PC100) := s5pc100

120
arch/arm/configs/loki_defconfig
View File

@ -1,120 +0,0 @@
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_EXPERT=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_LOKI=y
CONFIG_MACH_LB88RC8480=y
# CONFIG_CPU_FEROCEON_OLD_ID is not set
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_IPV6 is not set
CONFIG_NET_PKTGEN=m
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_FTL=y
CONFIG_NFTL=y
CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_GEOMETRY=y
CONFIG_MTD_CFI_I4=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_VERIFY_WRITE=y
CONFIG_MTD_NAND_ORION=y
CONFIG_BLK_DEV_LOOP=y
# CONFIG_MISC_DEVICES is not set
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_DEV_SR=m
CONFIG_CHR_DEV_SG=m
CONFIG_ATA=y
CONFIG_SATA_MV=y
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
CONFIG_MV643XX_ETH=y
# CONFIG_NETDEV_10000 is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
CONFIG_LEGACY_PTY_COUNT=16
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MV64XXX=y
CONFIG_SPI=y
# CONFIG_HWMON is not set
# CONFIG_VGA_CONSOLE is not set
CONFIG_USB=y
CONFIG_USB_DEVICEFS=y
CONFIG_USB_PRINTER=y
CONFIG_USB_STORAGE=y
CONFIG_USB_STORAGE_DATAFAB=y
CONFIG_USB_STORAGE_FREECOM=y
CONFIG_USB_STORAGE_SDDR09=y
CONFIG_USB_STORAGE_SDDR55=y
CONFIG_USB_STORAGE_JUMPSHOT=y
CONFIG_NEW_LEDS=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
# CONFIG_EXT3_FS_XATTR is not set
CONFIG_XFS_FS=y
CONFIG_INOTIFY=y
CONFIG_ISO9660_FS=y
CONFIG_UDF_FS=m
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_CRAMFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_BSD_DISKLABEL=y
CONFIG_MINIX_SUBPARTITION=y
CONFIG_SOLARIS_X86_PARTITION=y
CONFIG_UNIXWARE_DISKLABEL=y
CONFIG_LDM_PARTITION=y
CONFIG_LDM_DEBUG=y
CONFIG_SUN_PARTITION=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_SYSCTL_SYSCALL_CHECK=y
CONFIG_DEBUG_USER=y
CONFIG_CRYPTO_CBC=m
CONFIG_CRYPTO_ECB=m
CONFIG_CRYPTO_PCBC=m
CONFIG_CRC_CCITT=y
CONFIG_CRC16=y
CONFIG_LIBCRC32C=y

13
arch/arm/mach-loki/Kconfig
View File

@ -1,13 +0,0 @@
if ARCH_LOKI
menu "Marvell Loki (88RC8480) Implementations"
config MACH_LB88RC8480
bool "Marvell LB88RC8480 Development Board"
help
Say 'Y' here if you want your kernel to support the
Marvell LB88RC8480 Development Board.
endmenu
endif

3
arch/arm/mach-loki/Makefile
View File

@ -1,3 +0,0 @@
obj-y += common.o addr-map.o irq.o
obj-$(CONFIG_MACH_LB88RC8480) += lb88rc8480-setup.o

3
arch/arm/mach-loki/Makefile.boot
View File

@ -1,3 +0,0 @@
zreladdr-y := 0x00008000
params_phys-y := 0x00000100
initrd_phys-y := 0x00800000

122
arch/arm/mach-loki/addr-map.c
View File

@ -1,122 +0,0 @@
/*
* arch/arm/mach-loki/addr-map.c
*
* Address map functions for Marvell Loki (88RC8480) SoCs
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/mbus.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include "common.h"
/*
* Generic Address Decode Windows bit settings
*/
#define TARGET_DDR 0
#define TARGET_DEV_BUS 1
#define TARGET_PCIE0 3
#define TARGET_PCIE1 4
#define ATTR_DEV_BOOT 0x0f
#define ATTR_DEV_CS2 0x1b
#define ATTR_DEV_CS1 0x1d
#define ATTR_DEV_CS0 0x1e
#define ATTR_PCIE_IO 0x51
#define ATTR_PCIE_MEM 0x59
/*
* Helpers to get DDR bank info
*/
#define DDR_SIZE_CS(n) DDR_REG(0x1500 + ((n) << 3))
#define DDR_BASE_CS(n) DDR_REG(0x1504 + ((n) << 3))
/*
* CPU Address Decode Windows registers
*/
#define BRIDGE_REG(x) (BRIDGE_VIRT_BASE | (x))
#define CPU_WIN_CTRL(n) BRIDGE_REG(0x000 | ((n) << 4))
#define CPU_WIN_BASE(n) BRIDGE_REG(0x004 | ((n) << 4))
#define CPU_WIN_REMAP_LO(n) BRIDGE_REG(0x008 | ((n) << 4))
#define CPU_WIN_REMAP_HI(n) BRIDGE_REG(0x00c | ((n) << 4))
struct mbus_dram_target_info loki_mbus_dram_info;
static void __init setup_cpu_win(int win, u32 base, u32 size,
u8 target, u8 attr, int remap)
{
u32 ctrl;
base &= 0xffff0000;
ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (1 << 5) | target;
writel(base, CPU_WIN_BASE(win));
writel(ctrl, CPU_WIN_CTRL(win));
if (win < 2) {
if (remap < 0)
remap = base;
writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win));
writel(0, CPU_WIN_REMAP_HI(win));
}
}
void __init loki_setup_cpu_mbus(void)
{
int i;
int cs;
/*
* First, disable and clear windows.
*/
for (i = 0; i < 8; i++) {
writel(0, CPU_WIN_BASE(i));
writel(0, CPU_WIN_CTRL(i));
if (i < 2) {
writel(0, CPU_WIN_REMAP_LO(i));
writel(0, CPU_WIN_REMAP_HI(i));
}
}
/*
* Setup windows for PCIe IO+MEM space.
*/
setup_cpu_win(2, LOKI_PCIE0_MEM_PHYS_BASE, LOKI_PCIE0_MEM_SIZE,
TARGET_PCIE0, ATTR_PCIE_MEM, -1);
setup_cpu_win(3, LOKI_PCIE1_MEM_PHYS_BASE, LOKI_PCIE1_MEM_SIZE,
TARGET_PCIE1, ATTR_PCIE_MEM, -1);
/*
* Setup MBUS dram target info.
*/
loki_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
for (i = 0, cs = 0; i < 4; i++) {
u32 base = readl(DDR_BASE_CS(i));
u32 size = readl(DDR_SIZE_CS(i));
/*
* Chip select enabled?
*/
if (size & 1) {
struct mbus_dram_window *w;
w = &loki_mbus_dram_info.cs[cs++];
w->cs_index = i;
w->mbus_attr = 0xf & ~(1 << i);
w->base = base & 0xffff0000;
w->size = (size | 0x0000ffff) + 1;
}
}
loki_mbus_dram_info.num_cs = cs;
}
void __init loki_setup_dev_boot_win(u32 base, u32 size)
{
setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
}

162
arch/arm/mach-loki/common.c
View File

@ -1,162 +0,0 @@
/*
* arch/arm/mach-loki/common.c
*
* Core functions for Marvell Loki (88RC8480) SoCs
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/mbus.h>
#include <linux/dma-mapping.h>
#include <asm/page.h>
#include <asm/timex.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <mach/bridge-regs.h>
#include <mach/loki.h>
#include <plat/orion_nand.h>
#include <plat/time.h>
#include <plat/common.h>
#include "common.h"
/*****************************************************************************
* I/O Address Mapping
****************************************************************************/
static struct map_desc loki_io_desc[] __initdata = {
{
.virtual = LOKI_REGS_VIRT_BASE,
.pfn = __phys_to_pfn(LOKI_REGS_PHYS_BASE),
.length = LOKI_REGS_SIZE,
.type = MT_DEVICE,
},
};
void __init loki_map_io(void)
{
iotable_init(loki_io_desc, ARRAY_SIZE(loki_io_desc));
}
/*****************************************************************************
* GE00
****************************************************************************/
void __init loki_ge0_init(struct mv643xx_eth_platform_data *eth_data)
{
writel(0x00079220, GE0_VIRT_BASE + 0x20b0);
orion_ge00_init(eth_data, &loki_mbus_dram_info,
GE0_PHYS_BASE, IRQ_LOKI_GBE_A_INT,
0, LOKI_TCLK);
}
/*****************************************************************************
* GE01
****************************************************************************/
void __init loki_ge1_init(struct mv643xx_eth_platform_data *eth_data)
{
writel(0x00079220, GE1_VIRT_BASE + 0x20b0);
orion_ge01_init(eth_data, &loki_mbus_dram_info,
GE1_PHYS_BASE, IRQ_LOKI_GBE_B_INT,
0, LOKI_TCLK);
}
/*****************************************************************************
* SAS/SATA
****************************************************************************/
static struct resource loki_sas_resources[] = {
{
.name = "mvsas0 mem",
.start = SAS0_PHYS_BASE,
.end = SAS0_PHYS_BASE + 0x01ff,
.flags = IORESOURCE_MEM,
}, {
.name = "mvsas0 irq",
.start = IRQ_LOKI_SAS_A,
.end = IRQ_LOKI_SAS_A,
.flags = IORESOURCE_IRQ,
}, {
.name = "mvsas1 mem",
.start = SAS1_PHYS_BASE,
.end = SAS1_PHYS_BASE + 0x01ff,
.flags = IORESOURCE_MEM,
}, {
.name = "mvsas1 irq",
.start = IRQ_LOKI_SAS_B,
.end = IRQ_LOKI_SAS_B,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device loki_sas = {
.name = "mvsas",
.id = 0,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(loki_sas_resources),
.resource = loki_sas_resources,
};
void __init loki_sas_init(void)
{
writel(0x8300f707, DDR_REG(0x1424));
platform_device_register(&loki_sas);
}
/*****************************************************************************
* UART0
****************************************************************************/
void __init loki_uart0_init(void)
{
orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
IRQ_LOKI_UART0, LOKI_TCLK);
}
/*****************************************************************************
* UART1
****************************************************************************/
void __init loki_uart1_init(void)
{
orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
IRQ_LOKI_UART1, LOKI_TCLK);
}
/*****************************************************************************
* Time handling
****************************************************************************/
void __init loki_init_early(void)
{
orion_time_set_base(TIMER_VIRT_BASE);
}
static void loki_timer_init(void)
{
orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
IRQ_LOKI_BRIDGE, LOKI_TCLK);
}
struct sys_timer loki_timer = {
.init = loki_timer_init,
};
/*****************************************************************************
* General
****************************************************************************/
void __init loki_init(void)
{
printk(KERN_INFO "Loki ID: 88RC8480. TCLK=%d.\n", LOKI_TCLK);
loki_setup_cpu_mbus();
}

37
arch/arm/mach-loki/common.h
View File

@ -1,37 +0,0 @@
/*
* arch/arm/mach-loki/common.h
*
* Core functions for Marvell Loki (88RC8480) SoCs
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ARCH_LOKI_COMMON_H
#define __ARCH_LOKI_COMMON_H
struct mv643xx_eth_platform_data;
/*
* Basic Loki init functions used early by machine-setup.
*/
void loki_map_io(void);
void loki_init(void);
void loki_init_early(void);
void loki_init_irq(void);
extern struct mbus_dram_target_info loki_mbus_dram_info;
void loki_setup_cpu_mbus(void);
void loki_setup_dev_boot_win(u32 base, u32 size);
void loki_ge0_init(struct mv643xx_eth_platform_data *eth_data);
void loki_ge1_init(struct mv643xx_eth_platform_data *eth_data);
void loki_sas_init(void);
void loki_uart0_init(void);
void loki_uart1_init(void);
extern struct sys_timer loki_timer;
#endif

28
arch/arm/mach-loki/include/mach/bridge-regs.h
View File

@ -1,28 +0,0 @@
/*
* arch/arm/mach-loki/include/mach/bridge-regs.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_BRIDGE_REGS_H
#define __ASM_ARCH_BRIDGE_REGS_H
#include <mach/loki.h>
#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
#define SOFT_RESET_OUT_EN 0x00000004
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
#define SOFT_RESET 0x00000001
#define BRIDGE_INT_TIMER1_CLR 0x0004
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
#define IRQ_CAUSE_OFF 0x0000
#define IRQ_MASK_OFF 0x0004
#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
#endif

19
arch/arm/mach-loki/include/mach/debug-macro.S
View File

@ -1,19 +0,0 @@
/*
* arch/arm/mach-loki/include/mach/debug-macro.S
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <mach/loki.h>
.macro addruart, rp, rv
ldr \rp, =LOKI_REGS_PHYS_BASE
ldr \rv, =LOKI_REGS_VIRT_BASE
orr \rp, \rp, #0x00012000
orr \rv, \rv, #0x00012000
.endm
#define UART_SHIFT 2
#include <asm/hardware/debug-8250.S>

30
arch/arm/mach-loki/include/mach/entry-macro.S
View File

@ -1,30 +0,0 @@
/*
* arch/arm/mach-loki/include/mach/entry-macro.S
*
* Low-level IRQ helper macros for Marvell Loki (88RC8480) platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <mach/bridge-regs.h>
.macro disable_fiq
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_preamble, base, tmp
ldr \base, =IRQ_VIRT_BASE
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \irqstat, [\base, #IRQ_CAUSE_OFF]
ldr \tmp, [\base, #IRQ_MASK_OFF]
mov \irqnr, #0
ands \irqstat, \irqstat, \tmp
clzne \irqnr, \irqstat
rsbne \irqnr, \irqnr, #31
.endm

15
arch/arm/mach-loki/include/mach/hardware.h
View File

@ -1,15 +0,0 @@
/*
* arch/arm/mach-loki/include/mach/hardware.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include "loki.h"
#endif

26
arch/arm/mach-loki/include/mach/io.h
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@ -1,26 +0,0 @@
/*
* arch/arm/mach-loki/include/mach/io.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_IO_H
#define __ASM_ARCH_IO_H
#include "loki.h"
#define IO_SPACE_LIMIT 0xffffffff
static inline void __iomem *__io(unsigned long addr)
{
return (void __iomem *)((addr - LOKI_PCIE0_IO_PHYS_BASE)
+ LOKI_PCIE0_IO_VIRT_BASE);
}
#define __io(a) __io(a)
#define __mem_pci(a) (a)
#endif

58
arch/arm/mach-loki/include/mach/irqs.h
View File

@ -1,58 +0,0 @@
/*
* arch/arm/mach-loki/include/mach/irqs.h
*
* IRQ definitions for Marvell Loki (88RC8480) SoCs
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H
#include "loki.h" /* need GPIO_MAX */
/*
* Interrupt Controller
*/
#define IRQ_LOKI_PCIE_A_CPU_DRBL 0
#define IRQ_LOKI_CPU_PCIE_A_DRBL 1
#define IRQ_LOKI_PCIE_B_CPU_DRBL 2
#define IRQ_LOKI_CPU_PCIE_B_DRBL 3
#define IRQ_LOKI_COM_A_ERR 6
#define IRQ_LOKI_COM_A_IN 7
#define IRQ_LOKI_COM_A_OUT 8
#define IRQ_LOKI_COM_B_ERR 9
#define IRQ_LOKI_COM_B_IN 10
#define IRQ_LOKI_COM_B_OUT 11
#define IRQ_LOKI_DMA_A 12
#define IRQ_LOKI_DMA_B 13
#define IRQ_LOKI_SAS_A 14
#define IRQ_LOKI_SAS_B 15
#define IRQ_LOKI_DDR 16
#define IRQ_LOKI_XOR 17
#define IRQ_LOKI_BRIDGE 18
#define IRQ_LOKI_PCIE_A_ERR 20
#define IRQ_LOKI_PCIE_A_INT 21
#define IRQ_LOKI_PCIE_B_ERR 22
#define IRQ_LOKI_PCIE_B_INT 23
#define IRQ_LOKI_GBE_A_INT 24
#define IRQ_LOKI_GBE_B_INT 25
#define IRQ_LOKI_DEV_ERR 26
#define IRQ_LOKI_UART0 27
#define IRQ_LOKI_UART1 28
#define IRQ_LOKI_TWSI 29
#define IRQ_LOKI_GPIO_23_0 30
#define IRQ_LOKI_GPIO_25_24 31
/*
* Loki General Purpose Pins
*/
#define IRQ_LOKI_GPIO_START 32
#define NR_GPIO_IRQS GPIO_MAX
#define NR_IRQS (IRQ_LOKI_GPIO_START + NR_GPIO_IRQS)
#endif

83
arch/arm/mach-loki/include/mach/loki.h
View File

@ -1,83 +0,0 @@
/*
* arch/arm/mach-loki/include/mach/loki.h
*
* Generic definitions for Marvell Loki (88RC8480) SoC flavors
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_LOKI_H
#define __ASM_ARCH_LOKI_H
/*
* Marvell Loki (88RC8480) address maps.
*
* phys
* d0000000 on-chip peripheral registers
* e0000000 PCIe 0 Memory space
* e8000000 PCIe 1 Memory space
* f0000000 PCIe 0 I/O space
* f0100000 PCIe 1 I/O space
*
* virt phys size
* fed00000 d0000000 1M on-chip peripheral registers
* fee00000 f0000000 64K PCIe 0 I/O space
* fef00000 f0100000 64K PCIe 1 I/O space
*/
#define LOKI_REGS_PHYS_BASE 0xd0000000
#define LOKI_REGS_VIRT_BASE 0xfed00000
#define LOKI_REGS_SIZE SZ_1M
#define LOKI_PCIE0_IO_PHYS_BASE 0xf0000000
#define LOKI_PCIE0_IO_VIRT_BASE 0xfee00000
#define LOKI_PCIE0_IO_BUS_BASE 0x00000000
#define LOKI_PCIE0_IO_SIZE SZ_64K
#define LOKI_PCIE1_IO_PHYS_BASE 0xf0100000
#define LOKI_PCIE1_IO_VIRT_BASE 0xfef00000
#define LOKI_PCIE1_IO_BUS_BASE 0x00000000
#define LOKI_PCIE1_IO_SIZE SZ_64K
#define LOKI_PCIE0_MEM_PHYS_BASE 0xe0000000
#define LOKI_PCIE0_MEM_SIZE SZ_128M
#define LOKI_PCIE1_MEM_PHYS_BASE 0xe8000000
#define LOKI_PCIE1_MEM_SIZE SZ_128M
/*
* Register Map
*/
#define DEV_BUS_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x10000)
#define DEV_BUS_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x10000)
#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000)
#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000)
#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100)
#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100)
#define BRIDGE_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x20000)
#define PCIE0_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x30000)
#define PCIE1_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x40000)
#define SAS0_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x80000)
#define SAS1_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x90000)
#define GE0_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0xa0000)
#define GE0_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xa0000)
#define GE1_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0xb0000)
#define GE1_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xb0000)
#define DDR_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xf0000)
#define DDR_REG(x) (DDR_VIRT_BASE | (x))
#define GPIO_MAX 8
#endif

10
arch/arm/mach-loki/include/mach/memory.h
View File

@ -1,10 +0,0 @@
/*
* arch/arm/mach-loki/include/mach/memory.h
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
#define PLAT_PHYS_OFFSET UL(0x00000000)
#endif

36
arch/arm/mach-loki/include/mach/system.h
View File

@ -1,36 +0,0 @@
/*
* arch/arm/mach-loki/include/mach/system.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
#include <mach/bridge-regs.h>
static inline void arch_idle(void)
{
cpu_do_idle();
}
static inline void arch_reset(char mode, const char *cmd)
{
/*
* Enable soft reset to assert RSTOUTn.
*/
writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
/*
* Assert soft reset.
*/
writel(SOFT_RESET, SYSTEM_SOFT_RESET);
while (1)
;
}
#endif

11
arch/arm/mach-loki/include/mach/timex.h
View File

@ -1,11 +0,0 @@
/*
* arch/arm/mach-loki/include/mach/timex.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#define CLOCK_TICK_RATE (100 * HZ)
#define LOKI_TCLK 180000000

47
arch/arm/mach-loki/include/mach/uncompress.h
View File

@ -1,47 +0,0 @@
/*
* arch/arm/mach-loki/include/mach/uncompress.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/serial_reg.h>
#include <mach/loki.h>
#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE)
static void putc(const char c)
{
unsigned char *base = SERIAL_BASE;
int i;
for (i = 0; i < 0x1000; i++) {
if (base[UART_LSR << 2] & UART_LSR_THRE)
break;
barrier();
}
base[UART_TX << 2] = c;
}
static void flush(void)
{
unsigned char *base = SERIAL_BASE;
unsigned char mask;
int i;
mask = UART_LSR_TEMT | UART_LSR_THRE;
for (i = 0; i < 0x1000; i++) {
if ((base[UART_LSR << 2] & mask) == mask)
break;
barrier();
}
}
/*
* nothing to do
*/
#define arch_decomp_setup()
#define arch_decomp_wdog()

5
arch/arm/mach-loki/include/mach/vmalloc.h
View File

@ -1,5 +0,0 @@
/*
* arch/arm/mach-loki/include/mach/vmalloc.h
*/
#define VMALLOC_END 0xfe800000UL

22
arch/arm/mach-loki/irq.c
View File

@ -1,22 +0,0 @@
/*
* arch/arm/mach-loki/irq.c
*
* Marvell Loki (88RC8480) IRQ handling.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <mach/bridge-regs.h>
#include <plat/irq.h>
#include "common.h"
void __init loki_init_irq(void)
{
orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_OFF));
}

99
arch/arm/mach-loki/lb88rc8480-setup.c
View File

@ -1,99 +0,0 @@
/*
* arch/arm/mach-loki/lb88rc8480-setup.c
*
* Marvell LB88RC8480 Development Board Setup
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/nand.h>
#include <linux/timer.h>
#include <linux/ata_platform.h>
#include <linux/mv643xx_eth.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/loki.h>
#include "common.h"
#define LB88RC8480_FLASH_BOOT_CS_BASE 0xf8000000
#define LB88RC8480_FLASH_BOOT_CS_SIZE SZ_128M
#define LB88RC8480_NOR_BOOT_BASE 0xff000000
#define LB88RC8480_NOR_BOOT_SIZE SZ_16M
static struct mtd_partition lb88rc8480_boot_flash_parts[] = {
{
.name = "kernel",
.offset = 0,
.size = SZ_2M,
}, {
.name = "root-fs",
.offset = SZ_2M,
.size = (SZ_8M + SZ_4M + SZ_1M),
}, {
.name = "u-boot",
.offset = (SZ_8M + SZ_4M + SZ_2M + SZ_1M),
.size = SZ_1M,
},
};
static struct physmap_flash_data lb88rc8480_boot_flash_data = {
.parts = lb88rc8480_boot_flash_parts,
.nr_parts = ARRAY_SIZE(lb88rc8480_boot_flash_parts),
.width = 1, /* 8 bit bus width */
};
static struct resource lb88rc8480_boot_flash_resource = {
.flags = IORESOURCE_MEM,
.start = LB88RC8480_NOR_BOOT_BASE,
.end = LB88RC8480_NOR_BOOT_BASE + LB88RC8480_NOR_BOOT_SIZE - 1,
};
static struct platform_device lb88rc8480_boot_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &lb88rc8480_boot_flash_data,
},
.num_resources = 1,
.resource = &lb88rc8480_boot_flash_resource,
};
static struct mv643xx_eth_platform_data lb88rc8480_ge0_data = {
.phy_addr = MV643XX_ETH_PHY_ADDR(1),
.mac_addr = { 0x00, 0x50, 0x43, 0x11, 0x22, 0x33 },
};
static void __init lb88rc8480_init(void)
{
/*
* Basic setup. Needs to be called early.
*/
loki_init();
loki_ge0_init(&lb88rc8480_ge0_data);
loki_sas_init();
loki_uart0_init();
loki_uart1_init();
loki_setup_dev_boot_win(LB88RC8480_FLASH_BOOT_CS_BASE,
LB88RC8480_FLASH_BOOT_CS_SIZE);
platform_device_register(&lb88rc8480_boot_flash);
}
MACHINE_START(LB88RC8480, "Marvell LB88RC8480 Development Board")
/* Maintainer: Ke Wei <kewei@marvell.com> */
.boot_params = 0x00000100,
.init_machine = lb88rc8480_init,
.map_io = loki_map_io,
.init_early = loki_init_early,
.init_irq = loki_init_irq,
.timer = &loki_timer,
MACHINE_END

7
arch/arm/mach-s3c2400/Kconfig
View File

@ -1,7 +0,0 @@
# Copyright 2007 Simtec Electronics
#
# Licensed under GPLv2
menu "S3C2400 Machines"
endmenu

15
arch/arm/mach-s3c2400/Makefile
View File

@ -1,15 +0,0 @@
# arch/arm/mach-s3c2400/Makefile
#
# Copyright 2007 Simtec Electronics
#
# Licensed under GPLv2
obj-y :=
obj-m :=
obj-n :=
obj- :=
obj-$(CONFIG_CPU_S3C2400) += gpio.o
# Machine support

42
arch/arm/mach-s3c2400/gpio.c
View File

@ -1,42 +0,0 @@
/* linux/arch/arm/mach-s3c2400/gpio.c
*
* Copyright (c) 2006 Lucas Correia Villa Real <lucasvr@gobolinux.org>
*
* S3C2400 GPIO support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <mach/regs-gpio.h>
int s3c2400_gpio_getirq(unsigned int pin)
{
if (pin < S3C2410_GPE(0) || pin > S3C2400_GPE(7))
return -EINVAL; /* not valid interrupts */
return (pin - S3C2410_GPE(0)) + IRQ_EINT0;
}
EXPORT_SYMBOL(s3c2400_gpio_getirq);

66
arch/arm/mach-s3c2400/include/mach/map.h
View File

@ -1,66 +0,0 @@
/* arch/arm/mach-s3c2400/include/mach/map.h
*
* Copyright 2003-2007 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* Copyright 2003, Lucas Correia Villa Real
*
* S3C2400 - Memory map definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C2400_PA_MEMCTRL (0x14000000)
#define S3C2400_PA_USBHOST (0x14200000)
#define S3C2400_PA_IRQ (0x14400000)
#define S3C2400_PA_DMA (0x14600000)
#define S3C2400_PA_CLKPWR (0x14800000)
#define S3C2400_PA_LCD (0x14A00000)
#define S3C2400_PA_UART (0x15000000)
#define S3C2400_PA_TIMER (0x15100000)
#define S3C2400_PA_USBDEV (0x15200140)
#define S3C2400_PA_WATCHDOG (0x15300000)
#define S3C2400_PA_IIC (0x15400000)
#define S3C2400_PA_IIS (0x15508000)
#define S3C2400_PA_GPIO (0x15600000)
#define S3C2400_PA_RTC (0x15700040)
#define S3C2400_PA_ADC (0x15800000)
#define S3C2400_PA_SPI (0x15900000)
#define S3C2400_PA_MMC (0x15A00000)
#define S3C2400_SZ_MMC SZ_1M
/* physical addresses of all the chip-select areas */
#define S3C2400_CS0 (0x00000000)
#define S3C2400_CS1 (0x02000000)
#define S3C2400_CS2 (0x04000000)
#define S3C2400_CS3 (0x06000000)
#define S3C2400_CS4 (0x08000000)
#define S3C2400_CS5 (0x0A000000)
#define S3C2400_CS6 (0x0C000000)
#define S3C2400_CS7 (0x0E000000)
#define S3C2400_SDRAM_PA (S3C2400_CS6)
/* Use a single interface for common resources between S3C24XX cpus */
#define S3C24XX_PA_IRQ S3C2400_PA_IRQ
#define S3C24XX_PA_MEMCTRL S3C2400_PA_MEMCTRL
#define S3C24XX_PA_USBHOST S3C2400_PA_USBHOST
#define S3C24XX_PA_DMA S3C2400_PA_DMA
#define S3C24XX_PA_CLKPWR S3C2400_PA_CLKPWR
#define S3C24XX_PA_LCD S3C2400_PA_LCD
#define S3C24XX_PA_UART S3C2400_PA_UART
#define S3C24XX_PA_TIMER S3C2400_PA_TIMER
#define S3C24XX_PA_USBDEV S3C2400_PA_USBDEV
#define S3C24XX_PA_WATCHDOG S3C2400_PA_WATCHDOG
#define S3C24XX_PA_IIC S3C2400_PA_IIC
#define S3C24XX_PA_IIS S3C2400_PA_IIS
#define S3C24XX_PA_GPIO S3C2400_PA_GPIO
#define S3C24XX_PA_RTC S3C2400_PA_RTC
#define S3C24XX_PA_ADC S3C2400_PA_ADC
#define S3C24XX_PA_SPI S3C2400_PA_SPI

6
arch/arm/mach-s3c2410/include/mach/gpio-fns.h
View File

@ -52,12 +52,6 @@ extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
extern int s3c2410_gpio_getirq(unsigned int pin);
#ifdef CONFIG_CPU_S3C2400
extern int s3c2400_gpio_getirq(unsigned int pin);
#endif /* CONFIG_CPU_S3C2400 */
/* s3c2410_gpio_irqfilter
*
* set the irq filtering on the given pin

241
arch/arm/mach-s3c2410/include/mach/regs-gpio.h
View File

@ -16,11 +16,7 @@
#include <mach/gpio-nrs.h>
#ifdef CONFIG_CPU_S3C2400
#define S3C24XX_MISCCR S3C2400_MISCCR
#else
#define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80)
#endif /* CONFIG_CPU_S3C2400 */
/* general configuration options */
@ -42,67 +38,33 @@
/* configure GPIO ports A..G */
/* port A - S3C2410: 22bits, zero in bit X makes pin X output
* S3C2400: 18bits, zero in bit X makes pin X output
* 1 makes port special function, this is default
*/
#define S3C2410_GPACON S3C2410_GPIOREG(0x00)
#define S3C2410_GPADAT S3C2410_GPIOREG(0x04)
#define S3C2400_GPACON S3C2410_GPIOREG(0x00)
#define S3C2400_GPADAT S3C2410_GPIOREG(0x04)
#define S3C2410_GPA0_ADDR0 (1<<0)
#define S3C2410_GPA1_ADDR16 (1<<1)
#define S3C2410_GPA2_ADDR17 (1<<2)
#define S3C2410_GPA3_ADDR18 (1<<3)
#define S3C2410_GPA4_ADDR19 (1<<4)
#define S3C2410_GPA5_ADDR20 (1<<5)
#define S3C2410_GPA6_ADDR21 (1<<6)
#define S3C2410_GPA7_ADDR22 (1<<7)
#define S3C2410_GPA8_ADDR23 (1<<8)
#define S3C2410_GPA9_ADDR24 (1<<9)
#define S3C2410_GPA10_ADDR25 (1<<10)
#define S3C2400_GPA10_SCKE (1<<10)
#define S3C2410_GPA11_ADDR26 (1<<11)
#define S3C2400_GPA11_nCAS0 (1<<11)
#define S3C2410_GPA12_nGCS1 (1<<12)
#define S3C2400_GPA12_nCAS1 (1<<12)
#define S3C2410_GPA13_nGCS2 (1<<13)
#define S3C2400_GPA13_nGCS1 (1<<13)
#define S3C2410_GPA14_nGCS3 (1<<14)
#define S3C2400_GPA14_nGCS2 (1<<14)
#define S3C2410_GPA15_nGCS4 (1<<15)
#define S3C2400_GPA15_nGCS3 (1<<15)
#define S3C2410_GPA16_nGCS5 (1<<16)
#define S3C2400_GPA16_nGCS4 (1<<16)
#define S3C2410_GPA17_CLE (1<<17)
#define S3C2400_GPA17_nGCS5 (1<<17)
#define S3C2410_GPA18_ALE (1<<18)
#define S3C2410_GPA19_nFWE (1<<19)
#define S3C2410_GPA20_nFRE (1<<20)
#define S3C2410_GPA21_nRSTOUT (1<<21)
#define S3C2410_GPA22_nFCE (1<<22)
/* 0x08 and 0x0c are reserved on S3C2410 */
@ -111,10 +73,6 @@
* GPB is 10 IO pins, each configured by 2 bits each in GPBCON.
* 00 = input, 01 = output, 10=special function, 11=reserved
* S3C2400:
* GPB is 16 IO pins, each configured by 2 bits each in GPBCON.
* 00 = input, 01 = output, 10=data, 11=special function
* bit 0,1 = pin 0, 2,3= pin 1...
*
* CPBUP = pull up resistor control, 1=disabled, 0=enabled
@ -124,78 +82,35 @@
#define S3C2410_GPBDAT S3C2410_GPIOREG(0x14)
#define S3C2410_GPBUP S3C2410_GPIOREG(0x18)
#define S3C2400_GPBCON S3C2410_GPIOREG(0x08)
#define S3C2400_GPBDAT S3C2410_GPIOREG(0x0C)
#define S3C2400_GPBUP S3C2410_GPIOREG(0x10)
/* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */
#define S3C2410_GPB0_TOUT0 (0x02 << 0)
#define S3C2400_GPB0_DATA16 (0x02 << 0)
#define S3C2410_GPB1_TOUT1 (0x02 << 2)
#define S3C2400_GPB1_DATA17 (0x02 << 2)
#define S3C2410_GPB2_TOUT2 (0x02 << 4)
#define S3C2400_GPB2_DATA18 (0x02 << 4)
#define S3C2400_GPB2_TCLK1 (0x03 << 4)
#define S3C2410_GPB3_TOUT3 (0x02 << 6)
#define S3C2400_GPB3_DATA19 (0x02 << 6)
#define S3C2400_GPB3_TXD1 (0x03 << 6)
#define S3C2410_GPB4_TCLK0 (0x02 << 8)
#define S3C2400_GPB4_DATA20 (0x02 << 8)
#define S3C2410_GPB4_MASK (0x03 << 8)
#define S3C2400_GPB4_RXD1 (0x03 << 8)
#define S3C2400_GPB4_MASK (0x03 << 8)
#define S3C2410_GPB5_nXBACK (0x02 << 10)
#define S3C2443_GPB5_XBACK (0x03 << 10)
#define S3C2400_GPB5_DATA21 (0x02 << 10)
#define S3C2400_GPB5_nCTS1 (0x03 << 10)
#define S3C2410_GPB6_nXBREQ (0x02 << 12)
#define S3C2443_GPB6_XBREQ (0x03 << 12)
#define S3C2400_GPB6_DATA22 (0x02 << 12)
#define S3C2400_GPB6_nRTS1 (0x03 << 12)
#define S3C2410_GPB7_nXDACK1 (0x02 << 14)
#define S3C2443_GPB7_XDACK1 (0x03 << 14)
#define S3C2400_GPB7_DATA23 (0x02 << 14)
#define S3C2410_GPB8_nXDREQ1 (0x02 << 16)
#define S3C2400_GPB8_DATA24 (0x02 << 16)
#define S3C2410_GPB9_nXDACK0 (0x02 << 18)
#define S3C2443_GPB9_XDACK0 (0x03 << 18)
#define S3C2400_GPB9_DATA25 (0x02 << 18)
#define S3C2400_GPB9_I2SSDI (0x03 << 18)
#define S3C2410_GPB10_nXDRE0 (0x02 << 20)
#define S3C2443_GPB10_XDREQ0 (0x03 << 20)
#define S3C2400_GPB10_DATA26 (0x02 << 20)
#define S3C2400_GPB10_nSS (0x03 << 20)
#define S3C2400_GPB11_INP (0x00 << 22)
#define S3C2400_GPB11_OUTP (0x01 << 22)
#define S3C2400_GPB11_DATA27 (0x02 << 22)
#define S3C2400_GPB12_INP (0x00 << 24)
#define S3C2400_GPB12_OUTP (0x01 << 24)
#define S3C2400_GPB12_DATA28 (0x02 << 24)
#define S3C2400_GPB13_INP (0x00 << 26)
#define S3C2400_GPB13_OUTP (0x01 << 26)
#define S3C2400_GPB13_DATA29 (0x02 << 26)
#define S3C2400_GPB14_INP (0x00 << 28)
#define S3C2400_GPB14_OUTP (0x01 << 28)
#define S3C2400_GPB14_DATA30 (0x02 << 28)
#define S3C2400_GPB15_INP (0x00 << 30)
#define S3C2400_GPB15_OUTP (0x01 << 30)
#define S3C2400_GPB15_DATA31 (0x02 << 30)
#define S3C2410_GPB_PUPDIS(x) (1<<(x))
@ -208,59 +123,22 @@
#define S3C2410_GPCCON S3C2410_GPIOREG(0x20)
#define S3C2410_GPCDAT S3C2410_GPIOREG(0x24)
#define S3C2410_GPCUP S3C2410_GPIOREG(0x28)
#define S3C2400_GPCCON S3C2410_GPIOREG(0x14)
#define S3C2400_GPCDAT S3C2410_GPIOREG(0x18)
#define S3C2400_GPCUP S3C2410_GPIOREG(0x1C)
#define S3C2410_GPC0_LEND (0x02 << 0)
#define S3C2400_GPC0_VD0 (0x02 << 0)
#define S3C2410_GPC1_VCLK (0x02 << 2)
#define S3C2400_GPC1_VD1 (0x02 << 2)
#define S3C2410_GPC2_VLINE (0x02 << 4)
#define S3C2400_GPC2_VD2 (0x02 << 4)
#define S3C2410_GPC3_VFRAME (0x02 << 6)
#define S3C2400_GPC3_VD3 (0x02 << 6)
#define S3C2410_GPC4_VM (0x02 << 8)
#define S3C2400_GPC4_VD4 (0x02 << 8)
#define S3C2410_GPC5_LCDVF0 (0x02 << 10)
#define S3C2400_GPC5_VD5 (0x02 << 10)
#define S3C2410_GPC6_LCDVF1 (0x02 << 12)
#define S3C2400_GPC6_VD6 (0x02 << 12)
#define S3C2410_GPC7_LCDVF2 (0x02 << 14)
#define S3C2400_GPC7_VD7 (0x02 << 14)
#define S3C2410_GPC8_VD0 (0x02 << 16)
#define S3C2400_GPC8_VD8 (0x02 << 16)
#define S3C2410_GPC9_VD1 (0x02 << 18)
#define S3C2400_GPC9_VD9 (0x02 << 18)
#define S3C2410_GPC10_VD2 (0x02 << 20)
#define S3C2400_GPC10_VD10 (0x02 << 20)
#define S3C2410_GPC11_VD3 (0x02 << 22)
#define S3C2400_GPC11_VD11 (0x02 << 22)
#define S3C2410_GPC12_VD4 (0x02 << 24)
#define S3C2400_GPC12_VD12 (0x02 << 24)
#define S3C2410_GPC13_VD5 (0x02 << 26)
#define S3C2400_GPC13_VD13 (0x02 << 26)
#define S3C2410_GPC14_VD6 (0x02 << 28)
#define S3C2400_GPC14_VD14 (0x02 << 28)
#define S3C2410_GPC15_VD7 (0x02 << 30)
#define S3C2400_GPC15_VD15 (0x02 << 30)
#define S3C2410_GPC_PUPDIS(x) (1<<(x))
/*
@ -269,8 +147,6 @@
* almost identical setup to port b, but the special functions are mostly
* to do with the video system's data.
*
* S3C2400: Port D consists of 11 GPIO/Special function
*
* almost identical setup to port c
*/
@ -278,46 +154,31 @@
#define S3C2410_GPDDAT S3C2410_GPIOREG(0x34)
#define S3C2410_GPDUP S3C2410_GPIOREG(0x38)
#define S3C2400_GPDCON S3C2410_GPIOREG(0x20)
#define S3C2400_GPDDAT S3C2410_GPIOREG(0x24)
#define S3C2400_GPDUP S3C2410_GPIOREG(0x28)
#define S3C2410_GPD0_VD8 (0x02 << 0)
#define S3C2400_GPD0_VFRAME (0x02 << 0)
#define S3C2442_GPD0_nSPICS1 (0x03 << 0)
#define S3C2410_GPD1_VD9 (0x02 << 2)
#define S3C2400_GPD1_VM (0x02 << 2)
#define S3C2442_GPD1_SPICLK1 (0x03 << 2)
#define S3C2410_GPD2_VD10 (0x02 << 4)
#define S3C2400_GPD2_VLINE (0x02 << 4)
#define S3C2410_GPD3_VD11 (0x02 << 6)
#define S3C2400_GPD3_VCLK (0x02 << 6)
#define S3C2410_GPD4_VD12 (0x02 << 8)
#define S3C2400_GPD4_LEND (0x02 << 8)
#define S3C2410_GPD5_VD13 (0x02 << 10)
#define S3C2400_GPD5_TOUT0 (0x02 << 10)
#define S3C2410_GPD6_VD14 (0x02 << 12)
#define S3C2400_GPD6_TOUT1 (0x02 << 12)
#define S3C2410_GPD7_VD15 (0x02 << 14)
#define S3C2400_GPD7_TOUT2 (0x02 << 14)
#define S3C2410_GPD8_VD16 (0x02 << 16)
#define S3C2400_GPD8_TOUT3 (0x02 << 16)
#define S3C2440_GPD8_SPIMISO1 (0x03 << 16)
#define S3C2410_GPD9_VD17 (0x02 << 18)
#define S3C2400_GPD9_TCLK0 (0x02 << 18)
#define S3C2440_GPD9_SPIMOSI1 (0x03 << 18)
#define S3C2410_GPD10_VD18 (0x02 << 20)
#define S3C2400_GPD10_nWAIT (0x02 << 20)
#define S3C2440_GPD10_SPICLK1 (0x03 << 20)
#define S3C2410_GPD11_VD19 (0x02 << 22)
@ -340,9 +201,6 @@
* again, the same as port B, but dealing with I2S, SDI, and
* more miscellaneous functions
*
* S3C2400:
* Port E consists of 12 GPIO/Special function
*
* GPIO / interrupt inputs
*/
@ -350,74 +208,51 @@
#define S3C2410_GPEDAT S3C2410_GPIOREG(0x44)
#define S3C2410_GPEUP S3C2410_GPIOREG(0x48)
#define S3C2400_GPECON S3C2410_GPIOREG(0x2C)
#define S3C2400_GPEDAT S3C2410_GPIOREG(0x30)
#define S3C2400_GPEUP S3C2410_GPIOREG(0x34)
#define S3C2410_GPE0_I2SLRCK (0x02 << 0)
#define S3C2443_GPE0_AC_nRESET (0x03 << 0)
#define S3C2400_GPE0_EINT0 (0x02 << 0)
#define S3C2410_GPE0_MASK (0x03 << 0)
#define S3C2410_GPE1_I2SSCLK (0x02 << 2)
#define S3C2443_GPE1_AC_SYNC (0x03 << 2)
#define S3C2400_GPE1_EINT1 (0x02 << 2)
#define S3C2400_GPE1_nSS (0x03 << 2)
#define S3C2410_GPE1_MASK (0x03 << 2)
#define S3C2410_GPE2_CDCLK (0x02 << 4)
#define S3C2443_GPE2_AC_BITCLK (0x03 << 4)
#define S3C2400_GPE2_EINT2 (0x02 << 4)
#define S3C2400_GPE2_I2SSDI (0x03 << 4)
#define S3C2410_GPE3_I2SSDI (0x02 << 6)
#define S3C2443_GPE3_AC_SDI (0x03 << 6)
#define S3C2400_GPE3_EINT3 (0x02 << 6)
#define S3C2400_GPE3_nCTS1 (0x03 << 6)
#define S3C2410_GPE3_nSS0 (0x03 << 6)
#define S3C2410_GPE3_MASK (0x03 << 6)
#define S3C2410_GPE4_I2SSDO (0x02 << 8)
#define S3C2443_GPE4_AC_SDO (0x03 << 8)
#define S3C2400_GPE4_EINT4 (0x02 << 8)
#define S3C2400_GPE4_nRTS1 (0x03 << 8)
#define S3C2410_GPE4_I2SSDI (0x03 << 8)
#define S3C2410_GPE4_MASK (0x03 << 8)
#define S3C2410_GPE5_SDCLK (0x02 << 10)
#define S3C2443_GPE5_SD1_CLK (0x02 << 10)
#define S3C2400_GPE5_EINT5 (0x02 << 10)
#define S3C2400_GPE5_TCLK1 (0x03 << 10)
#define S3C2443_GPE5_AC_BITCLK (0x03 << 10)
#define S3C2410_GPE6_SDCMD (0x02 << 12)
#define S3C2443_GPE6_SD1_CMD (0x02 << 12)
#define S3C2443_GPE6_AC_SDI (0x03 << 12)
#define S3C2400_GPE6_EINT6 (0x02 << 12)
#define S3C2410_GPE7_SDDAT0 (0x02 << 14)
#define S3C2443_GPE5_SD1_DAT0 (0x02 << 14)
#define S3C2443_GPE7_AC_SDO (0x03 << 14)
#define S3C2400_GPE7_EINT7 (0x02 << 14)
#define S3C2410_GPE8_SDDAT1 (0x02 << 16)
#define S3C2443_GPE8_SD1_DAT1 (0x02 << 16)
#define S3C2443_GPE8_AC_SYNC (0x03 << 16)
#define S3C2400_GPE8_nXDACK0 (0x02 << 16)
#define S3C2410_GPE9_SDDAT2 (0x02 << 18)
#define S3C2443_GPE9_SD1_DAT2 (0x02 << 18)
#define S3C2443_GPE9_AC_nRESET (0x03 << 18)
#define S3C2400_GPE9_nXDACK1 (0x02 << 18)
#define S3C2400_GPE9_nXBACK (0x03 << 18)
#define S3C2410_GPE10_SDDAT3 (0x02 << 20)
#define S3C2443_GPE10_SD1_DAT3 (0x02 << 20)
#define S3C2400_GPE10_nXDREQ0 (0x02 << 20)
#define S3C2410_GPE11_SPIMISO0 (0x02 << 22)
#define S3C2400_GPE11_nXDREQ1 (0x02 << 22)
#define S3C2400_GPE11_nXBREQ (0x03 << 22)
#define S3C2410_GPE12_SPIMOSI0 (0x02 << 24)
@ -447,9 +282,6 @@
*
* pull up works like all other ports.
*
* S3C2400:
* Port F consists of 7 GPIO/Special function
*
* GPIO/serial/misc pins
*/
@ -457,37 +289,14 @@
#define S3C2410_GPFDAT S3C2410_GPIOREG(0x54)
#define S3C2410_GPFUP S3C2410_GPIOREG(0x58)
#define S3C2400_GPFCON S3C2410_GPIOREG(0x38)
#define S3C2400_GPFDAT S3C2410_GPIOREG(0x3C)
#define S3C2400_GPFUP S3C2410_GPIOREG(0x40)
#define S3C2410_GPF0_EINT0 (0x02 << 0)
#define S3C2400_GPF0_RXD0 (0x02 << 0)
#define S3C2410_GPF1_EINT1 (0x02 << 2)
#define S3C2400_GPF1_RXD1 (0x02 << 2)
#define S3C2400_GPF1_IICSDA (0x03 << 2)
#define S3C2410_GPF2_EINT2 (0x02 << 4)
#define S3C2400_GPF2_TXD0 (0x02 << 4)
#define S3C2410_GPF3_EINT3 (0x02 << 6)
#define S3C2400_GPF3_TXD1 (0x02 << 6)
#define S3C2400_GPF3_IICSCL (0x03 << 6)
#define S3C2410_GPF4_EINT4 (0x02 << 8)
#define S3C2400_GPF4_nRTS0 (0x02 << 8)
#define S3C2400_GPF4_nXBACK (0x03 << 8)
#define S3C2410_GPF5_EINT5 (0x02 << 10)
#define S3C2400_GPF5_nCTS0 (0x02 << 10)
#define S3C2400_GPF5_nXBREQ (0x03 << 10)
#define S3C2410_GPF6_EINT6 (0x02 << 12)
#define S3C2400_GPF6_CLKOUT (0x02 << 12)
#define S3C2410_GPF7_EINT7 (0x02 << 14)
#define S3C2410_GPF_PUPDIS(x) (1<<(x))
/* S3C2410:
@ -497,62 +306,38 @@
* 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
*
* pull up works like all other ports.
*
* S3C2400:
* Port G consists of 10 GPIO/Special function
*/
#define S3C2410_GPGCON S3C2410_GPIOREG(0x60)
#define S3C2410_GPGDAT S3C2410_GPIOREG(0x64)
#define S3C2410_GPGUP S3C2410_GPIOREG(0x68)
#define S3C2400_GPGCON S3C2410_GPIOREG(0x44)
#define S3C2400_GPGDAT S3C2410_GPIOREG(0x48)
#define S3C2400_GPGUP S3C2410_GPIOREG(0x4C)
#define S3C2410_GPG0_EINT8 (0x02 << 0)
#define S3C2400_GPG0_I2SLRCK (0x02 << 0)
#define S3C2410_GPG1_EINT9 (0x02 << 2)
#define S3C2400_GPG1_I2SSCLK (0x02 << 2)
#define S3C2410_GPG2_EINT10 (0x02 << 4)
#define S3C2410_GPG2_nSS0 (0x03 << 4)
#define S3C2400_GPG2_CDCLK (0x02 << 4)
#define S3C2410_GPG3_EINT11 (0x02 << 6)
#define S3C2410_GPG3_nSS1 (0x03 << 6)
#define S3C2400_GPG3_I2SSDO (0x02 << 6)
#define S3C2400_GPG3_I2SSDI (0x03 << 6)
#define S3C2410_GPG4_EINT12 (0x02 << 8)
#define S3C2400_GPG4_MMCCLK (0x02 << 8)
#define S3C2400_GPG4_I2SSDI (0x03 << 8)
#define S3C2410_GPG4_LCDPWREN (0x03 << 8)
#define S3C2443_GPG4_LCDPWRDN (0x03 << 8)
#define S3C2410_GPG5_EINT13 (0x02 << 10)
#define S3C2400_GPG5_MMCCMD (0x02 << 10)
#define S3C2400_GPG5_IICSDA (0x03 << 10)
#define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */
#define S3C2410_GPG6_EINT14 (0x02 << 12)
#define S3C2400_GPG6_MMCDAT (0x02 << 12)
#define S3C2400_GPG6_IICSCL (0x03 << 12)
#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)
#define S3C2410_GPG7_EINT15 (0x02 << 14)
#define S3C2410_GPG7_SPICLK1 (0x03 << 14)
#define S3C2400_GPG7_SPIMISO (0x02 << 14)
#define S3C2400_GPG7_IICSDA (0x03 << 14)
#define S3C2410_GPG8_EINT16 (0x02 << 16)
#define S3C2400_GPG8_SPIMOSI (0x02 << 16)
#define S3C2400_GPG8_IICSCL (0x03 << 16)
#define S3C2410_GPG9_EINT17 (0x02 << 18)
#define S3C2400_GPG9_SPICLK (0x02 << 18)
#define S3C2400_GPG9_MMCCLK (0x03 << 18)
#define S3C2410_GPG10_EINT18 (0x02 << 20)
@ -660,7 +445,6 @@
#define S3C2443_GPMUP S3C2410_GPIOREG(0x108)
/* miscellaneous control */
#define S3C2400_MISCCR S3C2410_GPIOREG(0x54)
#define S3C2410_MISCCR S3C2410_GPIOREG(0x80)
#define S3C2410_DCLKCON S3C2410_GPIOREG(0x84)
@ -674,14 +458,6 @@
#define S3C2410_MISCCR_SPUCR_LEN (0<<1)
#define S3C2410_MISCCR_SPUCR_LDIS (1<<1)
#define S3C2400_MISCCR_SPUCR_LEN (0<<0)
#define S3C2400_MISCCR_SPUCR_LDIS (1<<0)
#define S3C2400_MISCCR_SPUCR_HEN (0<<1)
#define S3C2400_MISCCR_SPUCR_HDIS (1<<1)
#define S3C2400_MISCCR_HZ_STOPEN (0<<2)
#define S3C2400_MISCCR_HZ_STOPPREV (1<<2)
#define S3C2410_MISCCR_USBDEV (0<<3)
#define S3C2410_MISCCR_USBHOST (1<<3)
@ -728,7 +504,6 @@
*
* Samsung datasheet p9-25
*/
#define S3C2400_EXTINT0 S3C2410_GPIOREG(0x58)
#define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88)
#define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C)
#define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90)
@ -796,22 +571,6 @@
#define S3C2410_GSTATUS2_OFFRESET (1<<1)
#define S3C2410_GSTATUS2_PONRESET (1<<0)
/* open drain control register */
#define S3C2400_OPENCR S3C2410_GPIOREG(0x50)
#define S3C2400_OPENCR_OPC_RXD1DIS (0<<0)
#define S3C2400_OPENCR_OPC_RXD1EN (1<<0)
#define S3C2400_OPENCR_OPC_TXD1DIS (0<<1)
#define S3C2400_OPENCR_OPC_TXD1EN (1<<1)
#define S3C2400_OPENCR_OPC_CMDDIS (0<<2)
#define S3C2400_OPENCR_OPC_CMDEN (1<<2)
#define S3C2400_OPENCR_OPC_DATDIS (0<<3)
#define S3C2400_OPENCR_OPC_DATEN (1<<3)
#define S3C2400_OPENCR_OPC_MISODIS (0<<4)
#define S3C2400_OPENCR_OPC_MISOEN (1<<4)
#define S3C2400_OPENCR_OPC_MOSIDIS (0<<5)
#define S3C2400_OPENCR_OPC_MOSIEN (1<<5)
/* 2412/2413 sleep configuration registers */
#define S3C2412_GPBSLPCON S3C2410_GPIOREG(0x1C)

28
arch/arm/mach-s3c2410/include/mach/regs-mem.h
View File

@ -145,29 +145,8 @@
#define S3C2410_BANKCON_Tacs_SHIFT (13)
#define S3C2410_BANKCON_SRAM (0x0 << 15)
#define S3C2400_BANKCON_EDODRAM (0x2 << 15)
#define S3C2410_BANKCON_SDRAM (0x3 << 15)
/* next bits only for EDO DRAM in 6,7 */
#define S3C2400_BANKCON_EDO_Trcd1 (0x00 << 4)
#define S3C2400_BANKCON_EDO_Trcd2 (0x01 << 4)
#define S3C2400_BANKCON_EDO_Trcd3 (0x02 << 4)
#define S3C2400_BANKCON_EDO_Trcd4 (0x03 << 4)
/* CAS pulse width */
#define S3C2400_BANKCON_EDO_PULSE1 (0x00 << 3)
#define S3C2400_BANKCON_EDO_PULSE2 (0x01 << 3)
/* CAS pre-charge */
#define S3C2400_BANKCON_EDO_TCP1 (0x00 << 2)
#define S3C2400_BANKCON_EDO_TCP2 (0x01 << 2)
/* control column address select */
#define S3C2400_BANKCON_EDO_SCANb8 (0x00 << 0)
#define S3C2400_BANKCON_EDO_SCANb9 (0x01 << 0)
#define S3C2400_BANKCON_EDO_SCANb10 (0x02 << 0)
#define S3C2400_BANKCON_EDO_SCANb11 (0x03 << 0)
/* next bits only for SDRAM in 6,7 */
#define S3C2410_BANKCON_Trcd2 (0x00 << 2)
#define S3C2410_BANKCON_Trcd3 (0x01 << 2)
@ -194,12 +173,6 @@
#define S3C2410_REFRESH_TRP_3clk (1<<20)
#define S3C2410_REFRESH_TRP_4clk (2<<20)
#define S3C2400_REFRESH_DRAM_TRP_MASK (3<<20)
#define S3C2400_REFRESH_DRAM_TRP_1_5clk (0<<20)
#define S3C2400_REFRESH_DRAM_TRP_2_5clk (1<<20)
#define S3C2400_REFRESH_DRAM_TRP_3_5clk (2<<20)
#define S3C2400_REFRESH_DRAM_TRP_4_5clk (3<<20)
#define S3C2410_REFRESH_TSRC_MASK (3<<18)
#define S3C2410_REFRESH_TSRC_4clk (0<<18)
#define S3C2410_REFRESH_TSRC_5clk (1<<18)
@ -222,7 +195,6 @@
#define S3C2410_BANKSIZE_4M (0x5 << 0)
#define S3C2410_BANKSIZE_2M (0x4 << 0)
#define S3C2410_BANKSIZE_MASK (0x7 << 0)
#define S3C2400_BANKSIZE_MASK (0x4 << 0)
#define S3C2410_BANKSIZE_SCLK_EN (1<<4)
#define S3C2410_BANKSIZE_SCKE_EN (1<<5)
#define S3C2410_BANKSIZE_BURST (1<<7)

2
arch/arm/mach-s3c2412/Kconfig
View File

@ -15,7 +15,7 @@ config CPU_S3C2412
config CPU_S3C2412_ONLY
bool
depends on ARCH_S3C2410 && !CPU_S3C2400 && !CPU_S3C2410 && \
depends on ARCH_S3C2410 && !CPU_S3C2410 && \
!CPU_S3C2416 && !CPU_S3C2440 && !CPU_S3C2442 && \
!CPU_S3C2443 && CPU_S3C2412
default y if CPU_S3C2412

27
arch/arm/mach-s3c24a0/include/mach/debug-macro.S
View File

@ -1,27 +0,0 @@
/* arch/arm/mach-s3c2410/include/mach/debug-macro.S
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* pull in the relevant register and map files. */
#include <mach/map.h>
#include <plat/regs-serial.h>
.macro addruart, rp, rv
ldr \rp, = S3C24XX_PA_UART
ldr \rv, = S3C24XX_VA_UART
#if CONFIG_DEBUG_S3C_UART != 0
add \rp, \rp, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
add \rv, \rv, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
#endif
.endm
/* include the reset of the code which will do the work, we're only
* compiling for a single cpu processor type so the default of s3c2440
* will be fine with us.
*/
#include <plat/debug-macro.S>

18
arch/arm/mach-s3c24a0/include/mach/io.h
View File

@ -1,18 +0,0 @@
/* arch/arm/mach-s3c24a0/include/mach/io.h
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben-linux@fluff.org>
*
* Default IO routines for S3C24A0
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
/* No current ISA/PCI bus support. */
#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
#define IO_SPACE_LIMIT (0xFFFFFFFF)
#endif

117
arch/arm/mach-s3c24a0/include/mach/irqs.h
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@ -1,117 +0,0 @@
/* linux/arch/arm/mach-s3c24a0/include/mach/irqs.h
*
* Copyright (c) 2003-2005 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_24A0_IRQS_H
#define __ASM_ARCH_24A0_IRQS_H __FILE__
#define IRQ_EINT0t2 S3C2410_IRQ(0) /* 16 */
/* for generic entry-macro.S */
#define IRQ_EINT0 IRQ_EINT0t2
#define IRQ_EINT3t6 S3C2410_IRQ(1)
#define IRQ_EINT7t10 S3C2410_IRQ(2)
#define IRQ_EINT11t14 S3C2410_IRQ(3)
#define IRQ_EINT15t18 S3C2410_IRQ(4) /* 20 */
#define IRQ_TICK S3C2410_IRQ(5)
#define IRQ_DCTQ S3C2410_IRQ(6)
#define IRQ_MC S3C2410_IRQ(7)
#define IRQ_ME S3C2410_IRQ(8) /* 24 */
#define IRQ_KEYPAD S3C2410_IRQ(9)
#define IRQ_TIMER0 S3C2410_IRQ(10)
#define IRQ_TIMER1 S3C2410_IRQ(11)
#define IRQ_TIMER2 S3C2410_IRQ(12)
#define IRQ_TIMER3_4 S3C2410_IRQ(13)
#define IRQ_OS_TIMER IRQ_TIMER3_4
#define IRQ_LCD S3C2410_IRQ(14)
#define IRQ_CAM_C S3C2410_IRQ(15)
#define IRQ_WDT_BATFLT S3C2410_IRQ(16) /* 32 */
#define IRQ_UART0 S3C2410_IRQ(17)
#define IRQ_CAM_P S3C2410_IRQ(18)
#define IRQ_MODEM S3C2410_IRQ(19)
#define IRQ_DMA S3C2410_IRQ(20)
#define IRQ_SDI S3C2410_IRQ(21)
#define IRQ_SPI0 S3C2410_IRQ(22)
#define IRQ_UART1 S3C2410_IRQ(23)
#define IRQ_AC97_NFLASH S3C2410_IRQ(24) /* 40 */
#define IRQ_USBD S3C2410_IRQ(25)
#define IRQ_USBH S3C2410_IRQ(26)
#define IRQ_IIC S3C2410_IRQ(27)
#define IRQ_IRDA_MSTICK S3C2410_IRQ(28) /* 44 */
#define IRQ_VLX_SPI1 S3C2410_IRQ(29)
#define IRQ_RTC S3C2410_IRQ(30) /* 46 */
#define IRQ_ADC_PEN S3C2410_IRQ(31)
/* interrupts generated from the external interrupts sources */
#define IRQ_EINT00 S3C2410_IRQ(32) /* 48 */
#define IRQ_EINT1 S3C2410_IRQ(33)
#define IRQ_EINT2 S3C2410_IRQ(34)
#define IRQ_EINT3 S3C2410_IRQ(35)
#define IRQ_EINT4 S3C2410_IRQ(36)
#define IRQ_EINT5 S3C2410_IRQ(37)
#define IRQ_EINT6 S3C2410_IRQ(38)
#define IRQ_EINT7 S3C2410_IRQ(39)
#define IRQ_EINT8 S3C2410_IRQ(40)
#define IRQ_EINT9 S3C2410_IRQ(41)
#define IRQ_EINT10 S3C2410_IRQ(42)
#define IRQ_EINT11 S3C2410_IRQ(43)
#define IRQ_EINT12 S3C2410_IRQ(44)
#define IRQ_EINT13 S3C2410_IRQ(45)
#define IRQ_EINT14 S3C2410_IRQ(46)
#define IRQ_EINT15 S3C2410_IRQ(47)
#define IRQ_EINT16 S3C2410_IRQ(48)
#define IRQ_EINT17 S3C2410_IRQ(49)
#define IRQ_EINT18 S3C2410_IRQ(50)
#define IRQ_EINT_BIT(x) ((x) - IRQ_EINT00)
/* SUB IRQS */
#define IRQ_S3CUART_RX0 S3C2410_IRQ(51) /* 67 */
#define IRQ_S3CUART_TX0 S3C2410_IRQ(52)
#define IRQ_S3CUART_ERR0 S3C2410_IRQ(53)
#define IRQ_S3CUART_RX1 S3C2410_IRQ(54)
#define IRQ_S3CUART_TX1 S3C2410_IRQ(55)
#define IRQ_S3CUART_ERR1 S3C2410_IRQ(56)
#define IRQ_S3CUART_RX2 (0x0)
#define IRQ_S3CUART_TX2 (0x0)
#define IRQ_S3CUART_ERR2 (0x0)
#define IRQ_IRDA S3C2410_IRQ(57)
#define IRQ_MSTICK S3C2410_IRQ(58)
#define IRQ_RESERVED0 S3C2410_IRQ(59)
#define IRQ_RESERVED1 S3C2410_IRQ(60)
#define IRQ_RESERVED2 S3C2410_IRQ(61)
#define IRQ_TIMER3 S3C2410_IRQ(62)
#define IRQ_TIMER4 S3C2410_IRQ(63)
#define IRQ_WDT S3C2410_IRQ(64)
#define IRQ_BATFLT S3C2410_IRQ(65)
#define IRQ_POST S3C2410_IRQ(66)
#define IRQ_DISP_FIFO S3C2410_IRQ(67)
#define IRQ_PENUP S3C2410_IRQ(68)
#define IRQ_PENDN S3C2410_IRQ(69)
#define IRQ_ADC S3C2410_IRQ(70)
#define IRQ_DISP_FRAME S3C2410_IRQ(71)
#define IRQ_NFLASH S3C2410_IRQ(72)
#define IRQ_AC97 S3C2410_IRQ(73)
#define IRQ_SPI1 S3C2410_IRQ(74)
#define IRQ_VLX S3C2410_IRQ(75)
#define IRQ_DMA0 S3C2410_IRQ(76)
#define IRQ_DMA1 S3C2410_IRQ(77)
#define IRQ_DMA2 S3C2410_IRQ(78)
#define IRQ_DMA3 S3C2410_IRQ(79)
#define IRQ_TC (0x0)
#define NR_IRQS (IRQ_DMA3+1)
#endif /* __ASM_ARCH_24A0_IRQS_H */

86
arch/arm/mach-s3c24a0/include/mach/map.h
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@ -1,86 +0,0 @@
/* linux/arch/arm/mach-s3c24a0/include/mach/map.h
*
* Copyright 2003-2007 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C24A0 - Memory map definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_24A0_MAP_H
#define __ASM_ARCH_24A0_MAP_H __FILE__
#include <plat/map-base.h>
#include <plat/map.h>
#define S3C24A0_PA_IO_BASE (0x40000000)
#define S3C24A0_PA_CLKPWR (0x40000000)
#define S3C24A0_PA_IRQ (0x40200000)
#define S3C24A0_PA_DMA (0x40400000)
#define S3C24A0_PA_MEMCTRL (0x40C00000)
#define S3C24A0_PA_NAND (0x40C00000)
#define S3C24A0_PA_SROM (0x40C20000)
#define S3C24A0_PA_SDRAM (0x40C40000)
#define S3C24A0_PA_BUSM (0x40CE0000)
#define S3C24A0_PA_USBHOST (0x41000000)
#define S3C24A0_PA_MODEMIF (0x41180000)
#define S3C24A0_PA_IRDA (0x41800000)
#define S3C24A0_PA_TIMER (0x44000000)
#define S3C24A0_PA_WATCHDOG (0x44100000)
#define S3C24A0_PA_RTC (0x44200000)
#define S3C24A0_PA_UART (0x44400000)
#define S3C24A0_PA_UART0 (S3C24A0_PA_UART)
#define S3C24A0_PA_UART1 (S3C24A0_PA_UART + 0x4000)
#define S3C24A0_PA_SPI (0x44500000)
#define S3C24A0_PA_IIC (0x44600000)
#define S3C24A0_PA_IIS (0x44700000)
#define S3C24A0_PA_GPIO (0x44800000)
#define S3C24A0_PA_KEYIF (0x44900000)
#define S3C24A0_PA_USBDEV (0x44A00000)
#define S3C24A0_PA_AC97 (0x45000000)
#define S3C24A0_PA_ADC (0x45800000)
#define S3C24A0_PA_SDI (0x46000000)
#define S3C24A0_PA_MS (0x46100000)
#define S3C24A0_PA_LCD (0x4A000000)
#define S3C24A0_PA_VPOST (0x4A100000)
/* physical addresses of all the chip-select areas */
#define S3C24A0_CS0 (0x00000000)
#define S3C24A0_CS1 (0x04000000)
#define S3C24A0_CS2 (0x08000000)
#define S3C24A0_CS3 (0x0C000000)
#define S3C24A0_CS4 (0x10000000)
#define S3C24A0_CS5 (0x40000000)
#define S3C24A0_SDRAM_PA (S3C24A0_CS4)
/* Use a single interface for common resources between S3C24XX cpus */
#define S3C24XX_PA_IRQ S3C24A0_PA_IRQ
#define S3C24XX_PA_MEMCTRL S3C24A0_PA_MEMCTRL
#define S3C24XX_PA_USBHOST S3C24A0_PA_USBHOST
#define S3C24XX_PA_DMA S3C24A0_PA_DMA
#define S3C24XX_PA_CLKPWR S3C24A0_PA_CLKPWR
#define S3C24XX_PA_LCD S3C24A0_PA_LCD
#define S3C24XX_PA_UART S3C24A0_PA_UART
#define S3C24XX_PA_TIMER S3C24A0_PA_TIMER
#define S3C24XX_PA_USBDEV S3C24A0_PA_USBDEV
#define S3C24XX_PA_WATCHDOG S3C24A0_PA_WATCHDOG
#define S3C24XX_PA_IIS S3C24A0_PA_IIS
#define S3C24XX_PA_GPIO S3C24A0_PA_GPIO
#define S3C24XX_PA_RTC S3C24A0_PA_RTC
#define S3C24XX_PA_ADC S3C24A0_PA_ADC
#define S3C24XX_PA_SPI S3C24A0_PA_SPI
#define S3C24XX_PA_SDI S3C24A0_PA_SDI
#define S3C24XX_PA_NAND S3C24A0_PA_NAND
#define S3C_PA_UART S3C24A0_PA_UART
#define S3C_PA_IIC S3C24A0_PA_IIC
#define S3C_PA_NAND S3C24XX_PA_NAND
#endif /* __ASM_ARCH_24A0_MAP_H */

21
arch/arm/mach-s3c24a0/include/mach/memory.h
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@ -1,21 +0,0 @@
/* linux/arch/arm/mach-s3c24a0/include/mach/memory.h
* from linux/include/asm-arm/arch-rpc/memory.h
*
* Copyright (C) 1996,1997,1998 Russell King.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_24A0_MEMORY_H
#define __ASM_ARCH_24A0_MEMORY_H __FILE__
#define PLAT_PHYS_OFFSET UL(0x10000000)
#define __virt_to_bus(x) __virt_to_phys(x)
#define __bus_to_virt(x) __phys_to_virt(x)
#define __pfn_to_bus(x) __pfn_to_phys(x)
#define __bus_to_pfn(x) __phys_to_pfn(x)
#endif

88
arch/arm/mach-s3c24a0/include/mach/regs-clock.h
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@ -1,88 +0,0 @@
/* linux/arch/arm/mach-s3c24a0/include/mach/regs-clock.h
*
* Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* S3C24A0 clock register definitions
*/
#ifndef __ASM_ARCH_24A0_REGS_CLOCK_H
#define __ASM_ARCH_24A0_REGS_CLOCK_H __FILE__
#define S3C24A0_MPLLCON S3C2410_CLKREG(0x10)
#define S3C24A0_UPLLCON S3C2410_CLKREG(0x14)
#define S3C24A0_CLKCON S3C2410_CLKREG(0x20)
#define S3C24A0_CLKSRC S3C2410_CLKREG(0x24)
#define S3C24A0_CLKDIVN S3C2410_CLKREG(0x28)
/* CLKCON register bits */
#define S3C24A0_CLKCON_VLX (1<<29)
#define S3C24A0_CLKCON_VPOST (1<<28)
#define S3C24A0_CLKCON_WDT (1<<27) /* reserved */
#define S3C24A0_CLKCON_MPEGDCTQ (1<<26)
#define S3C24A0_CLKCON_VPOSTIF (1<<25)
#define S3C24A0_CLKCON_MPEG4IF (1<<24)
#define S3C24A0_CLKCON_CAM_UPLL (1<<23)
#define S3C24A0_CLKCON_LCDC (1<<22)
#define S3C24A0_CLKCON_CAM_HCLK (1<<21)
#define S3C24A0_CLKCON_MPEG4 (1<<20)
#define S3C24A0_CLKCON_KEYPAD (1<<19)
#define S3C24A0_CLKCON_ADC (1<<18)
#define S3C24A0_CLKCON_SDI (1<<17)
#define S3C24A0_CLKCON_MS (1<<16) /* memory stick */
#define S3C24A0_CLKCON_USBD (1<<15)
#define S3C24A0_CLKCON_GPIO (1<<14)
#define S3C24A0_CLKCON_IIS (1<<13)
#define S3C24A0_CLKCON_IIC (1<<12)
#define S3C24A0_CLKCON_SPI (1<<11)
#define S3C24A0_CLKCON_UART1 (1<<10)
#define S3C24A0_CLKCON_UART0 (1<<9)
#define S3C24A0_CLKCON_PWMT (1<<8)
#define S3C24A0_CLKCON_USBH (1<<7)
#define S3C24A0_CLKCON_AC97 (1<<6)
#define S3C24A0_CLKCON_IrDA (1<<4)
#define S3C24A0_CLKCON_IDLE (1<<2)
#define S3C24A0_CLKCON_MON (1<<1)
#define S3C24A0_CLKCON_STOP (1<<0)
/* CLKSRC register bits */
#define S3C24A0_CLKSRC_OSC (1<<8) /* CLKSRC */
#define S3C24A0_CLKSRC_UPLL (1<<7)
#define S3C24A0_CLKSRC_MPLL (1<<5)
#define S3C24A0_CLKSRC_EXT (1<<4)
/* Use a single interface with the common code, for s3c24xx */
#define S3C2410_MPLLCON S3C24A0_MPLLCON
#define S3C2410_UPLLCON S3C24A0_UPLLCON
#define S3C2410_CLKCON S3C24A0_CLKCON
#define S3C2410_CLKSLOW S3C24A0_CLKSRC
#define S3C2410_CLKDIVN S3C24A0_CLKDIVN
#define S3C2410_CLKCON_IDLE S3C24A0_CLKCON_IDLE
#define S3C2410_CLKCON_POWER S3C24A0_CLKCON_STOP
#define S3C2410_CLKCON_LCDC S3C24A0_CLKCON_LCDC
#define S3C2410_CLKCON_USBH S3C24A0_CLKCON_USBH
#define S3C2410_CLKCON_USBD S3C24A0_CLKCON_USBD
#define S3C2410_CLKCON_PWMT S3C24A0_CLKCON_PWMT
#define S3C2410_CLKCON_SDI S3C24A0_CLKCON_SDI
#define S3C2410_CLKCON_UART0 S3C24A0_CLKCON_UART0
#define S3C2410_CLKCON_UART1 S3C24A0_CLKCON_UART1
#define S3C2410_CLKCON_GPIO S3C24A0_CLKCON_GPIO
#define S3C2410_CLKCON_ADC S3C24A0_CLKCON_ADC
#define S3C2410_CLKCON_IIC S3C24A0_CLKCON_IIC
#define S3C2410_CLKCON_IIS S3C24A0_CLKCON_IIS
#define S3C2410_CLKCON_SPI S3C24A0_CLKCON_SPI
#define S3C2410_CLKSLOW_UCLK_OFF S3C24A0_CLKSRC_UPLL
#define S3C2410_CLKSLOW_MPLL_OFF S3C24A0_CLKSRC_MPLL
#define S3C2410_CLKSLOW_SLOW (0xFF)
#define S3C2410_CLKSLOW_GET_SLOWVAL(x) (0x1)
#endif /* __ASM_ARCH_24A0_REGS_CLOCK_H */

25
arch/arm/mach-s3c24a0/include/mach/regs-irq.h
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@ -1,25 +0,0 @@
/* linux/arch/arm/mach-s3c24a0/include/mach/regs-irq.h
*
* Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
* http://www.simtec.co.uk/products/SWLINUX/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef ___ASM_ARCH_24A0_REGS_IRQ_H
#define ___ASM_ARCH_24A0_REGS_IRQ_H __FILE__
#define S3C2410_EINTMASK S3C2410_EINTREG(0x034)
#define S3C2410_EINTPEND S3C2410_EINTREG(0X038)
#define S3C24XX_EINTMASK S3C24XX_EINTREG(0x034)
#define S3C24XX_EINTPEND S3C24XX_EINTREG(0X038)
#endif /* __ASM_ARCH_24A0_REGS_IRQ_H */

25
arch/arm/mach-s3c24a0/include/mach/system.h
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@ -1,25 +0,0 @@
/* linux/arch/arm/mach-s3c24a0/include/mach/system.h
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C24A0 - System function defines and includes
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <mach/hardware.h>
#include <asm/io.h>
#include <mach/map.h>
static void arch_idle(void)
{
/* currently no specific idle support. */
}
void (*s3c24xx_reset_hook)(void);
#include <asm/plat-s3c24xx/system-reset.h>

15
arch/arm/mach-s3c24a0/include/mach/tick.h
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@ -1,15 +0,0 @@
/* linux/arch/arm/mach-s3c24a0/include/mach/tick.h
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C24A0 - timer tick support
*/
#define SUBSRC_TIMER4 (1 << (IRQ_TIMER4 - IRQ_S3CUART_RX0))
static inline int s3c24xx_ostimer_pending(void)
{
return __raw_readl(S3C2410_SUBSRCPND) & SUBSRC_TIMER4;
}

18
arch/arm/mach-s3c24a0/include/mach/timex.h
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@ -1,18 +0,0 @@
/* linux/arch/arm/mach-s3c24a0/include/mach/timex.h
*
* Copyright (c) 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2410 - time parameters
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_TIMEX_H
#define __ASM_ARCH_TIMEX_H
#define CLOCK_TICK_RATE 12000000
#endif /* __ASM_ARCH_TIMEX_H */

17
arch/arm/mach-s3c24a0/include/mach/vmalloc.h
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@ -1,17 +0,0 @@
/* linux/include/asm-arm/arch-s3c24ao/vmalloc.h
*
* Copyright 2008 Simtec Electronics <linux@simtec.co.uk>
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* S3C24A0 vmalloc definition
*/
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
#define VMALLOC_END 0xF6000000UL
#endif /* __ASM_ARCH_VMALLOC_H */

2
arch/arm/plat-s3c24xx/Kconfig
View File

@ -4,7 +4,7 @@
config PLAT_S3C24XX
bool
depends on ARCH_S3C2410 || ARCH_S3C24A0
depends on ARCH_S3C2410
default y
select NO_IOPORT
select ARCH_REQUIRE_GPIOLIB

15
arch/arm/plat-s3c24xx/cpu.c
View File

@ -46,7 +46,6 @@
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/clock.h>
#include <plat/s3c2400.h>
#include <plat/s3c2410.h>
#include <plat/s3c2412.h>
#include <plat/s3c2416.h>
@ -55,7 +54,6 @@
/* table of supported CPUs */
static const char name_s3c2400[] = "S3C2400";
static const char name_s3c2410[] = "S3C2410";
static const char name_s3c2412[] = "S3C2412";
static const char name_s3c2416[] = "S3C2416/S3C2450";
@ -157,15 +155,6 @@ static struct cpu_table cpu_ids[] __initdata = {
.init = s3c2443_init,
.name = name_s3c2443,
},
{
.idcode = 0x0, /* S3C2400 doesn't have an idcode */
.idmask = 0xffffffff,
.map_io = s3c2400_map_io,
.init_clocks = s3c2400_init_clocks,
.init_uarts = s3c2400_init_uarts,
.init = s3c2400_init,
.name = name_s3c2400
},
};
/* minimal IO mapping */
@ -200,11 +189,7 @@ static unsigned long s3c24xx_read_idcode_v5(void)
static unsigned long s3c24xx_read_idcode_v4(void)
{
#ifndef CONFIG_CPU_S3C2400
return __raw_readl(S3C2410_GSTATUS1);
#else
return 0UL;
#endif
}
/* Hook for arm_pm_restart to ensure we execute the reset code

9
arch/arm/plat-s3c24xx/include/plat/regs-iis.h
View File

@ -64,14 +64,5 @@
#define S3C2410_IISFCON_RXMASK (0x3f)
#define S3C2410_IISFCON_RXSHIFT (0)
#define S3C2400_IISFCON_TXDMA (1<<11)
#define S3C2400_IISFCON_RXDMA (1<<10)
#define S3C2400_IISFCON_TXENABLE (1<<9)
#define S3C2400_IISFCON_RXENABLE (1<<8)
#define S3C2400_IISFCON_TXMASK (0x07 << 4)
#define S3C2400_IISFCON_TXSHIFT (4)
#define S3C2400_IISFCON_RXMASK (0x07)
#define S3C2400_IISFCON_RXSHIFT (0)
#define S3C2410_IISFIFO (0x10)
#endif /* __ASM_ARCH_REGS_IIS_H */

1
arch/arm/plat-s3c24xx/include/plat/regs-spi.h
View File

@ -67,7 +67,6 @@
#define S3C2410_SPPIN_ENMUL (1<<2) /* Multi Master Error detect */
#define S3C2410_SPPIN_RESERVED (1<<1)
#define S3C2400_SPPIN_nCS (1<<1) /* SPI Card Select */
#define S3C2410_SPPIN_KEEP (1<<0) /* Master Out keep */
#define S3C2410_SPPRE (0x0C)

31
arch/arm/plat-s3c24xx/include/plat/s3c2400.h
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@ -1,31 +0,0 @@
/* linux/include/asm-arm/plat-s3c24xx/s3c2400.h
*
* Copyright (c) 2004 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* Header file for S3C2400 cpu support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Modifications:
* 09-Fev-2006 LCVR First version, based on s3c2410.h
*/
#ifdef CONFIG_CPU_S3C2400
extern int s3c2400_init(void);
extern void s3c2400_map_io(void);
extern void s3c2400_init_uarts(struct s3c2410_uartcfg *cfg, int no);
extern void s3c2400_init_clocks(int xtal);
#else
#define s3c2400_init_clocks NULL
#define s3c2400_init_uarts NULL
#define s3c2400_map_io NULL
#define s3c2400_init NULL
#endif

2
arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
View File

@ -140,7 +140,7 @@ extern unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
/* Pull-{up,down} resistor controls.
*
* S3C2410,S3C2440,S3C24A0 = Pull-UP,
* S3C2410,S3C2440 = Pull-UP,
* S3C2412,S3C2413 = Pull-Down
* S3C6400,S3C6410 = Pull-Both [None,Down,Up,Undef]
* S3C2443 = Pull-Both [not same as S3C6400]

8
arch/arm/plat-samsung/include/plat/regs-serial.h
View File

@ -155,14 +155,6 @@
#define S3C2410_UFSTAT_RXMASK (15<<0)
#define S3C2410_UFSTAT_RXSHIFT (0)
/* UFSTAT S3C24A0 */
#define S3C24A0_UFSTAT_TXFULL (1 << 14)
#define S3C24A0_UFSTAT_RXFULL (1 << 6)
#define S3C24A0_UFSTAT_TXMASK (63 << 8)
#define S3C24A0_UFSTAT_TXSHIFT (8)
#define S3C24A0_UFSTAT_RXMASK (63)
#define S3C24A0_UFSTAT_RXSHIFT (0)
/* UFSTAT S3C2443 same as S3C2440 */
#define S3C2440_UFSTAT_TXFULL (1<<14)
#define S3C2440_UFSTAT_RXFULL (1<<6)

15
drivers/tty/serial/Kconfig
View File

@ -457,7 +457,6 @@ config SERIAL_SAMSUNG_UARTS_4
config SERIAL_SAMSUNG_UARTS
int
depends on ARM && PLAT_SAMSUNG
default 2 if ARCH_S3C2400
default 6 if ARCH_S5P6450
default 4 if SERIAL_SAMSUNG_UARTS_4
default 3
@ -489,13 +488,6 @@ config SERIAL_SAMSUNG_CONSOLE
your boot loader about how to pass options to the kernel at
boot time.)
config SERIAL_S3C2400
tristate "Samsung S3C2410 Serial port support"
depends on ARM && SERIAL_SAMSUNG && CPU_S3C2400
default y if CPU_S3C2400
help
Serial port support for the Samsung S3C2400 SoC
config SERIAL_S3C2410
tristate "Samsung S3C2410 Serial port support"
depends on SERIAL_SAMSUNG && CPU_S3C2410
@ -519,13 +511,6 @@ config SERIAL_S3C2440
help
Serial port support for the Samsung S3C2440, S3C2416 and S3C2442 SoC
config SERIAL_S3C24A0
tristate "Samsung S3C24A0 Serial port support"
depends on SERIAL_SAMSUNG && CPU_S3C24A0
default y if CPU_S3C24A0
help
Serial port support for the Samsung S3C24A0 SoC
config SERIAL_S3C6400
tristate "Samsung S3C6400/S3C6410/S5P6440/S5P6450/S5PC100 Serial port support"
depends on SERIAL_SAMSUNG && (CPU_S3C6400 || CPU_S3C6410 || CPU_S5P6440 || CPU_S5P6450 || CPU_S5PC100)

2
drivers/tty/serial/Makefile
View File

@ -38,11 +38,9 @@ obj-$(CONFIG_SERIAL_BCM63XX) += bcm63xx_uart.o
obj-$(CONFIG_SERIAL_BFIN) += bfin_5xx.o
obj-$(CONFIG_SERIAL_BFIN_SPORT) += bfin_sport_uart.o
obj-$(CONFIG_SERIAL_SAMSUNG) += samsung.o
obj-$(CONFIG_SERIAL_S3C2400) += s3c2400.o
obj-$(CONFIG_SERIAL_S3C2410) += s3c2410.o
obj-$(CONFIG_SERIAL_S3C2412) += s3c2412.o
obj-$(CONFIG_SERIAL_S3C2440) += s3c2440.o
obj-$(CONFIG_SERIAL_S3C24A0) += s3c24a0.o
obj-$(CONFIG_SERIAL_S3C6400) += s3c6400.o
obj-$(CONFIG_SERIAL_S5PV210) += s5pv210.o
obj-$(CONFIG_SERIAL_MAX3100) += max3100.o

105
drivers/tty/serial/s3c2400.c
View File

@ -1,105 +0,0 @@
/*
* Driver for Samsung SoC onboard UARTs.
*
* Ben Dooks, Copyright (c) 2003-2005 Simtec Electronics
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <asm/irq.h>
#include <mach/hardware.h>
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include "samsung.h"
static int s3c2400_serial_getsource(struct uart_port *port,
struct s3c24xx_uart_clksrc *clk)
{
clk->divisor = 1;
clk->name = "pclk";
return 0;
}
static int s3c2400_serial_setsource(struct uart_port *port,
struct s3c24xx_uart_clksrc *clk)
{
return 0;
}
static int s3c2400_serial_resetport(struct uart_port *port,
struct s3c2410_uartcfg *cfg)
{
dbg("s3c2400_serial_resetport: port=%p (%08lx), cfg=%p\n",
port, port->mapbase, cfg);
wr_regl(port, S3C2410_UCON, cfg->ucon);
wr_regl(port, S3C2410_ULCON, cfg->ulcon);
/* reset both fifos */
wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
wr_regl(port, S3C2410_UFCON, cfg->ufcon);
return 0;
}
static struct s3c24xx_uart_info s3c2400_uart_inf = {
.name = "Samsung S3C2400 UART",
.type = PORT_S3C2400,
.fifosize = 16,
.rx_fifomask = S3C2410_UFSTAT_RXMASK,
.rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
.rx_fifofull = S3C2410_UFSTAT_RXFULL,
.tx_fifofull = S3C2410_UFSTAT_TXFULL,
.tx_fifomask = S3C2410_UFSTAT_TXMASK,
.tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
.get_clksrc = s3c2400_serial_getsource,
.set_clksrc = s3c2400_serial_setsource,
.reset_port = s3c2400_serial_resetport,
};
static int s3c2400_serial_probe(struct platform_device *dev)
{
return s3c24xx_serial_probe(dev, &s3c2400_uart_inf);
}
static struct platform_driver s3c2400_serial_driver = {
.probe = s3c2400_serial_probe,
.remove = __devexit_p(s3c24xx_serial_remove),
.driver = {
.name = "s3c2400-uart",
.owner = THIS_MODULE,
},
};
s3c24xx_console_init(&s3c2400_serial_driver, &s3c2400_uart_inf);
static inline int s3c2400_serial_init(void)
{
return s3c24xx_serial_init(&s3c2400_serial_driver, &s3c2400_uart_inf);
}
static inline void s3c2400_serial_exit(void)
{
platform_driver_unregister(&s3c2400_serial_driver);
}
module_init(s3c2400_serial_init);
module_exit(s3c2400_serial_exit);
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
MODULE_DESCRIPTION("Samsung S3C2400 SoC Serial port driver");
MODULE_ALIAS("platform:s3c2400-uart");

117
drivers/tty/serial/s3c24a0.c
View File

@ -1,117 +0,0 @@
/*
* Driver for Samsung S3C24A0 SoC onboard UARTs.
*
* Based on drivers/serial/s3c2410.c
*
* Author: Sandeep Patil <sandeep.patil@azingo.com>
*
* Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#include <linux/serial.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <mach/hardware.h>
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include "samsung.h"
static int s3c24a0_serial_setsource(struct uart_port *port,
struct s3c24xx_uart_clksrc *clk)
{
unsigned long ucon = rd_regl(port, S3C2410_UCON);
if (strcmp(clk->name, "uclk") == 0)
ucon |= S3C2410_UCON_UCLK;
else
ucon &= ~S3C2410_UCON_UCLK;
wr_regl(port, S3C2410_UCON, ucon);
return 0;
}
static int s3c24a0_serial_getsource(struct uart_port *port,
struct s3c24xx_uart_clksrc *clk)
{
unsigned long ucon = rd_regl(port, S3C2410_UCON);
clk->divisor = 1;
clk->name = (ucon & S3C2410_UCON_UCLK) ? "uclk" : "pclk";
return 0;
}
static int s3c24a0_serial_resetport(struct uart_port *port,
struct s3c2410_uartcfg *cfg)
{
dbg("s3c24a0_serial_resetport: port=%p (%08lx), cfg=%p\n",
port, port->mapbase, cfg);
wr_regl(port, S3C2410_UCON, cfg->ucon);
wr_regl(port, S3C2410_ULCON, cfg->ulcon);
/* reset both fifos */
wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
wr_regl(port, S3C2410_UFCON, cfg->ufcon);
return 0;
}
static struct s3c24xx_uart_info s3c24a0_uart_inf = {
.name = "Samsung S3C24A0 UART",
.type = PORT_S3C2410,
.fifosize = 16,
.rx_fifomask = S3C24A0_UFSTAT_RXMASK,
.rx_fifoshift = S3C24A0_UFSTAT_RXSHIFT,
.rx_fifofull = S3C24A0_UFSTAT_RXFULL,
.tx_fifofull = S3C24A0_UFSTAT_TXFULL,
.tx_fifomask = S3C24A0_UFSTAT_TXMASK,
.tx_fifoshift = S3C24A0_UFSTAT_TXSHIFT,
.get_clksrc = s3c24a0_serial_getsource,
.set_clksrc = s3c24a0_serial_setsource,
.reset_port = s3c24a0_serial_resetport,
};
static int s3c24a0_serial_probe(struct platform_device *dev)
{
return s3c24xx_serial_probe(dev, &s3c24a0_uart_inf);
}
static struct platform_driver s3c24a0_serial_driver = {
.probe = s3c24a0_serial_probe,
.remove = __devexit_p(s3c24xx_serial_remove),
.driver = {
.name = "s3c24a0-uart",
.owner = THIS_MODULE,
},
};
s3c24xx_console_init(&s3c24a0_serial_driver, &s3c24a0_uart_inf);
static int __init s3c24a0_serial_init(void)
{
return s3c24xx_serial_init(&s3c24a0_serial_driver, &s3c24a0_uart_inf);
}
static void __exit s3c24a0_serial_exit(void)
{
platform_driver_unregister(&s3c24a0_serial_driver);
}
module_init(s3c24a0_serial_init);
module_exit(s3c24a0_serial_exit);