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arm64: dts: exynos: Move FSYS CMU configuration from Exynos5433 dtsi to TM2 dts 

Move initial FSYS CMU (related to USB 3.0 devices) clocks configuration
from generic exynos5433.dtsi file to exynos5433-tm2.dts, as this is
a board specific item.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
Marek Szyprowski 2016-11-17 09:57:59 +01:00 committed by Krzysztof Kozlowski
parent e681376e62
commit 4c9eec94a5
2 changed files with 23 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
View File

@ -158,6 +158,29 @@ thermistor-charger {
};
};
&cmu_fsys {
assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
<&cmu_top CLK_MOUT_SCLK_USBHOST30>,
<&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
<&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
<&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
<&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
<&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>,
<&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>,
<&cmu_top CLK_DIV_SCLK_USBDRD30>,
<&cmu_top CLK_DIV_SCLK_USBHOST30>;
assigned-clock-parents = <&cmu_top CLK_MOUT_BUS_PLL_USER>,
<&cmu_top CLK_MOUT_BUS_PLL_USER>,
<&cmu_top CLK_SCLK_USBDRD30_FSYS>,
<&cmu_top CLK_SCLK_USBHOST30_FSYS>,
<&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
<&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
<&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>,
<&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>;
assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
<66700000>, <66700000>;
};
&cpu0 {
cpu-supply = <&buck3_reg>;
};

28
arch/arm64/boot/dts/exynos/exynos5433.dtsi
View File

@ -1143,14 +1143,6 @@ usbdrd30: usb@15400000 {
clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
<&cmu_fsys CLK_SCLK_USBDRD30>;
clock-names = "usbdrd30", "usbdrd30_susp_clk";
assigned-clocks =
<&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
<&cmu_top CLK_MOUT_SCLK_USBDRD30>,
<&cmu_top CLK_DIV_SCLK_USBDRD30>;
assigned-clock-parents =
<&cmu_top CLK_SCLK_USBDRD30_FSYS>,
<&cmu_top CLK_MOUT_BUS_PLL_USER>;
assigned-clock-rates = <0>, <0>, <66700000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
@ -1174,12 +1166,6 @@ usbdrd30_phy: phy@15500000 {
<&cmu_fsys CLK_SCLK_USBDRD30>;
clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
"itp";
assigned-clocks =
<&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
<&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>;
assigned-clock-parents =
<&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
<&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>;
#phy-cells = <1>;
samsung,pmu-syscon = <&pmu_system_controller>;
status = "disabled";
@ -1194,12 +1180,6 @@ usbhost30_phy: phy@15580000 {
<&cmu_fsys CLK_SCLK_USBHOST30>;
clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
"itp";
assigned-clocks =
<&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
<&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>;
assigned-clock-parents =
<&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
<&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>;
#phy-cells = <1>;
samsung,pmu-syscon = <&pmu_system_controller>;
status = "disabled";
@ -1210,14 +1190,6 @@ usbhost30: usb@15a00000 {
clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
<&cmu_fsys CLK_SCLK_USBHOST30>;
clock-names = "usbdrd30", "usbdrd30_susp_clk";
assigned-clocks =
<&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
<&cmu_top CLK_MOUT_SCLK_USBHOST30>,
<&cmu_top CLK_DIV_SCLK_USBHOST30>;
assigned-clock-parents =
<&cmu_top CLK_SCLK_USBHOST30_FSYS>,
<&cmu_top CLK_MOUT_BUS_PLL_USER>;
assigned-clock-rates = <0>, <0>, <66700000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;