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drm/amd/pp: Implement force_clock_level for RV 

under manual dpm mode, user can set gfx/mem clock
through sysfs pp_dpm_sclk/mclk on Rv.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu 2018-05-08 14:20:25 +08:00 committed by Alex Deucher
parent 267256b5d8
commit 4ccd2d931c
1 changed files with 45 additions and 0 deletions
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45
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
View File

@ -766,6 +766,51 @@ static int smu10_get_dal_power_level(struct pp_hwmgr *hwmgr,
static int smu10_force_clock_level(struct pp_hwmgr *hwmgr,
enum pp_clock_type type, uint32_t mask)
{
struct smu10_hwmgr *data = hwmgr->backend;
struct smu10_voltage_dependency_table *mclk_table =
data->clock_vol_info.vdd_dep_on_fclk;
uint32_t low, high;
low = mask ? (ffs(mask) - 1) : 0;
high = mask ? (fls(mask) - 1) : 0;
switch (type) {
case PP_SCLK:
if (low > 2 || high > 2) {
pr_info("Currently sclk only support 3 levels on RV\n");
return -EINVAL;
}
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetHardMinGfxClk,
low == 2 ? data->gfx_max_freq_limit/100 :
low == 1 ? SMU10_UMD_PSTATE_GFXCLK :
data->gfx_min_freq_limit/100);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMaxGfxClk,
high == 0 ? data->gfx_min_freq_limit/100 :
high == 1 ? SMU10_UMD_PSTATE_GFXCLK :
data->gfx_max_freq_limit/100);
break;
case PP_MCLK:
if (low > mclk_table->count - 1 || high > mclk_table->count - 1)
return -EINVAL;
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetHardMinFclkByFreq,
mclk_table->entries[low].clk/100);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMaxFclkByFreq,
mclk_table->entries[high].clk/100);
break;
case PP_PCIE:
default:
break;
}
return 0;
}