mirror of https://gitee.com/openkylin/linux.git
crypto: xilinx - Add Xilinx AES driver
This patch adds AES driver support for the Xilinx ZynqMP SoC. Signed-off-by: Mohan Marutirao Dhanawade <mohan.dhanawade@xilinx.com> Signed-off-by: Kalyani Akula <kalyani.akula@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Kalyani Akula
Herbert Xu
parent
4c4f3f3383
commit
4d96f7d481
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@ -754,6 +754,18 @@ config CRYPTO_DEV_ROCKCHIP
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This driver interfaces with the hardware crypto accelerator.
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Supporting cbc/ecb chainmode, and aes/des/des3_ede cipher mode.
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config CRYPTO_DEV_ZYNQMP_AES
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tristate "Support for Xilinx ZynqMP AES hw accelerator"
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depends on ZYNQMP_FIRMWARE || COMPILE_TEST
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select CRYPTO_AES
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select CRYPTO_ENGINE
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select CRYPTO_AEAD
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help
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Xilinx ZynqMP has AES-GCM engine used for symmetric key
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encryption and decryption. This driver interfaces with AES hw
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accelerator. Select this if you want to use the ZynqMP module
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for AES algorithms.
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config CRYPTO_DEV_MEDIATEK
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tristate "MediaTek's EIP97 Cryptographic Engine driver"
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depends on (ARM && ARCH_MEDIATEK) || COMPILE_TEST
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@ -47,5 +47,6 @@ obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/
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obj-$(CONFIG_CRYPTO_DEV_BCM_SPU) += bcm/
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obj-$(CONFIG_CRYPTO_DEV_SAFEXCEL) += inside-secure/
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obj-$(CONFIG_CRYPTO_DEV_ARTPEC6) += axis/
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obj-$(CONFIG_CRYPTO_DEV_ZYNQMP_AES) += xilinx/
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obj-y += hisilicon/
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obj-$(CONFIG_CRYPTO_DEV_AMLOGIC_GXL) += amlogic/
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@ -0,0 +1,2 @@
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# SPDX-License-Identifier: GPL-2.0-only
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obj-$(CONFIG_CRYPTO_DEV_ZYNQMP_AES) += zynqmp-aes-gcm.o
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@ -0,0 +1,457 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Xilinx ZynqMP AES Driver.
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* Copyright (c) 2020 Xilinx Inc.
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*/
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#include <crypto/aes.h>
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#include <crypto/engine.h>
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#include <crypto/gcm.h>
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#include <crypto/internal/aead.h>
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#include <crypto/scatterwalk.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/firmware/xlnx-zynqmp.h>
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#define ZYNQMP_DMA_BIT_MASK 32U
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#define ZYNQMP_AES_KEY_SIZE AES_KEYSIZE_256
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#define ZYNQMP_AES_AUTH_SIZE 16U
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#define ZYNQMP_KEY_SRC_SEL_KEY_LEN 1U
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#define ZYNQMP_AES_BLK_SIZE 1U
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#define ZYNQMP_AES_MIN_INPUT_BLK_SIZE 4U
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#define ZYNQMP_AES_WORD_LEN 4U
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#define ZYNQMP_AES_GCM_TAG_MISMATCH_ERR 0x01
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#define ZYNQMP_AES_WRONG_KEY_SRC_ERR 0x13
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#define ZYNQMP_AES_PUF_NOT_PROGRAMMED 0xE300
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enum zynqmp_aead_op {
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ZYNQMP_AES_DECRYPT = 0,
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ZYNQMP_AES_ENCRYPT
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};
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enum zynqmp_aead_keysrc {
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ZYNQMP_AES_KUP_KEY = 0,
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ZYNQMP_AES_DEV_KEY,
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ZYNQMP_AES_PUF_KEY
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};
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struct zynqmp_aead_drv_ctx {
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union {
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struct aead_alg aead;
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} alg;
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struct device *dev;
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struct crypto_engine *engine;
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const struct zynqmp_eemi_ops *eemi_ops;
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};
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struct zynqmp_aead_hw_req {
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u64 src;
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u64 iv;
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u64 key;
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u64 dst;
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u64 size;
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u64 op;
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u64 keysrc;
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};
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struct zynqmp_aead_tfm_ctx {
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struct crypto_engine_ctx engine_ctx;
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struct device *dev;
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u8 key[ZYNQMP_AES_KEY_SIZE];
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u8 *iv;
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u32 keylen;
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u32 authsize;
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enum zynqmp_aead_keysrc keysrc;
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struct crypto_aead *fbk_cipher;
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};
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struct zynqmp_aead_req_ctx {
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enum zynqmp_aead_op op;
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};
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static int zynqmp_aes_aead_cipher(struct aead_request *req)
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{
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struct crypto_aead *aead = crypto_aead_reqtfm(req);
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struct zynqmp_aead_tfm_ctx *tfm_ctx = crypto_aead_ctx(aead);
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struct zynqmp_aead_req_ctx *rq_ctx = aead_request_ctx(req);
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struct device *dev = tfm_ctx->dev;
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struct aead_alg *alg = crypto_aead_alg(aead);
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struct zynqmp_aead_drv_ctx *drv_ctx;
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struct zynqmp_aead_hw_req *hwreq;
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dma_addr_t dma_addr_data, dma_addr_hw_req;
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unsigned int data_size;
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unsigned int status;
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size_t dma_size;
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char *kbuf;
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int err;
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drv_ctx = container_of(alg, struct zynqmp_aead_drv_ctx, alg.aead);
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if (!drv_ctx->eemi_ops->aes)
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return -ENOTSUPP;
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if (tfm_ctx->keysrc == ZYNQMP_AES_KUP_KEY)
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dma_size = req->cryptlen + ZYNQMP_AES_KEY_SIZE
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+ GCM_AES_IV_SIZE;
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else
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dma_size = req->cryptlen + GCM_AES_IV_SIZE;
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kbuf = dma_alloc_coherent(dev, dma_size, &dma_addr_data, GFP_KERNEL);
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if (!kbuf)
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return -ENOMEM;
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hwreq = dma_alloc_coherent(dev, sizeof(struct zynqmp_aead_hw_req),
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&dma_addr_hw_req, GFP_KERNEL);
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if (!hwreq) {
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dma_free_coherent(dev, dma_size, kbuf, dma_addr_data);
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return -ENOMEM;
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}
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data_size = req->cryptlen;
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scatterwalk_map_and_copy(kbuf, req->src, 0, req->cryptlen, 0);
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memcpy(kbuf + data_size, req->iv, GCM_AES_IV_SIZE);
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hwreq->src = dma_addr_data;
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hwreq->dst = dma_addr_data;
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hwreq->iv = hwreq->src + data_size;
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hwreq->keysrc = tfm_ctx->keysrc;
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hwreq->op = rq_ctx->op;
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if (hwreq->op == ZYNQMP_AES_ENCRYPT)
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hwreq->size = data_size;
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else
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hwreq->size = data_size - ZYNQMP_AES_AUTH_SIZE;
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if (hwreq->keysrc == ZYNQMP_AES_KUP_KEY) {
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memcpy(kbuf + data_size + GCM_AES_IV_SIZE,
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tfm_ctx->key, ZYNQMP_AES_KEY_SIZE);
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hwreq->key = hwreq->src + data_size + GCM_AES_IV_SIZE;
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} else {
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hwreq->key = 0;
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}
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drv_ctx->eemi_ops->aes(dma_addr_hw_req, &status);
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if (status) {
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switch (status) {
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case ZYNQMP_AES_GCM_TAG_MISMATCH_ERR:
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dev_err(dev, "ERROR: Gcm Tag mismatch\n");
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break;
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case ZYNQMP_AES_WRONG_KEY_SRC_ERR:
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dev_err(dev, "ERROR: Wrong KeySrc, enable secure mode\n");
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break;
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case ZYNQMP_AES_PUF_NOT_PROGRAMMED:
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dev_err(dev, "ERROR: PUF is not registered\n");
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break;
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default:
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dev_err(dev, "ERROR: Unknown error\n");
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break;
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}
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err = -status;
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} else {
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if (hwreq->op == ZYNQMP_AES_ENCRYPT)
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data_size = data_size + ZYNQMP_AES_AUTH_SIZE;
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else
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data_size = data_size - ZYNQMP_AES_AUTH_SIZE;
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sg_copy_from_buffer(req->dst, sg_nents(req->dst),
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kbuf, data_size);
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err = 0;
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}
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if (kbuf) {
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memzero_explicit(kbuf, dma_size);
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dma_free_coherent(dev, dma_size, kbuf, dma_addr_data);
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}
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if (hwreq) {
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memzero_explicit(hwreq, sizeof(struct zynqmp_aead_hw_req));
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dma_free_coherent(dev, sizeof(struct zynqmp_aead_hw_req),
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hwreq, dma_addr_hw_req);
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}
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return err;
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}
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static int zynqmp_fallback_check(struct zynqmp_aead_tfm_ctx *tfm_ctx,
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struct aead_request *req)
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{
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int need_fallback = 0;
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struct zynqmp_aead_req_ctx *rq_ctx = aead_request_ctx(req);
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if (tfm_ctx->authsize != ZYNQMP_AES_AUTH_SIZE)
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need_fallback = 1;
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if (tfm_ctx->keysrc == ZYNQMP_AES_KUP_KEY &&
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tfm_ctx->keylen != ZYNQMP_AES_KEY_SIZE) {
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need_fallback = 1;
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}
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if (req->assoclen != 0 ||
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req->cryptlen < ZYNQMP_AES_MIN_INPUT_BLK_SIZE) {
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need_fallback = 1;
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}
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if ((req->cryptlen % ZYNQMP_AES_WORD_LEN) != 0)
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need_fallback = 1;
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if (rq_ctx->op == ZYNQMP_AES_DECRYPT &&
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req->cryptlen <= ZYNQMP_AES_AUTH_SIZE) {
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need_fallback = 1;
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}
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return need_fallback;
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}
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static int zynqmp_handle_aes_req(struct crypto_engine *engine,
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void *req)
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{
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struct aead_request *areq =
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container_of(req, struct aead_request, base);
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struct crypto_aead *aead = crypto_aead_reqtfm(req);
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struct zynqmp_aead_tfm_ctx *tfm_ctx = crypto_aead_ctx(aead);
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struct zynqmp_aead_req_ctx *rq_ctx = aead_request_ctx(areq);
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struct aead_request *subreq = aead_request_ctx(req);
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int need_fallback;
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int err;
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need_fallback = zynqmp_fallback_check(tfm_ctx, areq);
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if (need_fallback) {
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aead_request_set_tfm(subreq, tfm_ctx->fbk_cipher);
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aead_request_set_callback(subreq, areq->base.flags,
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NULL, NULL);
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aead_request_set_crypt(subreq, areq->src, areq->dst,
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areq->cryptlen, areq->iv);
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aead_request_set_ad(subreq, areq->assoclen);
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if (rq_ctx->op == ZYNQMP_AES_ENCRYPT)
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err = crypto_aead_encrypt(subreq);
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else
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err = crypto_aead_decrypt(subreq);
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} else {
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err = zynqmp_aes_aead_cipher(areq);
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}
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crypto_finalize_aead_request(engine, areq, err);
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return 0;
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}
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static int zynqmp_aes_aead_setkey(struct crypto_aead *aead, const u8 *key,
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unsigned int keylen)
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{
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struct crypto_tfm *tfm = crypto_aead_tfm(aead);
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struct zynqmp_aead_tfm_ctx *tfm_ctx =
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(struct zynqmp_aead_tfm_ctx *)crypto_tfm_ctx(tfm);
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unsigned char keysrc;
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if (keylen == ZYNQMP_KEY_SRC_SEL_KEY_LEN) {
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keysrc = *key;
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if (keysrc == ZYNQMP_AES_KUP_KEY ||
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keysrc == ZYNQMP_AES_DEV_KEY ||
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keysrc == ZYNQMP_AES_PUF_KEY) {
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tfm_ctx->keysrc = (enum zynqmp_aead_keysrc)keysrc;
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} else {
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tfm_ctx->keylen = keylen;
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}
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} else {
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tfm_ctx->keylen = keylen;
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if (keylen == ZYNQMP_AES_KEY_SIZE) {
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tfm_ctx->keysrc = ZYNQMP_AES_KUP_KEY;
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memcpy(tfm_ctx->key, key, keylen);
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}
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}
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tfm_ctx->fbk_cipher->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK;
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tfm_ctx->fbk_cipher->base.crt_flags |= (aead->base.crt_flags &
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CRYPTO_TFM_REQ_MASK);
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return crypto_aead_setkey(tfm_ctx->fbk_cipher, key, keylen);
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}
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static int zynqmp_aes_aead_setauthsize(struct crypto_aead *aead,
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unsigned int authsize)
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{
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struct crypto_tfm *tfm = crypto_aead_tfm(aead);
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struct zynqmp_aead_tfm_ctx *tfm_ctx =
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(struct zynqmp_aead_tfm_ctx *)crypto_tfm_ctx(tfm);
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tfm_ctx->authsize = authsize;
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return crypto_aead_setauthsize(tfm_ctx->fbk_cipher, authsize);
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}
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static int zynqmp_aes_aead_encrypt(struct aead_request *req)
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{
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struct zynqmp_aead_drv_ctx *drv_ctx;
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struct crypto_aead *aead = crypto_aead_reqtfm(req);
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struct aead_alg *alg = crypto_aead_alg(aead);
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struct zynqmp_aead_req_ctx *rq_ctx = aead_request_ctx(req);
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rq_ctx->op = ZYNQMP_AES_ENCRYPT;
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drv_ctx = container_of(alg, struct zynqmp_aead_drv_ctx, alg.aead);
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return crypto_transfer_aead_request_to_engine(drv_ctx->engine, req);
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}
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static int zynqmp_aes_aead_decrypt(struct aead_request *req)
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{
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struct zynqmp_aead_drv_ctx *drv_ctx;
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struct crypto_aead *aead = crypto_aead_reqtfm(req);
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struct aead_alg *alg = crypto_aead_alg(aead);
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struct zynqmp_aead_req_ctx *rq_ctx = aead_request_ctx(req);
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rq_ctx->op = ZYNQMP_AES_DECRYPT;
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drv_ctx = container_of(alg, struct zynqmp_aead_drv_ctx, alg.aead);
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return crypto_transfer_aead_request_to_engine(drv_ctx->engine, req);
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}
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static int zynqmp_aes_aead_init(struct crypto_aead *aead)
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{
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struct crypto_tfm *tfm = crypto_aead_tfm(aead);
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struct zynqmp_aead_tfm_ctx *tfm_ctx =
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(struct zynqmp_aead_tfm_ctx *)crypto_tfm_ctx(tfm);
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struct zynqmp_aead_drv_ctx *drv_ctx;
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struct aead_alg *alg = crypto_aead_alg(aead);
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drv_ctx = container_of(alg, struct zynqmp_aead_drv_ctx, alg.aead);
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tfm_ctx->dev = drv_ctx->dev;
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tfm_ctx->engine_ctx.op.do_one_request = zynqmp_handle_aes_req;
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tfm_ctx->engine_ctx.op.prepare_request = NULL;
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tfm_ctx->engine_ctx.op.unprepare_request = NULL;
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tfm_ctx->fbk_cipher = crypto_alloc_aead(drv_ctx->alg.aead.base.cra_name,
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0,
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CRYPTO_ALG_NEED_FALLBACK);
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if (IS_ERR(tfm_ctx->fbk_cipher)) {
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pr_err("%s() Error: failed to allocate fallback for %s\n",
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__func__, drv_ctx->alg.aead.base.cra_name);
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return PTR_ERR(tfm_ctx->fbk_cipher);
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}
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crypto_aead_set_reqsize(aead,
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max(sizeof(struct zynqmp_aead_req_ctx),
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sizeof(struct aead_request) +
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crypto_aead_reqsize(tfm_ctx->fbk_cipher)));
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return 0;
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}
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static void zynqmp_aes_aead_exit(struct crypto_aead *aead)
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{
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struct crypto_tfm *tfm = crypto_aead_tfm(aead);
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struct zynqmp_aead_tfm_ctx *tfm_ctx =
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(struct zynqmp_aead_tfm_ctx *)crypto_tfm_ctx(tfm);
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if (tfm_ctx->fbk_cipher) {
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crypto_free_aead(tfm_ctx->fbk_cipher);
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tfm_ctx->fbk_cipher = NULL;
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}
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memzero_explicit(tfm_ctx, sizeof(struct zynqmp_aead_tfm_ctx));
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}
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static struct zynqmp_aead_drv_ctx aes_drv_ctx = {
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.alg.aead = {
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.setkey = zynqmp_aes_aead_setkey,
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.setauthsize = zynqmp_aes_aead_setauthsize,
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.encrypt = zynqmp_aes_aead_encrypt,
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.decrypt = zynqmp_aes_aead_decrypt,
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.init = zynqmp_aes_aead_init,
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.exit = zynqmp_aes_aead_exit,
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.ivsize = GCM_AES_IV_SIZE,
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.maxauthsize = ZYNQMP_AES_AUTH_SIZE,
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.base = {
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.cra_name = "gcm(aes)",
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.cra_driver_name = "xilinx-zynqmp-aes-gcm",
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.cra_priority = 200,
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.cra_flags = CRYPTO_ALG_TYPE_AEAD |
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CRYPTO_ALG_ASYNC |
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CRYPTO_ALG_KERN_DRIVER_ONLY |
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CRYPTO_ALG_NEED_FALLBACK,
|
||||
.cra_blocksize = ZYNQMP_AES_BLK_SIZE,
|
||||
.cra_ctxsize = sizeof(struct zynqmp_aead_tfm_ctx),
|
||||
.cra_module = THIS_MODULE,
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
static int zynqmp_aes_aead_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
int err;
|
||||
|
||||
/* ZynqMP AES driver supports only one instance */
|
||||
if (!aes_drv_ctx.dev)
|
||||
aes_drv_ctx.dev = dev;
|
||||
else
|
||||
return -ENODEV;
|
||||
|
||||
aes_drv_ctx.eemi_ops = zynqmp_pm_get_eemi_ops();
|
||||
if (IS_ERR(aes_drv_ctx.eemi_ops)) {
|
||||
dev_err(dev, "Failed to get ZynqMP EEMI interface\n");
|
||||
return PTR_ERR(aes_drv_ctx.eemi_ops);
|
||||
}
|
||||
|
||||
err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(ZYNQMP_DMA_BIT_MASK));
|
||||
if (err < 0) {
|
||||
dev_err(dev, "No usable DMA configuration\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
aes_drv_ctx.engine = crypto_engine_alloc_init(dev, 1);
|
||||
if (!aes_drv_ctx.engine) {
|
||||
dev_err(dev, "Cannot alloc AES engine\n");
|
||||
err = -ENOMEM;
|
||||
goto err_engine;
|
||||
}
|
||||
|
||||
err = crypto_engine_start(aes_drv_ctx.engine);
|
||||
if (err) {
|
||||
dev_err(dev, "Cannot start AES engine\n");
|
||||
goto err_engine;
|
||||
}
|
||||
|
||||
err = crypto_register_aead(&aes_drv_ctx.alg.aead);
|
||||
if (err < 0) {
|
||||
dev_err(dev, "Failed to register AEAD alg.\n");
|
||||
goto err_aead;
|
||||
}
|
||||
return 0;
|
||||
|
||||
err_aead:
|
||||
crypto_unregister_aead(&aes_drv_ctx.alg.aead);
|
||||
|
||||
err_engine:
|
||||
if (aes_drv_ctx.engine)
|
||||
crypto_engine_exit(aes_drv_ctx.engine);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int zynqmp_aes_aead_remove(struct platform_device *pdev)
|
||||
{
|
||||
crypto_engine_exit(aes_drv_ctx.engine);
|
||||
crypto_unregister_aead(&aes_drv_ctx.alg.aead);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id zynqmp_aes_dt_ids[] = {
|
||||
{ .compatible = "xlnx,zynqmp-aes" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, zynqmp_aes_dt_ids);
|
||||
|
||||
static struct platform_driver zynqmp_aes_driver = {
|
||||
.probe = zynqmp_aes_aead_probe,
|
||||
.remove = zynqmp_aes_aead_remove,
|
||||
.driver = {
|
||||
.name = "zynqmp-aes",
|
||||
.of_match_table = zynqmp_aes_dt_ids,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(zynqmp_aes_driver);
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue