mirror of https://gitee.com/openkylin/linux.git
Allwinner Clocks Additions for 3.18
The most important part of this serie is the addition of the phase API to handle the MMC clocks in the Allwinner SoCs. Apart from that, the A23 gained a new mbus driver, and there's a fix for a incorrect divider table on the APB0 clock. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJUJm3zAAoJEBx+YmzsjxAgxJwQAJk3+Oq3J54jzRxKLGjUpfy9 Ma9p/78ZSnYlYWrEn62vzu7sGeMJsPo4Lsmy+Hch2r765+PzFZw9oDaxjFT5poQy Mv8F7Uyetc99sGAfmg/fKnzgQpp1t+9+kB42cV6lzjXolqX/ACcIjzFOzROXEF9B 2bnQ3RwXqvQhKKryDBg9+hJYt1R15d4SxQ7Rn6lb6WsZTxjGVO0cvvU3tp4QGQgg ZDUkJNLzLYdMK9XUNyqreatmz+HMxL5vYHeEWFz388ECp9DRUPT3MqlQcUqgSLlD eMqQPOnd5p5ZEUdB8qAAtf4kIbQTaVa7/4u37sE/+fogw6Pq/6a2Jqppl9aJWD7I PDFjxSMl77W5mQZSEanbc0a0qmqAqtZokDusP0bc0ETSZzmPVvohjW5Fa9Awyi0j PeN2bTglaFDPsHxKlQ31HF/e/almXkpiIXegeG0e/3VrGSrghFMQtqLEUXgVPu10 4PV8x7O2ib1VVAowwOb10qGv0fLGC8UCqL9zXVNlCy268ijjKMlNyK3U1sllphba fWBYgtg9+1YHONI1SewuYibAqROC7ICDXiqDkJVb6UWmO39HBcOFDb3HJ0EIj8T4 9v1clkVy1vONIqfvi1SeTekLovpROOxhxGtyXTpdx5qdlVhBjkEsNVHc5jh6BPHr o9TlBnnmIPajvF9wMN+H =ZkI9 -----END PGP SIGNATURE----- Merge tag 'sunxi-clocks-for-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next Allwinner Clocks Additions for 3.18 The most important part of this serie is the addition of the phase API to handle the MMC clocks in the Allwinner SoCs. Apart from that, the A23 gained a new mbus driver, and there's a fix for a incorrect divider table on the APB0 clock.
This commit is contained in:
Mike Turquette
commit
4dc7ed32f3
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@ -46,7 +46,11 @@ Required properties:
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"allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
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"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
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"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
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"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
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"allwinner,sun4i-a10-mmc-output-clk" - for the MMC output clock on A10
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"allwinner,sun4i-a10-mmc-sample-clk" - for the MMC sample clock on A10
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"allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
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"allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23
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"allwinner,sun7i-a20-out-clk" - for the external output clocks
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"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
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"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
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@ -287,7 +287,7 @@ usb_clk: clk@01c200cc {
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mbus_clk: clk@01c2015c {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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compatible = "allwinner,sun5i-a13-mbus-clk";
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reg = <0x01c2015c 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mbus";
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@ -285,7 +285,7 @@ usb_clk: clk@01c200cc {
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mbus_clk: clk@01c2015c {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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compatible = "allwinner,sun5i-a13-mbus-clk";
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reg = <0x01c2015c 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mbus";
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@ -346,7 +346,7 @@ spi3_clk: clk@01c200d4 {
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mbus_clk: clk@01c2015c {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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compatible = "allwinner,sun5i-a13-mbus-clk";
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reg = <0x01c2015c 0x4>;
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clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
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clock-output-names = "mbus";
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@ -119,11 +119,11 @@ static void clk_summary_show_one(struct seq_file *s, struct clk *c, int level)
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if (!c)
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return;
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seq_printf(s, "%*s%-*s %11d %12d %11lu %10lu\n",
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seq_printf(s, "%*s%-*s %11d %12d %11lu %10lu %-3d\n",
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level * 3 + 1, "",
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30 - level * 3, c->name,
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c->enable_count, c->prepare_count, clk_get_rate(c),
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clk_get_accuracy(c));
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clk_get_accuracy(c), clk_get_phase(c));
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}
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static void clk_summary_show_subtree(struct seq_file *s, struct clk *c,
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@ -145,8 +145,8 @@ static int clk_summary_show(struct seq_file *s, void *data)
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struct clk *c;
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struct hlist_head **lists = (struct hlist_head **)s->private;
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seq_puts(s, " clock enable_cnt prepare_cnt rate accuracy\n");
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seq_puts(s, "--------------------------------------------------------------------------------\n");
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seq_puts(s, " clock enable_cnt prepare_cnt rate accuracy phase\n");
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seq_puts(s, "----------------------------------------------------------------------------------------\n");
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clk_prepare_lock();
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@ -182,6 +182,7 @@ static void clk_dump_one(struct seq_file *s, struct clk *c, int level)
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seq_printf(s, "\"prepare_count\": %d,", c->prepare_count);
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seq_printf(s, "\"rate\": %lu", clk_get_rate(c));
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seq_printf(s, "\"accuracy\": %lu", clk_get_accuracy(c));
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seq_printf(s, "\"phase\": %d", clk_get_phase(c));
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}
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static void clk_dump_subtree(struct seq_file *s, struct clk *c, int level)
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@ -266,6 +267,11 @@ static int clk_debug_create_one(struct clk *clk, struct dentry *pdentry)
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if (!d)
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goto err_out;
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d = debugfs_create_u32("clk_phase", S_IRUGO, clk->dentry,
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(u32 *)&clk->phase);
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if (!d)
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goto err_out;
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d = debugfs_create_x32("clk_flags", S_IRUGO, clk->dentry,
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(u32 *)&clk->flags);
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if (!d)
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@ -1725,6 +1731,77 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
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}
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EXPORT_SYMBOL_GPL(clk_set_parent);
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/**
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* clk_set_phase - adjust the phase shift of a clock signal
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* @clk: clock signal source
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* @degrees: number of degrees the signal is shifted
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*
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* Shifts the phase of a clock signal by the specified
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* degrees. Returns 0 on success, -EERROR otherwise.
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*
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* This function makes no distinction about the input or reference
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* signal that we adjust the clock signal phase against. For example
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* phase locked-loop clock signal generators we may shift phase with
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* respect to feedback clock signal input, but for other cases the
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* clock phase may be shifted with respect to some other, unspecified
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* signal.
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*
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* Additionally the concept of phase shift does not propagate through
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* the clock tree hierarchy, which sets it apart from clock rates and
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* clock accuracy. A parent clock phase attribute does not have an
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* impact on the phase attribute of a child clock.
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*/
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int clk_set_phase(struct clk *clk, int degrees)
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{
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int ret = 0;
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if (!clk)
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goto out;
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/* sanity check degrees */
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degrees %= 360;
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if (degrees < 0)
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degrees += 360;
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clk_prepare_lock();
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if (!clk->ops->set_phase)
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goto out_unlock;
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ret = clk->ops->set_phase(clk->hw, degrees);
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if (!ret)
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clk->phase = degrees;
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out_unlock:
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clk_prepare_unlock();
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out:
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return ret;
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}
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/**
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* clk_get_phase - return the phase shift of a clock signal
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* @clk: clock signal source
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*
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* Returns the phase shift of a clock node in degrees, otherwise returns
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* -EERROR.
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*/
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int clk_get_phase(struct clk *clk)
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{
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int ret = 0;
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if (!clk)
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goto out;
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clk_prepare_lock();
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ret = clk->phase;
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clk_prepare_unlock();
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out:
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return ret;
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}
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/**
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* __clk_init - initialize the data structures in a struct clk
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* @dev: device initializing this clk, placeholder for now
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@ -1843,6 +1920,16 @@ int __clk_init(struct device *dev, struct clk *clk)
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else
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clk->accuracy = 0;
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/*
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* Set clk's phase.
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* Since a phase is by definition relative to its parent, just
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* query the current clock phase, or just assume it's in phase.
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*/
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if (clk->ops->get_phase)
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clk->phase = clk->ops->get_phase(clk->hw);
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else
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clk->phase = 0;
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/*
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* Set clk's rate. The preferred method is to use .recalc_rate. For
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* simple clocks and lazy developers the default fallback is to use the
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@ -5,6 +5,8 @@
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obj-y += clk-sunxi.o clk-factors.o
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obj-y += clk-a10-hosc.o
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obj-y += clk-a20-gmac.o
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obj-y += clk-mod0.o
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obj-y += clk-sun8i-mbus.o
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obj-$(CONFIG_MFD_SUN6I_PRCM) += \
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clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \
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@ -9,18 +9,18 @@
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/string.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include "clk-factors.h"
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/*
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* DOC: basic adjustable factor-based clock that cannot gate
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* DOC: basic adjustable factor-based clock
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*
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* Traits of this clock:
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* prepare - clk_prepare only ensures that parents are prepared
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@ -32,6 +32,8 @@
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#define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
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#define FACTORS_MAX_PARENTS 5
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#define SETMASK(len, pos) (((1U << (len)) - 1) << (pos))
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#define CLRMASK(len, pos) (~(SETMASK(len, pos)))
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#define FACTOR_GET(bit, len, reg) (((reg) & SETMASK(len, bit)) >> (bit))
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@ -147,9 +149,96 @@ static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
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return 0;
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}
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const struct clk_ops clk_factors_ops = {
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static const struct clk_ops clk_factors_ops = {
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.determine_rate = clk_factors_determine_rate,
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.recalc_rate = clk_factors_recalc_rate,
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.round_rate = clk_factors_round_rate,
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.set_rate = clk_factors_set_rate,
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};
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struct clk * __init sunxi_factors_register(struct device_node *node,
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const struct factors_data *data,
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spinlock_t *lock)
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{
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struct clk *clk;
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struct clk_factors *factors;
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struct clk_gate *gate = NULL;
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struct clk_mux *mux = NULL;
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struct clk_hw *gate_hw = NULL;
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struct clk_hw *mux_hw = NULL;
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const char *clk_name = node->name;
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const char *parents[FACTORS_MAX_PARENTS];
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void __iomem *reg;
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int i = 0;
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reg = of_iomap(node, 0);
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/* if we have a mux, we will have >1 parents */
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while (i < FACTORS_MAX_PARENTS &&
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(parents[i] = of_clk_get_parent_name(node, i)) != NULL)
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i++;
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/*
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* some factor clocks, such as pll5 and pll6, may have multiple
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* outputs, and have their name designated in factors_data
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*/
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if (data->name)
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clk_name = data->name;
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else
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of_property_read_string(node, "clock-output-names", &clk_name);
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factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
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if (!factors)
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return NULL;
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/* set up factors properties */
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factors->reg = reg;
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factors->config = data->table;
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factors->get_factors = data->getter;
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factors->lock = lock;
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/* Add a gate if this factor clock can be gated */
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if (data->enable) {
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gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
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if (!gate) {
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kfree(factors);
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return NULL;
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}
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/* set up gate properties */
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gate->reg = reg;
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gate->bit_idx = data->enable;
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gate->lock = factors->lock;
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gate_hw = &gate->hw;
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}
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/* Add a mux if this factor clock can be muxed */
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if (data->mux) {
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mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
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if (!mux) {
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kfree(factors);
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kfree(gate);
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return NULL;
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}
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/* set up gate properties */
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mux->reg = reg;
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mux->shift = data->mux;
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mux->mask = SUNXI_FACTORS_MUX_MASK;
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mux->lock = factors->lock;
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mux_hw = &mux->hw;
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}
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clk = clk_register_composite(NULL, clk_name,
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parents, i,
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mux_hw, &clk_mux_ops,
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&factors->hw, &clk_factors_ops,
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gate_hw, &clk_gate_ops, 0);
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if (!IS_ERR(clk)) {
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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clk_register_clkdev(clk, clk_name, NULL);
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}
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return clk;
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}
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|
|
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@ -3,9 +3,12 @@
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/spinlock.h>
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#define SUNXI_FACTORS_NOT_APPLICABLE (0)
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#define SUNXI_FACTORS_MUX_MASK 0x3
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|
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struct clk_factors_config {
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u8 nshift;
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u8 nwidth;
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@ -18,6 +21,14 @@ struct clk_factors_config {
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u8 n_start;
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};
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struct factors_data {
|
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int enable;
|
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int mux;
|
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struct clk_factors_config *table;
|
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void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p);
|
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const char *name;
|
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};
|
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|
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struct clk_factors {
|
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struct clk_hw hw;
|
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void __iomem *reg;
|
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|
|
@ -26,5 +37,8 @@ struct clk_factors {
|
|||
spinlock_t *lock;
|
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};
|
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|
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extern const struct clk_ops clk_factors_ops;
|
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struct clk * __init sunxi_factors_register(struct device_node *node,
|
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const struct factors_data *data,
|
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spinlock_t *lock);
|
||||
|
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#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,283 @@
|
|||
/*
|
||||
* Copyright 2013 Emilio López
|
||||
*
|
||||
* Emilio López <emilio@elopez.com.ar>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/of_address.h>
|
||||
|
||||
#include "clk-factors.h"
|
||||
|
||||
/**
|
||||
* sun4i_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
|
||||
* MOD0 rate is calculated as follows
|
||||
* rate = (parent_rate >> p) / (m + 1);
|
||||
*/
|
||||
|
||||
static void sun4i_a10_get_mod0_factors(u32 *freq, u32 parent_rate,
|
||||
u8 *n, u8 *k, u8 *m, u8 *p)
|
||||
{
|
||||
u8 div, calcm, calcp;
|
||||
|
||||
/* These clocks can only divide, so we will never be able to achieve
|
||||
* frequencies higher than the parent frequency */
|
||||
if (*freq > parent_rate)
|
||||
*freq = parent_rate;
|
||||
|
||||
div = DIV_ROUND_UP(parent_rate, *freq);
|
||||
|
||||
if (div < 16)
|
||||
calcp = 0;
|
||||
else if (div / 2 < 16)
|
||||
calcp = 1;
|
||||
else if (div / 4 < 16)
|
||||
calcp = 2;
|
||||
else
|
||||
calcp = 3;
|
||||
|
||||
calcm = DIV_ROUND_UP(div, 1 << calcp);
|
||||
|
||||
*freq = (parent_rate >> calcp) / calcm;
|
||||
|
||||
/* we were called to round the frequency, we can now return */
|
||||
if (n == NULL)
|
||||
return;
|
||||
|
||||
*m = calcm - 1;
|
||||
*p = calcp;
|
||||
}
|
||||
|
||||
/* user manual says "n" but it's really "p" */
|
||||
static struct clk_factors_config sun4i_a10_mod0_config = {
|
||||
.mshift = 0,
|
||||
.mwidth = 4,
|
||||
.pshift = 16,
|
||||
.pwidth = 2,
|
||||
};
|
||||
|
||||
static const struct factors_data sun4i_a10_mod0_data __initconst = {
|
||||
.enable = 31,
|
||||
.mux = 24,
|
||||
.table = &sun4i_a10_mod0_config,
|
||||
.getter = sun4i_a10_get_mod0_factors,
|
||||
};
|
||||
|
||||
static DEFINE_SPINLOCK(sun4i_a10_mod0_lock);
|
||||
|
||||
static void __init sun4i_a10_mod0_setup(struct device_node *node)
|
||||
{
|
||||
sunxi_factors_register(node, &sun4i_a10_mod0_data, &sun4i_a10_mod0_lock);
|
||||
}
|
||||
CLK_OF_DECLARE(sun4i_a10_mod0, "allwinner,sun4i-a10-mod0-clk", sun4i_a10_mod0_setup);
|
||||
|
||||
static DEFINE_SPINLOCK(sun5i_a13_mbus_lock);
|
||||
|
||||
static void __init sun5i_a13_mbus_setup(struct device_node *node)
|
||||
{
|
||||
struct clk *mbus = sunxi_factors_register(node, &sun4i_a10_mod0_data, &sun5i_a13_mbus_lock);
|
||||
|
||||
/* The MBUS clocks needs to be always enabled */
|
||||
__clk_get(mbus);
|
||||
clk_prepare_enable(mbus);
|
||||
}
|
||||
CLK_OF_DECLARE(sun5i_a13_mbus, "allwinner,sun5i-a13-mbus-clk", sun5i_a13_mbus_setup);
|
||||
|
||||
struct mmc_phase_data {
|
||||
u8 offset;
|
||||
};
|
||||
|
||||
struct mmc_phase {
|
||||
struct clk_hw hw;
|
||||
void __iomem *reg;
|
||||
struct mmc_phase_data *data;
|
||||
spinlock_t *lock;
|
||||
};
|
||||
|
||||
#define to_mmc_phase(_hw) container_of(_hw, struct mmc_phase, hw)
|
||||
|
||||
static int mmc_get_phase(struct clk_hw *hw)
|
||||
{
|
||||
struct clk *mmc, *mmc_parent, *clk = hw->clk;
|
||||
struct mmc_phase *phase = to_mmc_phase(hw);
|
||||
unsigned int mmc_rate, mmc_parent_rate;
|
||||
u16 step, mmc_div;
|
||||
u32 value;
|
||||
u8 delay;
|
||||
|
||||
value = readl(phase->reg);
|
||||
delay = (value >> phase->data->offset) & 0x3;
|
||||
|
||||
if (!delay)
|
||||
return 180;
|
||||
|
||||
/* Get the main MMC clock */
|
||||
mmc = clk_get_parent(clk);
|
||||
if (!mmc)
|
||||
return -EINVAL;
|
||||
|
||||
/* And its rate */
|
||||
mmc_rate = clk_get_rate(mmc);
|
||||
if (!mmc_rate)
|
||||
return -EINVAL;
|
||||
|
||||
/* Now, get the MMC parent (most likely some PLL) */
|
||||
mmc_parent = clk_get_parent(mmc);
|
||||
if (!mmc_parent)
|
||||
return -EINVAL;
|
||||
|
||||
/* And its rate */
|
||||
mmc_parent_rate = clk_get_rate(mmc_parent);
|
||||
if (!mmc_parent_rate)
|
||||
return -EINVAL;
|
||||
|
||||
/* Get MMC clock divider */
|
||||
mmc_div = mmc_parent_rate / mmc_rate;
|
||||
|
||||
step = DIV_ROUND_CLOSEST(360, mmc_div);
|
||||
return delay * step;
|
||||
}
|
||||
|
||||
static int mmc_set_phase(struct clk_hw *hw, int degrees)
|
||||
{
|
||||
struct clk *mmc, *mmc_parent, *clk = hw->clk;
|
||||
struct mmc_phase *phase = to_mmc_phase(hw);
|
||||
unsigned int mmc_rate, mmc_parent_rate;
|
||||
unsigned long flags;
|
||||
u32 value;
|
||||
u8 delay;
|
||||
|
||||
/* Get the main MMC clock */
|
||||
mmc = clk_get_parent(clk);
|
||||
if (!mmc)
|
||||
return -EINVAL;
|
||||
|
||||
/* And its rate */
|
||||
mmc_rate = clk_get_rate(mmc);
|
||||
if (!mmc_rate)
|
||||
return -EINVAL;
|
||||
|
||||
/* Now, get the MMC parent (most likely some PLL) */
|
||||
mmc_parent = clk_get_parent(mmc);
|
||||
if (!mmc_parent)
|
||||
return -EINVAL;
|
||||
|
||||
/* And its rate */
|
||||
mmc_parent_rate = clk_get_rate(mmc_parent);
|
||||
if (!mmc_parent_rate)
|
||||
return -EINVAL;
|
||||
|
||||
if (degrees != 180) {
|
||||
u16 step, mmc_div;
|
||||
|
||||
/* Get MMC clock divider */
|
||||
mmc_div = mmc_parent_rate / mmc_rate;
|
||||
|
||||
/*
|
||||
* We can only outphase the clocks by multiple of the
|
||||
* PLL's period.
|
||||
*
|
||||
* Since the MMC clock in only a divider, and the
|
||||
* formula to get the outphasing in degrees is deg =
|
||||
* 360 * delta / period
|
||||
*
|
||||
* If we simplify this formula, we can see that the
|
||||
* only thing that we're concerned about is the number
|
||||
* of period we want to outphase our clock from, and
|
||||
* the divider set by the MMC clock.
|
||||
*/
|
||||
step = DIV_ROUND_CLOSEST(360, mmc_div);
|
||||
delay = DIV_ROUND_CLOSEST(degrees, step);
|
||||
} else {
|
||||
delay = 0;
|
||||
}
|
||||
|
||||
spin_lock_irqsave(phase->lock, flags);
|
||||
value = readl(phase->reg);
|
||||
value &= ~GENMASK(phase->data->offset + 3, phase->data->offset);
|
||||
value |= delay << phase->data->offset;
|
||||
writel(value, phase->reg);
|
||||
spin_unlock_irqrestore(phase->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct clk_ops mmc_clk_ops = {
|
||||
.get_phase = mmc_get_phase,
|
||||
.set_phase = mmc_set_phase,
|
||||
};
|
||||
|
||||
static void __init sun4i_a10_mmc_phase_setup(struct device_node *node,
|
||||
struct mmc_phase_data *data)
|
||||
{
|
||||
const char *parent_names[1] = { of_clk_get_parent_name(node, 0) };
|
||||
struct clk_init_data init = {
|
||||
.num_parents = 1,
|
||||
.parent_names = parent_names,
|
||||
.ops = &mmc_clk_ops,
|
||||
};
|
||||
|
||||
struct mmc_phase *phase;
|
||||
struct clk *clk;
|
||||
|
||||
phase = kmalloc(sizeof(*phase), GFP_KERNEL);
|
||||
if (!phase)
|
||||
return;
|
||||
|
||||
phase->hw.init = &init;
|
||||
|
||||
phase->reg = of_iomap(node, 0);
|
||||
if (!phase->reg)
|
||||
goto err_free;
|
||||
|
||||
phase->data = data;
|
||||
phase->lock = &sun4i_a10_mod0_lock;
|
||||
|
||||
if (of_property_read_string(node, "clock-output-names", &init.name))
|
||||
init.name = node->name;
|
||||
|
||||
clk = clk_register(NULL, &phase->hw);
|
||||
if (IS_ERR(clk))
|
||||
goto err_unmap;
|
||||
|
||||
of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
||||
|
||||
return;
|
||||
|
||||
err_unmap:
|
||||
iounmap(phase->reg);
|
||||
err_free:
|
||||
kfree(phase);
|
||||
}
|
||||
|
||||
|
||||
static struct mmc_phase_data mmc_output_clk = {
|
||||
.offset = 8,
|
||||
};
|
||||
|
||||
static struct mmc_phase_data mmc_sample_clk = {
|
||||
.offset = 20,
|
||||
};
|
||||
|
||||
static void __init sun4i_a10_mmc_output_setup(struct device_node *node)
|
||||
{
|
||||
sun4i_a10_mmc_phase_setup(node, &mmc_output_clk);
|
||||
}
|
||||
CLK_OF_DECLARE(sun4i_a10_mmc_output, "allwinner,sun4i-a10-mmc-output-clk", sun4i_a10_mmc_output_setup);
|
||||
|
||||
static void __init sun4i_a10_mmc_sample_setup(struct device_node *node)
|
||||
{
|
||||
sun4i_a10_mmc_phase_setup(node, &mmc_sample_clk);
|
||||
}
|
||||
CLK_OF_DECLARE(sun4i_a10_mmc_sample, "allwinner,sun4i-a10-mmc-sample-clk", sun4i_a10_mmc_sample_setup);
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
/*
|
||||
* Copyright 2014 Chen-Yu Tsai
|
||||
*
|
||||
* Chen-Yu Tsai <wens@csie.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/of_address.h>
|
||||
|
||||
#include "clk-factors.h"
|
||||
|
||||
/**
|
||||
* sun8i_a23_get_mbus_factors() - calculates m factor for MBUS clocks
|
||||
* MBUS rate is calculated as follows
|
||||
* rate = parent_rate / (m + 1);
|
||||
*/
|
||||
|
||||
static void sun8i_a23_get_mbus_factors(u32 *freq, u32 parent_rate,
|
||||
u8 *n, u8 *k, u8 *m, u8 *p)
|
||||
{
|
||||
u8 div;
|
||||
|
||||
/*
|
||||
* These clocks can only divide, so we will never be able to
|
||||
* achieve frequencies higher than the parent frequency
|
||||
*/
|
||||
if (*freq > parent_rate)
|
||||
*freq = parent_rate;
|
||||
|
||||
div = DIV_ROUND_UP(parent_rate, *freq);
|
||||
|
||||
if (div > 8)
|
||||
div = 8;
|
||||
|
||||
*freq = parent_rate / div;
|
||||
|
||||
/* we were called to round the frequency, we can now return */
|
||||
if (m == NULL)
|
||||
return;
|
||||
|
||||
*m = div - 1;
|
||||
}
|
||||
|
||||
static struct clk_factors_config sun8i_a23_mbus_config = {
|
||||
.mshift = 0,
|
||||
.mwidth = 3,
|
||||
};
|
||||
|
||||
static const struct factors_data sun8i_a23_mbus_data __initconst = {
|
||||
.enable = 31,
|
||||
.mux = 24,
|
||||
.table = &sun8i_a23_mbus_config,
|
||||
.getter = sun8i_a23_get_mbus_factors,
|
||||
};
|
||||
|
||||
static DEFINE_SPINLOCK(sun8i_a23_mbus_lock);
|
||||
|
||||
static void __init sun8i_a23_mbus_setup(struct device_node *node)
|
||||
{
|
||||
struct clk *mbus = sunxi_factors_register(node, &sun8i_a23_mbus_data,
|
||||
&sun8i_a23_mbus_lock);
|
||||
|
||||
/* The MBUS clocks needs to be always enabled */
|
||||
__clk_get(mbus);
|
||||
clk_prepare_enable(mbus);
|
||||
}
|
||||
CLK_OF_DECLARE(sun8i_a23_mbus, "allwinner,sun8i-a23-mbus-clk", sun8i_a23_mbus_setup);
|
||||
|
|
@ -19,6 +19,7 @@
|
|||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/reset-controller.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#include "clk-factors.h"
|
||||
|
||||
|
|
@ -319,46 +320,6 @@ static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
|
|||
|
||||
|
||||
|
||||
/**
|
||||
* sun4i_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
|
||||
* MOD0 rate is calculated as follows
|
||||
* rate = (parent_rate >> p) / (m + 1);
|
||||
*/
|
||||
|
||||
static void sun4i_get_mod0_factors(u32 *freq, u32 parent_rate,
|
||||
u8 *n, u8 *k, u8 *m, u8 *p)
|
||||
{
|
||||
u8 div, calcm, calcp;
|
||||
|
||||
/* These clocks can only divide, so we will never be able to achieve
|
||||
* frequencies higher than the parent frequency */
|
||||
if (*freq > parent_rate)
|
||||
*freq = parent_rate;
|
||||
|
||||
div = DIV_ROUND_UP(parent_rate, *freq);
|
||||
|
||||
if (div < 16)
|
||||
calcp = 0;
|
||||
else if (div / 2 < 16)
|
||||
calcp = 1;
|
||||
else if (div / 4 < 16)
|
||||
calcp = 2;
|
||||
else
|
||||
calcp = 3;
|
||||
|
||||
calcm = DIV_ROUND_UP(div, 1 << calcp);
|
||||
|
||||
*freq = (parent_rate >> calcp) / calcm;
|
||||
|
||||
/* we were called to round the frequency, we can now return */
|
||||
if (n == NULL)
|
||||
return;
|
||||
|
||||
*m = calcm - 1;
|
||||
*p = calcp;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
|
||||
|
|
@ -440,16 +401,6 @@ EXPORT_SYMBOL(clk_sunxi_mmc_phase_control);
|
|||
* sunxi_factors_clk_setup() - Setup function for factor clocks
|
||||
*/
|
||||
|
||||
#define SUNXI_FACTORS_MUX_MASK 0x3
|
||||
|
||||
struct factors_data {
|
||||
int enable;
|
||||
int mux;
|
||||
struct clk_factors_config *table;
|
||||
void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p);
|
||||
const char *name;
|
||||
};
|
||||
|
||||
static struct clk_factors_config sun4i_pll1_config = {
|
||||
.nshift = 8,
|
||||
.nwidth = 5,
|
||||
|
|
@ -503,14 +454,6 @@ static struct clk_factors_config sun4i_apb1_config = {
|
|||
.pwidth = 2,
|
||||
};
|
||||
|
||||
/* user manual says "n" but it's really "p" */
|
||||
static struct clk_factors_config sun4i_mod0_config = {
|
||||
.mshift = 0,
|
||||
.mwidth = 4,
|
||||
.pshift = 16,
|
||||
.pwidth = 2,
|
||||
};
|
||||
|
||||
/* user manual says "n" but it's really "p" */
|
||||
static struct clk_factors_config sun7i_a20_out_config = {
|
||||
.mshift = 8,
|
||||
|
|
@ -568,13 +511,6 @@ static const struct factors_data sun4i_apb1_data __initconst = {
|
|||
.getter = sun4i_get_apb1_factors,
|
||||
};
|
||||
|
||||
static const struct factors_data sun4i_mod0_data __initconst = {
|
||||
.enable = 31,
|
||||
.mux = 24,
|
||||
.table = &sun4i_mod0_config,
|
||||
.getter = sun4i_get_mod0_factors,
|
||||
};
|
||||
|
||||
static const struct factors_data sun7i_a20_out_data __initconst = {
|
||||
.enable = 31,
|
||||
.mux = 24,
|
||||
|
|
@ -583,89 +519,9 @@ static const struct factors_data sun7i_a20_out_data __initconst = {
|
|||
};
|
||||
|
||||
static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
|
||||
const struct factors_data *data)
|
||||
const struct factors_data *data)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct clk_factors *factors;
|
||||
struct clk_gate *gate = NULL;
|
||||
struct clk_mux *mux = NULL;
|
||||
struct clk_hw *gate_hw = NULL;
|
||||
struct clk_hw *mux_hw = NULL;
|
||||
const char *clk_name = node->name;
|
||||
const char *parents[SUNXI_MAX_PARENTS];
|
||||
void __iomem *reg;
|
||||
int i = 0;
|
||||
|
||||
reg = of_iomap(node, 0);
|
||||
|
||||
/* if we have a mux, we will have >1 parents */
|
||||
while (i < SUNXI_MAX_PARENTS &&
|
||||
(parents[i] = of_clk_get_parent_name(node, i)) != NULL)
|
||||
i++;
|
||||
|
||||
/*
|
||||
* some factor clocks, such as pll5 and pll6, may have multiple
|
||||
* outputs, and have their name designated in factors_data
|
||||
*/
|
||||
if (data->name)
|
||||
clk_name = data->name;
|
||||
else
|
||||
of_property_read_string(node, "clock-output-names", &clk_name);
|
||||
|
||||
factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
|
||||
if (!factors)
|
||||
return NULL;
|
||||
|
||||
/* Add a gate if this factor clock can be gated */
|
||||
if (data->enable) {
|
||||
gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
|
||||
if (!gate) {
|
||||
kfree(factors);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* set up gate properties */
|
||||
gate->reg = reg;
|
||||
gate->bit_idx = data->enable;
|
||||
gate->lock = &clk_lock;
|
||||
gate_hw = &gate->hw;
|
||||
}
|
||||
|
||||
/* Add a mux if this factor clock can be muxed */
|
||||
if (data->mux) {
|
||||
mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
|
||||
if (!mux) {
|
||||
kfree(factors);
|
||||
kfree(gate);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* set up gate properties */
|
||||
mux->reg = reg;
|
||||
mux->shift = data->mux;
|
||||
mux->mask = SUNXI_FACTORS_MUX_MASK;
|
||||
mux->lock = &clk_lock;
|
||||
mux_hw = &mux->hw;
|
||||
}
|
||||
|
||||
/* set up factors properties */
|
||||
factors->reg = reg;
|
||||
factors->config = data->table;
|
||||
factors->get_factors = data->getter;
|
||||
factors->lock = &clk_lock;
|
||||
|
||||
clk = clk_register_composite(NULL, clk_name,
|
||||
parents, i,
|
||||
mux_hw, &clk_mux_ops,
|
||||
&factors->hw, &clk_factors_ops,
|
||||
gate_hw, &clk_gate_ops, 0);
|
||||
|
||||
if (!IS_ERR(clk)) {
|
||||
of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
||||
clk_register_clkdev(clk, clk_name, NULL);
|
||||
}
|
||||
|
||||
return clk;
|
||||
return sunxi_factors_register(node, data, &clk_lock);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -762,10 +618,19 @@ static const struct div_data sun4i_ahb_data __initconst = {
|
|||
.width = 2,
|
||||
};
|
||||
|
||||
static const struct clk_div_table sun4i_apb0_table[] __initconst = {
|
||||
{ .val = 0, .div = 2 },
|
||||
{ .val = 1, .div = 2 },
|
||||
{ .val = 2, .div = 4 },
|
||||
{ .val = 3, .div = 8 },
|
||||
{ } /* sentinel */
|
||||
};
|
||||
|
||||
static const struct div_data sun4i_apb0_data __initconst = {
|
||||
.shift = 8,
|
||||
.pow = 1,
|
||||
.width = 2,
|
||||
.table = sun4i_apb0_table,
|
||||
};
|
||||
|
||||
static const struct div_data sun6i_a31_apb2_div_data __initconst = {
|
||||
|
|
@ -1199,7 +1064,6 @@ static const struct of_device_id clk_factors_match[] __initconst = {
|
|||
{.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,},
|
||||
{.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_data,},
|
||||
{.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
|
||||
{.compatible = "allwinner,sun4i-a10-mod0-clk", .data = &sun4i_mod0_data,},
|
||||
{.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
|
||||
{}
|
||||
};
|
||||
|
|
@ -1311,7 +1175,6 @@ static void __init sun4i_a10_init_clocks(struct device_node *node)
|
|||
CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sun4i_a10_init_clocks);
|
||||
|
||||
static const char *sun5i_critical_clocks[] __initdata = {
|
||||
"mbus",
|
||||
"pll5_ddr",
|
||||
"ahb_sdram",
|
||||
};
|
||||
|
|
|
|||
|
|
@ -46,6 +46,7 @@ struct clk {
|
|||
unsigned int enable_count;
|
||||
unsigned int prepare_count;
|
||||
unsigned long accuracy;
|
||||
int phase;
|
||||
struct hlist_head children;
|
||||
struct hlist_node child_node;
|
||||
struct hlist_node debug_node;
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
#ifdef CONFIG_COMMON_CLK
|
||||
|
||||
|
|
@ -129,6 +130,14 @@ struct dentry;
|
|||
* set then clock accuracy will be initialized to parent accuracy
|
||||
* or 0 (perfect clock) if clock has no parent.
|
||||
*
|
||||
* @get_phase: Queries the hardware to get the current phase of a clock.
|
||||
* Returned values are 0-359 degrees on success, negative
|
||||
* error codes on failure.
|
||||
*
|
||||
* @set_phase: Shift the phase this clock signal in degrees specified
|
||||
* by the second argument. Valid values for degrees are
|
||||
* 0-359. Return 0 on success, otherwise -EERROR.
|
||||
*
|
||||
* @init: Perform platform-specific initialization magic.
|
||||
* This is not not used by any of the basic clock types.
|
||||
* Please consider other ways of solving initialization problems
|
||||
|
|
@ -177,6 +186,8 @@ struct clk_ops {
|
|||
unsigned long parent_rate, u8 index);
|
||||
unsigned long (*recalc_accuracy)(struct clk_hw *hw,
|
||||
unsigned long parent_accuracy);
|
||||
int (*get_phase)(struct clk_hw *hw);
|
||||
int (*set_phase)(struct clk_hw *hw, int degrees);
|
||||
void (*init)(struct clk_hw *hw);
|
||||
int (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
|
||||
};
|
||||
|
|
|
|||
|
|
@ -106,6 +106,25 @@ int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb);
|
|||
*/
|
||||
long clk_get_accuracy(struct clk *clk);
|
||||
|
||||
/**
|
||||
* clk_set_phase - adjust the phase shift of a clock signal
|
||||
* @clk: clock signal source
|
||||
* @degrees: number of degrees the signal is shifted
|
||||
*
|
||||
* Shifts the phase of a clock signal by the specified degrees. Returns 0 on
|
||||
* success, -EERROR otherwise.
|
||||
*/
|
||||
int clk_set_phase(struct clk *clk, int degrees);
|
||||
|
||||
/**
|
||||
* clk_get_phase - return the phase shift of a clock signal
|
||||
* @clk: clock signal source
|
||||
*
|
||||
* Returns the phase shift of a clock node in degrees, otherwise returns
|
||||
* -EERROR.
|
||||
*/
|
||||
int clk_get_phase(struct clk *clk);
|
||||
|
||||
#else
|
||||
|
||||
static inline long clk_get_accuracy(struct clk *clk)
|
||||
|
|
@ -113,6 +132,16 @@ static inline long clk_get_accuracy(struct clk *clk)
|
|||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
static inline long clk_set_phase(struct clk *clk, int phase)
|
||||
{
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
static inline long clk_get_phase(struct clk *clk)
|
||||
{
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
|
|
|||
Loading…
Reference in New Issue