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drm/amdgpu/psp: add xgmi ta header
Add the psp xgmi driver interface. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef _TA_XGMI_IF_H
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#define _TA_XGMI_IF_H
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/* Responses have bit 31 set */
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#define RSP_ID_MASK (1U << 31)
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#define RSP_ID(cmdId) (((uint32_t)(cmdId)) | RSP_ID_MASK)
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enum ta_command_xgmi {
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TA_COMMAND_XGMI__INITIALIZE = 0x00,
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TA_COMMAND_XGMI__GET_NODE_ID = 0x01,
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TA_COMMAND_XGMI__GET_HIVE_ID = 0x02,
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TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO = 0x03,
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TA_COMMAND_XGMI__SET_TOPOLOGY_INFO = 0x04
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};
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/* XGMI related enumerations */
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/**********************************************************/;
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enum ta_xgmi_connected_nodes {
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TA_XGMI__MAX_CONNECTED_NODES = 64
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};
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enum ta_xgmi_status {
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TA_XGMI_STATUS__SUCCESS = 0x00,
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TA_XGMI_STATUS__GENERIC_FAILURE = 0x01,
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TA_XGMI_STATUS__NULL_POINTER = 0x02,
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TA_XGMI_STATUS__INVALID_PARAMETER = 0x03,
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TA_XGMI_STATUS__NOT_INITIALIZED = 0x04,
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TA_XGMI_STATUS__INVALID_NODE_NUM = 0x05,
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TA_XGMI_STATUS__INVALID_NODE_ID = 0x06,
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TA_XGMI_STATUS__INVALID_TOPOLOGY = 0x07,
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TA_XGMI_STATUS__FAILED_ID_GEN = 0x08,
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TA_XGMI_STATUS__FAILED_TOPOLOGY_INIT = 0x09,
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TA_XGMI_STATUS__SET_SHARING_ERROR = 0x0A
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};
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enum ta_xgmi_assigned_sdma_engine {
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TA_XGMI_ASSIGNED_SDMA_ENGINE__NOT_ASSIGNED = -1,
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TA_XGMI_ASSIGNED_SDMA_ENGINE__SDMA0 = 0,
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TA_XGMI_ASSIGNED_SDMA_ENGINE__SDMA1 = 1,
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TA_XGMI_ASSIGNED_SDMA_ENGINE__SDMA2 = 2,
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TA_XGMI_ASSIGNED_SDMA_ENGINE__SDMA3 = 3,
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TA_XGMI_ASSIGNED_SDMA_ENGINE__SDMA4 = 4,
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TA_XGMI_ASSIGNED_SDMA_ENGINE__SDMA5 = 5
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};
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/* input/output structures for XGMI commands */
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/**********************************************************/
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struct ta_xgmi_node_info {
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uint64_t node_id;
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uint8_t num_hops;
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uint8_t is_sharing_enabled;
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enum ta_xgmi_assigned_sdma_engine sdma_engine;
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};
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struct ta_xgmi_cmd_initialize_output {
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uint32_t status;
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};
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struct ta_xgmi_cmd_get_node_id_output {
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uint64_t node_id;
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};
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struct ta_xgmi_cmd_get_hive_id_output {
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uint64_t hive_id;
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};
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struct ta_xgmi_cmd_get_topology_info_input {
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uint32_t num_nodes;
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struct ta_xgmi_node_info nodes[TA_XGMI__MAX_CONNECTED_NODES];
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};
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struct ta_xgmi_cmd_get_topology_info_output {
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uint32_t num_nodes;
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struct ta_xgmi_node_info nodes[TA_XGMI__MAX_CONNECTED_NODES];
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};
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struct ta_xgmi_cmd_set_topology_info_input {
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uint32_t num_nodes;
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struct ta_xgmi_node_info nodes[TA_XGMI__MAX_CONNECTED_NODES];
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};
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/**********************************************************/
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/* Common input structure for XGMI callbacks */
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union ta_xgmi_cmd_input {
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struct ta_xgmi_cmd_get_topology_info_input get_topology_info;
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struct ta_xgmi_cmd_set_topology_info_input set_topology_info;
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};
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/* Common output structure for XGMI callbacks */
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union ta_xgmi_cmd_output {
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struct ta_xgmi_cmd_initialize_output initialize;
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struct ta_xgmi_cmd_get_node_id_output get_node_id;
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struct ta_xgmi_cmd_get_hive_id_output get_hive_id;
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struct ta_xgmi_cmd_get_topology_info_output get_topology_info;
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};
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/**********************************************************/
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struct ta_xgmi_shared_memory {
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uint32_t cmd_id;
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uint32_t resp_id;
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enum ta_xgmi_status xgmi_status;
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uint32_t reserved;
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union ta_xgmi_cmd_input xgmi_in_message;
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union ta_xgmi_cmd_output xgmi_out_message;
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};
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#endif //_TA_XGMI_IF_H
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