openkylin
/
linux
mirror of https://gitee.com/openkylin/linux.git
9
0
Fork 0
Code Issues Projects Releases Wiki Activity

drm/i915/vlv: add pll assertion when disabling DPIO common well 

When doing this, all PLLs should be disabled.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Jesse Barnes 2014-05-23 13:16:45 -07:00 committed by Daniel Vetter
parent f618e38ded
commit 4dfbd12c33
1 changed files with 4 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/i915/intel_pm.c
View File

@ -5711,9 +5711,11 @@ static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
void __vlv_set_power_well(struct drm_i915_private *dev_priv, void __vlv_set_power_well(struct drm_i915_private *dev_priv,
enum punit_power_well power_well_id, bool enable) enum punit_power_well power_well_id, bool enable)
{ {
struct drm_device *dev = dev_priv->dev;
u32 mask; u32 mask;
u32 state; u32 state;
u32 ctrl; u32 ctrl;
enum pipe pipe;
if (power_well_id == PUNIT_POWER_WELL_DPIO_CMN_BC) { if (power_well_id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
if (enable) { if (enable) {
@ -5727,6 +5729,8 @@ void __vlv_set_power_well(struct drm_i915_private *dev_priv,
DPLL_INTEGRATED_CRI_CLK_VLV); DPLL_INTEGRATED_CRI_CLK_VLV);
udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
} else { } else {
for_each_pipe(pipe)
assert_pll_disabled(dev_priv, pipe);
/* Assert common reset */ /* Assert common reset */
I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) &
~DPIO_CMNRST); ~DPIO_CMNRST);