mirror of https://gitee.com/openkylin/linux.git
Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: drm/radeon: add GET_PARAM/INFO support for Z pipes drm/radeon/kms: add r100/r200 OQ support. drm: Fix sysfs device confusion. drm/radeon/kms: implement the bo busy ioctl properly.
This commit is contained in:
commit
4dfd79e7b4
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@ -22,44 +22,50 @@
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#define to_drm_minor(d) container_of(d, struct drm_minor, kdev)
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#define to_drm_connector(d) container_of(d, struct drm_connector, kdev)
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static struct device_type drm_sysfs_device_minor = {
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.name = "drm_minor"
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};
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/**
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* drm_sysfs_suspend - DRM class suspend hook
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* drm_class_suspend - DRM class suspend hook
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* @dev: Linux device to suspend
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* @state: power state to enter
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*
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* Just figures out what the actual struct drm_device associated with
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* @dev is and calls its suspend hook, if present.
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*/
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static int drm_sysfs_suspend(struct device *dev, pm_message_t state)
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static int drm_class_suspend(struct device *dev, pm_message_t state)
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{
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struct drm_minor *drm_minor = to_drm_minor(dev);
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struct drm_device *drm_dev = drm_minor->dev;
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if (drm_minor->type == DRM_MINOR_LEGACY &&
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!drm_core_check_feature(drm_dev, DRIVER_MODESET) &&
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drm_dev->driver->suspend)
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return drm_dev->driver->suspend(drm_dev, state);
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if (dev->type == &drm_sysfs_device_minor) {
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struct drm_minor *drm_minor = to_drm_minor(dev);
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struct drm_device *drm_dev = drm_minor->dev;
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if (drm_minor->type == DRM_MINOR_LEGACY &&
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!drm_core_check_feature(drm_dev, DRIVER_MODESET) &&
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drm_dev->driver->suspend)
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return drm_dev->driver->suspend(drm_dev, state);
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}
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return 0;
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}
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/**
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* drm_sysfs_resume - DRM class resume hook
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* drm_class_resume - DRM class resume hook
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* @dev: Linux device to resume
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*
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* Just figures out what the actual struct drm_device associated with
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* @dev is and calls its resume hook, if present.
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*/
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static int drm_sysfs_resume(struct device *dev)
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static int drm_class_resume(struct device *dev)
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{
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struct drm_minor *drm_minor = to_drm_minor(dev);
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struct drm_device *drm_dev = drm_minor->dev;
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if (drm_minor->type == DRM_MINOR_LEGACY &&
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!drm_core_check_feature(drm_dev, DRIVER_MODESET) &&
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drm_dev->driver->resume)
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return drm_dev->driver->resume(drm_dev);
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if (dev->type == &drm_sysfs_device_minor) {
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struct drm_minor *drm_minor = to_drm_minor(dev);
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struct drm_device *drm_dev = drm_minor->dev;
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if (drm_minor->type == DRM_MINOR_LEGACY &&
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!drm_core_check_feature(drm_dev, DRIVER_MODESET) &&
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drm_dev->driver->resume)
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return drm_dev->driver->resume(drm_dev);
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}
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return 0;
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}
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@ -99,8 +105,8 @@ struct class *drm_sysfs_create(struct module *owner, char *name)
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goto err_out;
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}
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class->suspend = drm_sysfs_suspend;
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class->resume = drm_sysfs_resume;
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class->suspend = drm_class_suspend;
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class->resume = drm_class_resume;
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err = class_create_file(class, &class_attr_version);
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if (err)
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@ -480,6 +486,7 @@ int drm_sysfs_device_add(struct drm_minor *minor)
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minor->kdev.class = drm_class;
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minor->kdev.release = drm_sysfs_device_release;
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minor->kdev.devt = minor->device;
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minor->kdev.type = &drm_sysfs_device_minor;
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if (minor->type == DRM_MINOR_CONTROL)
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minor_str = "controlD%d";
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else if (minor->type == DRM_MINOR_RENDER)
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@ -1091,6 +1091,16 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
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tmp |= tile_flags;
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ib[idx] = tmp;
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break;
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case RADEON_RB3D_ZPASS_ADDR:
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r = r100_cs_packet_next_reloc(p, &reloc);
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if (r) {
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DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
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idx, reg);
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r100_cs_dump_packet(p, pkt);
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return r;
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}
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ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
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break;
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default:
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/* FIXME: we don't want to allow anyothers packet */
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break;
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@ -448,6 +448,7 @@ void r300_gpu_init(struct radeon_device *rdev)
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/* rv350,rv370,rv380 */
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rdev->num_gb_pipes = 1;
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}
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rdev->num_z_pipes = 1;
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gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
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switch (rdev->num_gb_pipes) {
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case 2:
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@ -486,7 +487,8 @@ void r300_gpu_init(struct radeon_device *rdev)
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printk(KERN_WARNING "Failed to wait MC idle while "
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"programming pipes. Bad things might happen.\n");
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}
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DRM_INFO("radeon: %d pipes initialized.\n", rdev->num_gb_pipes);
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DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
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rdev->num_gb_pipes, rdev->num_z_pipes);
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}
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int r300_ga_reset(struct radeon_device *rdev)
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@ -165,7 +165,18 @@ void r420_pipes_init(struct radeon_device *rdev)
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printk(KERN_WARNING "Failed to wait GUI idle while "
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"programming pipes. Bad things might happen.\n");
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}
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DRM_INFO("radeon: %d pipes initialized.\n", rdev->num_gb_pipes);
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if (rdev->family == CHIP_RV530) {
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tmp = RREG32(RV530_GB_PIPE_SELECT2);
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if ((tmp & 3) == 3)
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rdev->num_z_pipes = 2;
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else
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rdev->num_z_pipes = 1;
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} else
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rdev->num_z_pipes = 1;
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DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
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rdev->num_gb_pipes, rdev->num_z_pipes);
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}
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void r420_gpu_init(struct radeon_device *rdev)
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@ -177,7 +177,6 @@ void r520_gpu_init(struct radeon_device *rdev)
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*/
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/* workaround for RV530 */
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if (rdev->family == CHIP_RV530) {
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WREG32(0x4124, 1);
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WREG32(0x4128, 0xFF);
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}
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r420_pipes_init(rdev);
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@ -655,6 +655,7 @@ struct radeon_device {
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int usec_timeout;
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enum radeon_pll_errata pll_errata;
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int num_gb_pipes;
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int num_z_pipes;
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int disp_priority;
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/* BIOS */
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uint8_t *bios;
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@ -406,6 +406,15 @@ static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
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{
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uint32_t gb_tile_config, gb_pipe_sel = 0;
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if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) {
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uint32_t z_pipe_sel = RADEON_READ(RV530_GB_PIPE_SELECT2);
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if ((z_pipe_sel & 3) == 3)
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dev_priv->num_z_pipes = 2;
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else
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dev_priv->num_z_pipes = 1;
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} else
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dev_priv->num_z_pipes = 1;
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/* RS4xx/RS6xx/R4xx/R5xx */
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
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gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
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@ -100,9 +100,10 @@
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* 1.28- Add support for VBL on CRTC2
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* 1.29- R500 3D cmd buffer support
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* 1.30- Add support for occlusion queries
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* 1.31- Add support for num Z pipes from GET_PARAM
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*/
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#define DRIVER_MAJOR 1
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#define DRIVER_MINOR 30
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#define DRIVER_MINOR 31
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#define DRIVER_PATCHLEVEL 0
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/*
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@ -329,6 +330,7 @@ typedef struct drm_radeon_private {
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resource_size_t fb_aper_offset;
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int num_gb_pipes;
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int num_z_pipes;
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int track_flush;
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drm_local_map_t *mmio;
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/* pipe config regs */
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#define R400_GB_PIPE_SELECT 0x402c
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#define RV530_GB_PIPE_SELECT2 0x4124
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#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */
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#define R300_GB_TILE_CONFIG 0x4018
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# define R300_ENABLE_TILING (1 << 0)
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@ -283,7 +283,7 @@ int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
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mutex_lock(&dev->struct_mutex);
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drm_gem_object_unreference(gobj);
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mutex_unlock(&dev->struct_mutex);
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return 0;
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return r;
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}
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int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
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@ -95,6 +95,9 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
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case RADEON_INFO_NUM_GB_PIPES:
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value = rdev->num_gb_pipes;
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break;
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case RADEON_INFO_NUM_Z_PIPES:
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value = rdev->num_z_pipes;
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break;
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default:
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DRM_DEBUG("Invalid request %d\n", info->request);
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return -EINVAL;
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DRM_IOCTL_DEF(DRM_RADEON_INFO, radeon_info_ioctl, DRM_AUTH),
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DRM_IOCTL_DEF(DRM_RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH),
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DRM_IOCTL_DEF(DRM_RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH),
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DRM_IOCTL_DEF(DRM_RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH),
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};
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int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);
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@ -2337,6 +2337,9 @@
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# define RADEON_RE_WIDTH_SHIFT 0
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# define RADEON_RE_HEIGHT_SHIFT 16
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#define RADEON_RB3D_ZPASS_DATA 0x3290
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#define RADEON_RB3D_ZPASS_ADDR 0x3294
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#define RADEON_SE_CNTL 0x1c4c
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# define RADEON_FFACE_CULL_CW (0 << 0)
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# define RADEON_FFACE_CULL_CCW (1 << 0)
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#define RADEON_SCRATCH_REG4 0x15f0
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#define RADEON_SCRATCH_REG5 0x15f4
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#define RV530_GB_PIPE_SELECT2 0x4124
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#endif
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@ -3081,6 +3081,9 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
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case RADEON_PARAM_NUM_GB_PIPES:
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value = dev_priv->num_gb_pipes;
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break;
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case RADEON_PARAM_NUM_Z_PIPES:
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value = dev_priv->num_z_pipes;
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break;
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default:
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DRM_DEBUG("Invalid parameter %d\n", param->param);
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return -EINVAL;
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@ -508,6 +508,7 @@ typedef struct {
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#define DRM_RADEON_INFO 0x27
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#define DRM_RADEON_GEM_SET_TILING 0x28
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#define DRM_RADEON_GEM_GET_TILING 0x29
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#define DRM_RADEON_GEM_BUSY 0x2a
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#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
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#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)
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@ -548,6 +549,7 @@ typedef struct {
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#define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info)
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#define DRM_IOCTL_RADEON_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling)
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#define DRM_IOCTL_RADEON_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling)
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#define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy)
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typedef struct drm_radeon_init {
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enum {
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#define RADEON_PARAM_FB_LOCATION 14 /* FB location */
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#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */
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#define RADEON_PARAM_DEVICE_ID 16
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#define RADEON_PARAM_NUM_Z_PIPES 17 /* num Z pipes */
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typedef struct drm_radeon_getparam {
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int param;
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@ -895,6 +898,7 @@ struct drm_radeon_cs {
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#define RADEON_INFO_DEVICE_ID 0x00
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#define RADEON_INFO_NUM_GB_PIPES 0x01
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#define RADEON_INFO_NUM_Z_PIPES 0x02
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struct drm_radeon_info {
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uint32_t request;
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