mirror of https://gitee.com/openkylin/linux.git
drm/i915/cnl: Setup PAT Index.
Different from previous platforms, on CNL+ there's separated registers for separated indexes. v2: Remove comments regarding uncertainty around the table. v3: Remove extra line (by Ben) Cc: Clint Taylor <clinton.a.taylor@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170815232539.3562-1-rodrigo.vivi@intel.com
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@ -2742,6 +2742,24 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
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return 0;
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}
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static void cnl_setup_private_ppat(struct drm_i915_private *dev_priv)
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{
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/* XXX: spec is unclear if this is still needed for CNL+ */
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if (!USES_PPGTT(dev_priv)) {
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I915_WRITE(GEN10_PAT_INDEX(0), GEN8_PPAT_UC);
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return;
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}
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I915_WRITE(GEN10_PAT_INDEX(0), GEN8_PPAT_WB | GEN8_PPAT_LLC);
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I915_WRITE(GEN10_PAT_INDEX(1), GEN8_PPAT_WC | GEN8_PPAT_LLCELLC);
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I915_WRITE(GEN10_PAT_INDEX(2), GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
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I915_WRITE(GEN10_PAT_INDEX(3), GEN8_PPAT_UC);
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I915_WRITE(GEN10_PAT_INDEX(4), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
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I915_WRITE(GEN10_PAT_INDEX(5), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1));
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I915_WRITE(GEN10_PAT_INDEX(6), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2));
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I915_WRITE(GEN10_PAT_INDEX(7), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
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}
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/* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
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* bits. When using advanced contexts each context stores its own PAT, but
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* writing this data shouldn't be harmful even in those cases. */
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@ -2856,7 +2874,9 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
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ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
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if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
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if (INTEL_GEN(dev_priv) >= 10)
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cnl_setup_private_ppat(dev_priv);
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else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
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chv_setup_private_ppat(dev_priv);
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else
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bdw_setup_private_ppat(dev_priv);
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@ -3138,7 +3158,9 @@ void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
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ggtt->base.closed = false;
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if (INTEL_GEN(dev_priv) >= 8) {
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if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
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if (INTEL_GEN(dev_priv) >= 10)
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cnl_setup_private_ppat(dev_priv);
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else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
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chv_setup_private_ppat(dev_priv);
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else
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bdw_setup_private_ppat(dev_priv);
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@ -2336,6 +2336,7 @@ enum i915_power_well_id {
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#define DONE_REG _MMIO(0x40b0)
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#define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0)
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#define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4)
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#define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + index*4)
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#define BSD_HWS_PGA_GEN7 _MMIO(0x04180)
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#define BLT_HWS_PGA_GEN7 _MMIO(0x04280)
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#define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380)
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