mirror of https://gitee.com/openkylin/linux.git
[media] coda: move cache setup into coda9_set_frame_cache, also use it in start_encoding
The frame cache should be set up correctly to encode NV12 source frames. This was not done before, so move the cache setup out of start_decoding into its own function and call it from both start_encoding and start_decoding. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
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@ -721,6 +721,26 @@ int coda_check_firmware(struct coda_dev *dev)
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return ret;
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return ret;
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}
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}
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static void coda9_set_frame_cache(struct coda_ctx *ctx, u32 fourcc)
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{
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u32 cache_size, cache_config;
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/* Luma 2x0 page, 2x6 cache, chroma 2x0 page, 2x4 cache size */
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cache_size = 0x20262024;
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cache_config = 2 << CODA9_CACHE_PAGEMERGE_OFFSET;
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coda_write(ctx->dev, cache_size, CODA9_CMD_SET_FRAME_CACHE_SIZE);
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if (fourcc == V4L2_PIX_FMT_NV12) {
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cache_config |= 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |
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16 << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET |
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0 << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET;
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} else {
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cache_config |= 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |
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8 << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET |
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8 << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET;
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}
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coda_write(ctx->dev, cache_config, CODA9_CMD_SET_FRAME_CACHE_CONFIG);
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}
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/*
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/*
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* Encoder context operations
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* Encoder context operations
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*/
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*/
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@ -1049,6 +1069,8 @@ static int coda_start_encoding(struct coda_ctx *ctx)
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coda_write(dev, ctx->iram_info.buf_btp_use,
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coda_write(dev, ctx->iram_info.buf_btp_use,
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CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
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CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
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coda9_set_frame_cache(ctx, q_data_src->fourcc);
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/* FIXME */
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/* FIXME */
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coda_write(dev, ctx->internal_frames[2].paddr,
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coda_write(dev, ctx->internal_frames[2].paddr,
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CODA9_CMD_SET_FRAME_SUBSAMP_A);
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CODA9_CMD_SET_FRAME_SUBSAMP_A);
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@ -1606,30 +1628,13 @@ static int __coda_start_decoding(struct coda_ctx *ctx)
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CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
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CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
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coda_write(dev, ctx->iram_info.buf_ovl_use,
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coda_write(dev, ctx->iram_info.buf_ovl_use,
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CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
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CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
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if (dev->devtype->product == CODA_960)
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if (dev->devtype->product == CODA_960) {
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coda_write(dev, ctx->iram_info.buf_btp_use,
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coda_write(dev, ctx->iram_info.buf_btp_use,
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CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
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CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
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}
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if (dev->devtype->product == CODA_960) {
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coda_write(dev, -1, CODA9_CMD_SET_FRAME_DELAY);
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int cbb_size, crb_size;
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coda9_set_frame_cache(ctx, dst_fourcc);
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coda_write(dev, -1, CODA9_CMD_SET_FRAME_DELAY);
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/* Luma 2x0 page, 2x6 cache, chroma 2x0 page, 2x4 cache size */
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coda_write(dev, 0x20262024, CODA9_CMD_SET_FRAME_CACHE_SIZE);
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if (dst_fourcc == V4L2_PIX_FMT_NV12) {
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cbb_size = 0;
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crb_size = 16;
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} else {
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cbb_size = 8;
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crb_size = 8;
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}
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}
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coda_write(dev, 2 << CODA9_CACHE_PAGEMERGE_OFFSET |
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32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |
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cbb_size << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET |
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crb_size << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET,
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CODA9_CMD_SET_FRAME_CACHE_CONFIG);
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}
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}
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if (src_fourcc == V4L2_PIX_FMT_H264) {
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if (src_fourcc == V4L2_PIX_FMT_H264) {
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