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mvebu dt64 for 4.20 (part 2) 

- Add System Error Interrupt support to Armada SoCs (7K/8K)
  - Add CPU idle support on Armada 8K
 -----BEGIN PGP SIGNATURE-----
 
 iFwEABECAB0WIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCW7Y4zAAKCRALBhiOFHI7
 1QMVAKCqI2E6bf9ZiombIqMC/6/3IyxBMQCYxOCnpIbMbfaaufLkOf2XgOnq7g==
 =KspX
 -----END PGP SIGNATURE-----

Merge tag 'mvebu-dt64-4.20-2' of git://git.infradead.org/linux-mvebu into next/dt

mvebu dt64 for 4.20 (part 2)

 - Add System Error Interrupt support to Armada SoCs (7K/8K)
 - Add CPU idle support on Armada 8K

* tag 'mvebu-dt64-4.20-2' of git://git.infradead.org/linux-mvebu:
  arm64: dts: clearfog-gt-8k: add PCIe slot description
  arm64: dts: marvell: add CP110 ICU SEI subnode
  arm64: dts: marvell: use new bindings for CP110 interrupts
  arm64: dts: marvell: add AP806 SEI subnode
  arm64: dts: marvell: add CPU Idle power state support on Armada 7K/8K
  arm64: dts: marvell: Add node labels for the cpus

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2018-10-05 17:22:59 +02:00
parent 38764692af 91f84690b5
commit 4e6a32e6eb
8 changed files with 145 additions and 83 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm64/boot/dts/marvell/armada-372x.dtsi
View File

@ -16,7 +16,7 @@ / {
compatible = "marvell,armada3720", "marvell,armada3710";
cpus {
cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x1>;

2
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
View File

@ -40,7 +40,7 @@ psci-area@4000000 {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0>;

7
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
View File

@ -233,6 +233,13 @@ cp0_sdhci_pins: sdhci-pins {
};
};
&cp0_pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&cp0_pci0_reset_pins>;
reset-gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
status = "okay";
};
&cp0_gpio2 {
sata_reset {
gpio-hog;

4
arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
View File

@ -15,13 +15,13 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x000>;
enable-method = "psci";
};
cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x001>;

12
arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
View File

@ -15,29 +15,33 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x000>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
};
cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x001>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
};
cpu@100 {
cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x100>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
};
cpu@101 {
cpu3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x101>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
};
};
};

36
arch/arm64/boot/dts/marvell/armada-ap806.dtsi
View File

@ -28,6 +28,33 @@ psci {
method = "smc";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
idle_states {
entry_method = "arm,pcsi";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
local-timer-stop;
arm,psci-suspend-param = <0x0010000>;
entry-latency-us = <80>;
exit-latency-us = <160>;
min-residency-us = <320>;
};
CLUSTER_SLEEP_0: cluster-sleep-0 {
compatible = "arm,idle-state";
local-timer-stop;
arm,psci-suspend-param = <0x1010000>;
entry-latency-us = <500>;
exit-latency-us = <1000>;
min-residency-us = <2500>;
};
};
};
ap806 {
#address-cells = <2>;
#size-cells = <2>;
@ -125,6 +152,15 @@ pic: interrupt-controller@3f0100 {
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
sei: interrupt-controller@3f0200 {
compatible = "marvell,ap806-sei";
reg = <0x3f0200 0x40>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
interrupt-controller;
msi-controller;
};
xor@400000 {
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x400000 0x1000>,

16
arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi
View File

@ -13,49 +13,49 @@ cpus {
#size-cells = <0>;
compatible = "marvell,armada-ap810-octa";
cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x000>;
enable-method = "psci";
};
cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x001>;
enable-method = "psci";
};
cpu@100 {
cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x100>;
enable-method = "psci";
};
cpu@101 {
cpu3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x101>;
enable-method = "psci";
};
cpu@200 {
cpu4: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x200>;
enable-method = "psci";
};
cpu@201 {
cpu5: cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x201>;
enable-method = "psci";
};
cpu@300 {
cpu6: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x300>;
enable-method = "psci";
};
cpu@301 {
cpu7: cpu@301 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x301>;

149
arch/arm64/boot/dts/marvell/armada-cp110.dtsi
View File

@ -43,7 +43,7 @@ &CP110_NAME {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
interrupt-parent = <&CP110_LABEL(icu)>;
interrupt-parent = <&CP110_LABEL(icu_nsr)>;
ranges;
config-space@CP110_BASE {
@ -65,16 +65,16 @@ CP110_LABEL(ethernet): ethernet@0 {
dma-coherent;
CP110_LABEL(eth0): eth0 {
interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 59 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 63 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 67 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 71 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <39 IRQ_TYPE_LEVEL_HIGH>,
<43 IRQ_TYPE_LEVEL_HIGH>,
<47 IRQ_TYPE_LEVEL_HIGH>,
<51 IRQ_TYPE_LEVEL_HIGH>,
<55 IRQ_TYPE_LEVEL_HIGH>,
<59 IRQ_TYPE_LEVEL_HIGH>,
<63 IRQ_TYPE_LEVEL_HIGH>,
<67 IRQ_TYPE_LEVEL_HIGH>,
<71 IRQ_TYPE_LEVEL_HIGH>,
<129 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hif0", "hif1", "hif2",
"hif3", "hif4", "hif5", "hif6", "hif7",
"hif8", "link";
@ -84,16 +84,16 @@ CP110_LABEL(eth0): eth0 {
};
CP110_LABEL(eth1): eth1 {
interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 60 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 64 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 68 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 72 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <40 IRQ_TYPE_LEVEL_HIGH>,
<44 IRQ_TYPE_LEVEL_HIGH>,
<48 IRQ_TYPE_LEVEL_HIGH>,
<52 IRQ_TYPE_LEVEL_HIGH>,
<56 IRQ_TYPE_LEVEL_HIGH>,
<60 IRQ_TYPE_LEVEL_HIGH>,
<64 IRQ_TYPE_LEVEL_HIGH>,
<68 IRQ_TYPE_LEVEL_HIGH>,
<72 IRQ_TYPE_LEVEL_HIGH>,
<128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hif0", "hif1", "hif2",
"hif3", "hif4", "hif5", "hif6", "hif7",
"hif8", "link";
@ -103,16 +103,16 @@ CP110_LABEL(eth1): eth1 {
};
CP110_LABEL(eth2): eth2 {
interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 61 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 65 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 69 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 73 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <41 IRQ_TYPE_LEVEL_HIGH>,
<45 IRQ_TYPE_LEVEL_HIGH>,
<49 IRQ_TYPE_LEVEL_HIGH>,
<53 IRQ_TYPE_LEVEL_HIGH>,
<57 IRQ_TYPE_LEVEL_HIGH>,
<61 IRQ_TYPE_LEVEL_HIGH>,
<65 IRQ_TYPE_LEVEL_HIGH>,
<69 IRQ_TYPE_LEVEL_HIGH>,
<73 IRQ_TYPE_LEVEL_HIGH>,
<127 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hif0", "hif1", "hif2",
"hif3", "hif4", "hif5", "hif6", "hif7",
"hif8", "link";
@ -183,16 +183,31 @@ CP110_LABEL(xmdio): mdio@12a600 {
CP110_LABEL(icu): interrupt-controller@1e0000 {
compatible = "marvell,cp110-icu";
reg = <0x1e0000 0x440>;
#interrupt-cells = <3>;
interrupt-controller;
msi-parent = <&gicp>;
#address-cells = <1>;
#size-cells = <1>;
CP110_LABEL(icu_nsr): interrupt-controller@10 {
compatible = "marvell,cp110-icu-nsr";
reg = <0x10 0x20>;
#interrupt-cells = <2>;
interrupt-controller;
msi-parent = <&gicp>;
};
CP110_LABEL(icu_sei): interrupt-controller@50 {
compatible = "marvell,cp110-icu-sei";
reg = <0x50 0x10>;
#interrupt-cells = <2>;
interrupt-controller;
msi-parent = <&sei>;
};
};
CP110_LABEL(rtc): rtc@284000 {
compatible = "marvell,armada-8k-rtc";
reg = <0x284000 0x20>, <0x284080 0x24>;
reg-names = "rtc", "rtc-soc";
interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
};
CP110_LABEL(syscon0): system-controller@440000 {
@ -212,10 +227,10 @@ CP110_LABEL(gpio1): gpio@100 {
#gpio-cells = <2>;
gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
interrupt-controller;
interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
<85 IRQ_TYPE_LEVEL_HIGH>,
<84 IRQ_TYPE_LEVEL_HIGH>,
<83 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@ -227,10 +242,10 @@ CP110_LABEL(gpio2): gpio@140 {
#gpio-cells = <2>;
gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>;
interrupt-controller;
interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
<81 IRQ_TYPE_LEVEL_HIGH>,
<80 IRQ_TYPE_LEVEL_HIGH>,
<79 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};
@ -253,7 +268,7 @@ CP110_LABEL(usb3_0): usb3@500000 {
"generic-xhci";
reg = <0x500000 0x4000>;
dma-coherent;
interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 22>,
<&CP110_LABEL(clk) 1 16>;
@ -265,7 +280,7 @@ CP110_LABEL(usb3_1): usb3@510000 {
"generic-xhci";
reg = <0x510000 0x4000>;
dma-coherent;
interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <105 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 23>,
<&CP110_LABEL(clk) 1 16>;
@ -277,7 +292,7 @@ CP110_LABEL(sata0): sata@540000 {
"generic-ahci";
reg = <0x540000 0x30000>;
dma-coherent;
interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&CP110_LABEL(clk) 1 15>,
<&CP110_LABEL(clk) 1 16>;
status = "disabled";
@ -330,7 +345,7 @@ CP110_LABEL(i2c0): i2c@701000 {
reg = <0x701000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 21>,
<&CP110_LABEL(clk) 1 17>;
@ -342,7 +357,7 @@ CP110_LABEL(i2c1): i2c@701100 {
reg = <0x701100 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 21>,
<&CP110_LABEL(clk) 1 17>;
@ -353,7 +368,7 @@ CP110_LABEL(uart0): serial@702000 {
compatible = "snps,dw-apb-uart";
reg = <0x702000 0x100>;
reg-shift = <2>;
interrupts = <ICU_GRP_NSR 122 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clock-names = "baudclk", "apb_pclk";
clocks = <&CP110_LABEL(clk) 1 21>,
@ -365,7 +380,7 @@ CP110_LABEL(uart1): serial@702100 {
compatible = "snps,dw-apb-uart";
reg = <0x702100 0x100>;
reg-shift = <2>;
interrupts = <ICU_GRP_NSR 123 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clock-names = "baudclk", "apb_pclk";
clocks = <&CP110_LABEL(clk) 1 21>,
@ -377,7 +392,7 @@ CP110_LABEL(uart2): serial@702200 {
compatible = "snps,dw-apb-uart";
reg = <0x702200 0x100>;
reg-shift = <2>;
interrupts = <ICU_GRP_NSR 124 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clock-names = "baudclk", "apb_pclk";
clocks = <&CP110_LABEL(clk) 1 21>,
@ -389,7 +404,7 @@ CP110_LABEL(uart3): serial@702300 {
compatible = "snps,dw-apb-uart";
reg = <0x702300 0x100>;
reg-shift = <2>;
interrupts = <ICU_GRP_NSR 125 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clock-names = "baudclk", "apb_pclk";
clocks = <&CP110_LABEL(clk) 1 21>,
@ -408,7 +423,7 @@ CP110_LABEL(nand_controller): nand@720000 {
reg = <0x720000 0x54>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 2>,
<&CP110_LABEL(clk) 1 17>;
@ -420,7 +435,7 @@ CP110_LABEL(trng): trng@760000 {
compatible = "marvell,armada-8k-rng",
"inside-secure,safexcel-eip76";
reg = <0x760000 0x7d>;
interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 25>,
<&CP110_LABEL(clk) 1 17>;
@ -430,7 +445,7 @@ CP110_LABEL(trng): trng@760000 {
CP110_LABEL(sdhci0): sdhci@780000 {
compatible = "marvell,armada-cp110-sdhci";
reg = <0x780000 0x300>;
interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "axi";
clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1 18>;
dma-coherent;
@ -440,12 +455,12 @@ CP110_LABEL(sdhci0): sdhci@780000 {
CP110_LABEL(crypto): crypto@800000 {
compatible = "inside-secure,safexcel-eip197b";
reg = <0x800000 0x200000>;
interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <87 IRQ_TYPE_LEVEL_HIGH>,
<88 IRQ_TYPE_LEVEL_HIGH>,
<89 IRQ_TYPE_LEVEL_HIGH>,
<90 IRQ_TYPE_LEVEL_HIGH>,
<91 IRQ_TYPE_LEVEL_HIGH>,
<92 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mem", "ring0", "ring1",
"ring2", "ring3", "eip";
clock-names = "core", "reg";
@ -474,8 +489,8 @@ CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE {
/* non-prefetchable memory */
0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0) 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>;
@ -501,8 +516,8 @@ CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE {
/* non-prefetchable memory */
0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1) 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clock-names = "core", "reg";
@ -529,8 +544,8 @@ CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE {
/* non-prefetchable memory */
0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2) 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clock-names = "core", "reg";