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sparc64: Add a comment about why we only use certain memory barriers these days. 

Based upon feedback from Mathieu Desnoyers.

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2009-11-05 20:24:33 -08:00
parent 03717e3d12
commit 4eb0c00b62
1 changed files with 4 additions and 0 deletions
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4
arch/sparc/include/asm/system_64.h
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@ -63,6 +63,10 @@ do { __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \
: : : "memory"); \ : : : "memory"); \
} while (0) } while (0)
/* The kernel always executes in TSO memory model these days,
* and furthermore most sparc64 chips implement more stringent
* memory ordering than required by the specifications.
*/
#define mb() membar_safe("#StoreLoad") #define mb() membar_safe("#StoreLoad")
#define rmb() __asm__ __volatile__("":::"memory") #define rmb() __asm__ __volatile__("":::"memory")
#define wmb() __asm__ __volatile__("":::"memory") #define wmb() __asm__ __volatile__("":::"memory")