mirror of https://gitee.com/openkylin/linux.git
ARM: dts: Make CPU configuration more readable on exynos542x/5800
Exynos5420 and Exynos5800 boards boot from big core (A15) but Exynos5422 boards choose otherwise: LITTLE core (A7) (on Exynos5422 this is property of the board - configurable by pulling up/down gpg2-1). To make user-visible CPU ordering more consistent the 'cpus' node was overridden by exynos5422-cpus.dtsi. However this is a little bit ugly and error-prone. Overriding the CPU child nodes requires to basically reverse what was done initially in exynos5420.dtsi. Instead, split CPU configuration entirely to separate files which should be included by board DTS. Suggested-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org> Reviewed-by: Chanho Park <parkch98@gmail.com>
This commit is contained in:
Krzysztof Kozlowski
parent
145794121f
commit
4f0d20ec19
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@ -11,6 +11,7 @@
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/dts-v1/;
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#include "exynos5420.dtsi"
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#include "exynos5420-cpus.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/input/input.h>
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@ -0,0 +1,92 @@
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/*
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* SAMSUNG EXYNOS5420 SoC cpu device tree source
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*
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* Copyright (c) 2015 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* This file provides desired ordering for Exynos5420 and Exynos5800
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* boards: CPU[0123] being the A15.
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*
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* The Exynos5420, 5422 and 5800 actually share the same CPU configuration
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* but particular boards choose different booting order.
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*
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* Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
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* booting cluster (big or LITTLE) is chosen by IROM code by reading
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* the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
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* from the LITTLE: Cortex-A7.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x0>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x1>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x2>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x3>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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};
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cpu4: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x100>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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};
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cpu5: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x101>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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};
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cpu6: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x102>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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};
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cpu7: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x103>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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};
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};
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};
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@ -15,6 +15,7 @@
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#include <dt-bindings/clock/maxim,max77802.h>
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#include <dt-bindings/regulator/maxim,max77802.h>
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#include "exynos5420.dtsi"
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#include "exynos5420-cpus.dtsi"
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/ {
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model = "Google Peach Pit Rev 6+";
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@ -11,6 +11,7 @@
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/dts-v1/;
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#include "exynos5420.dtsi"
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#include "exynos5420-cpus.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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@ -50,74 +50,10 @@ aliases {
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usbdrdphy1 = &usbdrd_phy1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x0>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x1>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x2>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x3>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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};
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cpu4: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x100>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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};
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cpu5: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x101>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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};
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cpu6: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x102>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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};
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cpu7: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x103>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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};
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};
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/*
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* The 'cpus' node is not present here but instead it is provided
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* by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
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*/
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cci: cci@10d20000 {
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compatible = "arm,cci-400";
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@ -4,78 +4,88 @@
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* Copyright (c) 2015 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* The only difference between EXYNOS5422 and EXYNOS5800 is cpu ordering. The
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* EXYNOS5422 is booting from Cortex-A7 core while the EXYNOS5800 is booting
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* from Cortex-A15 core.
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* This file provides desired ordering for Exynos5422: CPU[0123] being the A7.
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*
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* EXYNOS5422 based board files can include this file to provide cpu ordering
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* which could boot a cortex-a7 from cpu0.
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* The Exynos5420, 5422 and 5800 actually share the same CPU configuration
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* but particular boards choose different booting order.
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*
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* Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
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* booting cluster (big or LITTLE) is chosen by IROM code by reading
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* the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
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* from the LITTLE: Cortex-A7.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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&cpu0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x100>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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};
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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&cpu1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x101>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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};
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cpu0: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x100>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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};
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&cpu2 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x102>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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};
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cpu1: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x101>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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};
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&cpu3 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x103>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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};
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cpu2: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x102>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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};
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&cpu4 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x0>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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};
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cpu3: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x103>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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};
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&cpu5 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x1>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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};
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cpu4: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x0>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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};
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&cpu6 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x2>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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};
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cpu5: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x1>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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};
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&cpu7 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x3>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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cpu6: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x2>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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};
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cpu7: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x3>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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};
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};
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};
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@ -15,6 +15,7 @@
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#include <dt-bindings/clock/maxim,max77802.h>
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#include <dt-bindings/regulator/maxim,max77802.h>
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#include "exynos5800.dtsi"
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#include "exynos5420-cpus.dtsi"
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/ {
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model = "Google Peach Pi Rev 10+";
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