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memory: tegra: Consolidate register fields 

Subsequent patches will add more register fields to the tegra_mc_client
structure, so consolidate all register field definitions into a common
sub-structure for coherency.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20210602163302.120041-2-thierry.reding@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
This commit is contained in:
Thierry Reding 2021-06-02 18:32:51 +02:00 committed by Krzysztof Kozlowski
parent eeafcdea46
commit 4f1ac76e5e
7 changed files with 2933 additions and 2394 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
drivers/iommu/tegra-smmu.c
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@ -376,9 +376,9 @@ static void tegra_smmu_enable(struct tegra_smmu *smmu, unsigned int swgroup,
if (client->swgroup != swgroup)
continue;
value = smmu_readl(smmu, client->smmu.reg);
value |= BIT(client->smmu.bit);
smmu_writel(smmu, value, client->smmu.reg);
value = smmu_readl(smmu, client->regs.smmu.reg);
value |= BIT(client->regs.smmu.bit);
smmu_writel(smmu, value, client->regs.smmu.reg);
}
}
@ -404,9 +404,9 @@ static void tegra_smmu_disable(struct tegra_smmu *smmu, unsigned int swgroup,
if (client->swgroup != swgroup)
continue;
value = smmu_readl(smmu, client->smmu.reg);
value &= ~BIT(client->smmu.bit);
smmu_writel(smmu, value, client->smmu.reg);
value = smmu_readl(smmu, client->regs.smmu.reg);
value &= ~BIT(client->regs.smmu.bit);
smmu_writel(smmu, value, client->regs.smmu.reg);
}
}
@ -1042,9 +1042,9 @@ static int tegra_smmu_clients_show(struct seq_file *s, void *data)
const struct tegra_mc_client *client = &smmu->soc->clients[i];
const char *status;
value = smmu_readl(smmu, client->smmu.reg);
value = smmu_readl(smmu, client->regs.smmu.reg);
if (value & BIT(client->smmu.bit))
if (value & BIT(client->regs.smmu.bit))
status = "yes";
else
status = "no";

10
drivers/memory/tegra/mc.c
View File

@ -316,13 +316,13 @@ static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc)
/* write latency allowance defaults */
for (i = 0; i < mc->soc->num_clients; i++) {
const struct tegra_mc_la *la = &mc->soc->clients[i].la;
const struct tegra_mc_client *client = &mc->soc->clients[i];
u32 value;
value = mc_readl(mc, la->reg);
value &= ~(la->mask << la->shift);
value |= (la->def & la->mask) << la->shift;
mc_writel(mc, value, la->reg);
value = mc_readl(mc, client->regs.la.reg);
value &= ~(client->regs.la.mask << client->regs.la.shift);
value |= (client->regs.la.def & client->regs.la.mask) << client->regs.la.shift;
mc_writel(mc, value, client->regs.la.reg);
}
/* latch new values */

1244
drivers/memory/tegra/tegra114.c
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File diff suppressed because it is too large Load Diff

1304
drivers/memory/tegra/tegra124.c
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File diff suppressed because it is too large Load Diff

1432
drivers/memory/tegra/tegra210.c
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File diff suppressed because it is too large Load Diff

1291
drivers/memory/tegra/tegra30.c
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File diff suppressed because it is too large Load Diff

30
include/soc/tegra/mc.h
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@ -17,25 +17,12 @@ struct clk;
struct device;
struct page;
struct tegra_smmu_enable {
unsigned int reg;
unsigned int bit;
};
struct tegra_mc_timing {
unsigned long rate;
u32 *emem_data;
};
/* latency allowance */
struct tegra_mc_la {
unsigned int reg;
unsigned int shift;
unsigned int mask;
unsigned int def;
};
struct tegra_mc_client {
unsigned int id;
const char *name;
@ -43,8 +30,21 @@ struct tegra_mc_client {
unsigned int fifo_size;
struct tegra_smmu_enable smmu;
struct tegra_mc_la la;
struct {
/* Tegra SMMU enable */
struct {
unsigned int reg;
unsigned int bit;
} smmu;
/* latency allowance */
struct {
unsigned int reg;
unsigned int shift;
unsigned int mask;
unsigned int def;
} la;
} regs;
};
struct tegra_smmu_swgroup {