mirror of https://gitee.com/openkylin/linux.git
clk: renesas: r8a77995: Correct RCLK handling
According to R-Car Gen3 Hardware Manual Rev.1.00, R-Car D3 has the RCLK Frequency Control Register (RCKCR), which determines the OSC and RINT predivider values, and selection of the RCLK clock source between RINT and the On-Chip Oscillator. Hence change the OSC and RINT clock definitions to use the RCKCR divider, and add the missing On-Chip Oscillator and RCLK clock source switching logic. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
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@ -46,6 +46,8 @@ enum clk_ids {
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CLK_S3,
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CLK_SDSRC,
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CLK_SSPSRC,
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CLK_RINT,
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CLK_OCO,
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/* Module Clocks */
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MOD_CLK_BASE
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@ -72,6 +74,10 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
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DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
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DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
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DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
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DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
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/* Core Clock Outputs */
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DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1),
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DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
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@ -90,8 +96,8 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
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DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1),
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DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1),
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DEF_FIXED("osc", R8A77995_CLK_OSC, CLK_EXTAL, 384, 1),
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DEF_FIXED("r", R8A77995_CLK_R, CLK_EXTAL, 1536, 1),
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DEF_DIV6_RO("osc", R8A77995_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
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DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2),
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DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
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@ -102,6 +108,8 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
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DEF_DIV6P1("canfd", R8A77995_CLK_CANFD, CLK_PLL0D3, 0x244),
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DEF_DIV6P1("mso", R8A77995_CLK_MSO, CLK_PLL1D2, 0x014),
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DEF_GEN3_RCKSEL("r", R8A77995_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
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};
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static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
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