mirror of https://gitee.com/openkylin/linux.git
r8169: adjust some registers.
Define new registers and modify some existing ones. Signed-off-by: Hayes Wang <hayeswang@realtek.com> Acked-by: Francois Romieu <romieu@fr.zoreil.com>
This commit is contained in:
Hayes Wang
Francois Romieu
parent
d84e0bd797
commit
4f6b00e5f1
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@ -70,8 +70,6 @@ static const int multicast_filter_limit = 32;
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#define MAC_ADDR_LEN 6
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#define MAX_READ_REQUEST_SHIFT 12
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#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
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#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
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#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
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#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
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#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
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@ -270,9 +268,20 @@ enum rtl_registers {
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TxPoll = 0x38,
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IntrMask = 0x3c,
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IntrStatus = 0x3e,
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TxConfig = 0x40,
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RxConfig = 0x44,
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TxConfig = 0x40,
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#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
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#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
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RxConfig = 0x44,
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#define RX128_INT_EN (1 << 15) /* 8111c and later */
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#define RX_MULTI_EN (1 << 14) /* 8111c only */
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#define RXCFG_FIFO_SHIFT 13
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/* No threshold before first PCI xfer */
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#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
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#define RXCFG_DMA_SHIFT 8
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/* Unlimited maximum PCI burst. */
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#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
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#define RTL_RX_CONFIG_MASK 0xff7e1880u
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RxMissed = 0x4c,
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@ -327,12 +336,13 @@ enum rtl8168_8101_registers {
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#define EPHYAR_REG_SHIFT 16
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#define EPHYAR_DATA_MASK 0xffff
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DLLPR = 0xd0,
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#define PM_SWITCH (1 << 6)
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#define PFM_EN (1 << 6)
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DBG_REG = 0xd1,
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#define FIX_NAK_1 (1 << 4)
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#define FIX_NAK_2 (1 << 3)
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TWSI = 0xd2,
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MCU = 0xd3,
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#define NOW_IS_OOB (1 << 7)
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#define EN_NDP (1 << 3)
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#define EN_OOB_RESET (1 << 2)
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EFUSEAR = 0xdc,
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@ -345,18 +355,22 @@ enum rtl8168_8101_registers {
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};
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enum rtl8168_registers {
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LED_FREQ = 0x1a,
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EEE_LED = 0x1b,
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ERIDR = 0x70,
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ERIAR = 0x74,
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#define ERIAR_FLAG 0x80000000
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#define ERIAR_WRITE_CMD 0x80000000
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#define ERIAR_READ_CMD 0x00000000
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#define ERIAR_ADDR_BYTE_ALIGN 4
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#define ERIAR_EXGMAC 0
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#define ERIAR_MSIX 1
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#define ERIAR_ASF 2
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#define ERIAR_TYPE_SHIFT 16
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#define ERIAR_BYTEEN 0x0f
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#define ERIAR_BYTEEN_SHIFT 12
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#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
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#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
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#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
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#define ERIAR_MASK_SHIFT 12
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#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
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#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
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#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
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EPHY_RXER_NUM = 0x7c,
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OCPDR = 0xb0, /* OCP GPHY access */
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#define OCPDR_WRITE_CMD 0x80000000
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@ -371,6 +385,7 @@ enum rtl8168_registers {
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RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
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MISC = 0xf0, /* 8168e only. */
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#define TXPLA_RST (1 << 29)
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#define PWM_EN (1 << 22)
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};
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enum rtl_register_content {
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@ -395,6 +410,7 @@ enum rtl_register_content {
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RxCRC = (1 << 19),
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/* ChipCmdBits */
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StopReq = 0x80,
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CmdReset = 0x10,
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CmdRxEnb = 0x08,
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CmdTxEnb = 0x04,
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@ -417,10 +433,6 @@ enum rtl_register_content {
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AcceptMyPhys = 0x02,
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AcceptAllPhys = 0x01,
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/* RxConfigBits */
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RxCfgFIFOShift = 13,
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RxCfgDMAShift = 8,
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/* TxConfigBits */
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TxInterFrameGapShift = 24,
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TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
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@ -712,8 +724,7 @@ static void rtl8169_down(struct net_device *dev);
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static void rtl8169_rx_clear(struct rtl8169_private *tp);
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static int rtl8169_poll(struct napi_struct *napi, int budget);
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static const unsigned int rtl8169_rx_config =
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(RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
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static const unsigned int rtl8169_rx_config = RX_FIFO_THRESH | RX_DMA_BURST;
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static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
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{
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@ -4368,7 +4379,7 @@ static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
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RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
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RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
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RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
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RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
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rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
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}
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