ARM: dts: zynq: DT changes for v4.19

- Add Z-turn board
 - Add mmc aliases
 - Fix model information
 - Sort out documentatio
 - Update Zybo Z7
 - Fix gpio-keys
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Merge tag 'zynq-dt-for-v4.19-v2' of https://github.com/Xilinx/linux-xlnx into next/dt

ARM: dts: zynq: DT changes for v4.19

- Add Z-turn board
- Add mmc aliases
- Fix model information
- Sort out documentatio
- Update Zybo Z7
- Fix gpio-keys

* tag 'zynq-dt-for-v4.19-v2' of https://github.com/Xilinx/linux-xlnx:
  ARM: dts: zynq: Remove #address/#size-cells from gpio-keys
  ARM: dts: zynq: Add LEDs to the Zybo Z7 board
  ARM: dts: zynq: Use gpio constants for the Zybo Z7 board
  ARM: dts: zynq: Fix memory size on the Zybo Z7 board
  dt-bindings: xilinx: zynq: Add missing boards
  dt-bindings: xilinx: zynq: Move Paralella board to Xilinx
  dt-bindings: xilinx: zynq: Sort entries alphabetically
  dt-bindings: xilinx: zynq: Improve boards description
  ARM: dts: zynq: correct and improve the model property of dt files
  ARM: dts: zynq: Set correct manufacturer for ZedBoard and MicroZed boards
  ARM: dts: zynq: Add mmc alias for zc702/zc706/zed/zybo
  ARM: dts: zynq: Add support for Z-turn board

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2018-07-21 14:27:56 -07:00
commit 4fc116f395
16 changed files with 170 additions and 30 deletions

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@ -1,7 +0,0 @@
Adapteva Platforms Device Tree Bindings
---------------------------------------
Parallella board
Required root node properties:
- compatible = "adapteva,parallella";

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@ -8,18 +8,38 @@ Required root node properties:
Additional compatible strings:
- Xilinx internal board cc108
- Adapteva Parallella board
"adapteva,parallella"
- Avnet MicroZed board
"avnet,zynq-microzed"
"xlnx,zynq-microzed"
- Avnet ZedBoard board
"avnet,zynq-zed"
"xlnx,zynq-zed"
- Digilent Zybo board
"digilent,zynq-zybo"
- Digilent Zybo Z7 board
"digilent,zynq-zybo-z7"
- Xilinx CC108 internal board
"xlnx,zynq-cc108"
- Xilinx internal board zc770 with different FMC cards
- Xilinx ZC702 internal board
"xlnx,zynq-zc702"
- Xilinx ZC706 internal board
"xlnx,zynq-zc706"
- Xilinx ZC770 internal board, with different FMC cards
"xlnx,zynq-zc770-xm010"
"xlnx,zynq-zc770-xm011"
"xlnx,zynq-zc770-xm012"
"xlnx,zynq-zc770-xm013"
- Digilent Zybo Z7 board
"digilent,zynq-zybo-z7"
---------------------------------------------------------------
Xilinx Zynq UltraScale+ MPSoC Platforms Device Tree Bindings

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@ -1115,6 +1115,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-zc770-xm012.dtb \
zynq-zc770-xm013.dtb \
zynq-zed.dtb \
zynq-zturn.dtb \
zynq-zybo.dtb \
zynq-zybo-z7.dtb
dtb-$(CONFIG_MACH_ARMADA_370) += \

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@ -12,8 +12,8 @@
/include/ "zynq-7000.dtsi"
/ {
model = "Xilinx CC108 board";
compatible = "xlnx,zynq-cc108", "xlnx,zynq-7000";
model = "Xilinx Zynq";
aliases {
ethernet0 = &gem0;

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@ -7,8 +7,8 @@
/include/ "zynq-7000.dtsi"
/ {
model = "Zynq MicroZED Development Board";
compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000";
model = "Avnet MicroZed board";
compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000";
aliases {
ethernet0 = &gem0;

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@ -12,7 +12,7 @@
/include/ "zynq-7000.dtsi"
/ {
model = "Adapteva Parallella Board";
model = "Adapteva Parallella board";
compatible = "adapteva,parallella", "xlnx,zynq-7000";
aliases {

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@ -7,13 +7,14 @@
#include "zynq-7000.dtsi"
/ {
model = "Zynq ZC702 Development Board";
model = "Xilinx ZC702 board";
compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
aliases {
ethernet0 = &gem0;
i2c0 = &i2c0;
serial0 = &uart1;
mmc0 = &sdhci0;
};
memory@0 {
@ -28,8 +29,6 @@ chosen {
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
sw14 {
label = "sw14";

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@ -7,13 +7,14 @@
#include "zynq-7000.dtsi"
/ {
model = "Zynq ZC706 Development Board";
model = "Xilinx ZC706 board";
compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
aliases {
ethernet0 = &gem0;
i2c0 = &i2c0;
serial0 = &uart1;
mmc0 = &sdhci0;
};
memory@0 {

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@ -8,8 +8,8 @@
#include "zynq-7000.dtsi"
/ {
model = "Xilinx ZC770 XM010 board";
compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000";
model = "Xilinx Zynq";
aliases {
ethernet0 = &gem0;

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@ -8,8 +8,8 @@
#include "zynq-7000.dtsi"
/ {
model = "Xilinx ZC770 XM011 board";
compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000";
model = "Xilinx Zynq";
aliases {
i2c0 = &i2c1;

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@ -8,8 +8,8 @@
#include "zynq-7000.dtsi"
/ {
model = "Xilinx ZC770 XM012 board";
compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000";
model = "Xilinx Zynq";
aliases {
i2c0 = &i2c0;

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@ -8,8 +8,8 @@
#include "zynq-7000.dtsi"
/ {
model = "Xilinx ZC770 XM013 board";
compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000";
model = "Xilinx Zynq";
aliases {
ethernet0 = &gem1;

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@ -7,12 +7,13 @@
#include "zynq-7000.dtsi"
/ {
model = "Zynq Zed Development Board";
compatible = "xlnx,zynq-zed", "xlnx,zynq-7000";
model = "Avnet ZedBoard board";
compatible = "avnet,zynq-zed", "xlnx,zynq-zed", "xlnx,zynq-7000";
aliases {
ethernet0 = &gem0;
serial0 = &uart1;
mmc0 = &sdhci0;
};
memory@0 {

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@ -0,0 +1,114 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2015 Andrea Merello <adnrea.merello@gmail.com>
* Copyright (C) 2017 Alexander Graf <agraf@suse.de>
*
* Based on zynq-zed.dts which is:
* Copyright (C) 2011 - 2014 Xilinx
* Copyright (C) 2012 National Instruments Corp.
*
*/
/dts-v1/;
/include/ "zynq-7000.dtsi"
/ {
model = "Zynq Z-Turn MYIR Board";
compatible = "myir,zynq-zturn", "xlnx,zynq-7000";
aliases {
ethernet0 = &gem0;
serial0 = &uart1;
serial1 = &uart0;
mmc0 = &sdhci0;
};
memory@0 {
device_type = "memory";
reg = <0x0 0x40000000>;
};
chosen {
stdout-path = "serial0:115200n8";
};
gpio-leds {
compatible = "gpio-leds";
usr-led1 {
label = "usr-led1";
gpios = <&gpio0 0x0 0x1>;
default-state = "off";
};
usr-led2 {
label = "usr-led2";
gpios = <&gpio0 0x9 0x1>;
default-state = "off";
};
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
K1 {
label = "K1";
gpios = <&gpio0 0x32 0x1>;
linux,code = <0x66>;
gpio-key,wakeup;
autorepeat;
};
};
};
&clkc {
ps-clk-frequency = <33333333>;
};
&gem0 {
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&ethernet_phy>;
ethernet_phy: ethernet-phy@0 {
reg = <0x0>;
};
};
&sdhci0 {
status = "okay";
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";
};
&can0 {
status = "okay";
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;
stlm75@49 {
status = "okay";
compatible = "lm75";
reg = <0x49>;
};
accelerometer@53 {
compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x";
reg = <0x53>;
interrupt-parent = <&intc>;
interrupts = <0x0 0x1e 0x4>;
};
};

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@ -1,9 +1,10 @@
// SPDX-License-Identifier: GPL-2.0+
/dts-v1/;
#include "zynq-7000.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Zynq ZYBO Z7 Development Board";
model = "Digilent Zybo Z7 board";
compatible = "digilent,zynq-zybo-z7", "xlnx,zynq-7000";
aliases {
@ -13,7 +14,7 @@ aliases {
memory@0 {
device_type = "memory";
reg = <0x0 0x20000000>;
reg = <0x0 0x40000000>;
};
chosen {
@ -21,10 +22,19 @@ chosen {
stdout-path = "serial0:115200n8";
};
gpio-leds {
compatible = "gpio-leds";
ld4 {
label = "zynq-zybo-z7:green:ld4";
gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
};
};
usb_phy0: phy0 {
#phy-cells = <0>;
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio0 46 1>;
reset-gpios = <&gpio0 46 GPIO_ACTIVE_LOW>;
};
};

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@ -7,12 +7,13 @@
#include "zynq-7000.dtsi"
/ {
model = "Zynq ZYBO Development Board";
model = "Digilent Zybo board";
compatible = "digilent,zynq-zybo", "xlnx,zynq-7000";
aliases {
ethernet0 = &gem0;
serial0 = &uart1;
mmc0 = &sdhci0;
};
memory@0 {