mirror of https://gitee.com/openkylin/linux.git
Merge commit 'gcl/gcl-next'
This commit is contained in:
commit
5006d1aae8
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@ -90,7 +90,7 @@ mpc5200_setup_xlb_arbiter(void)
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of_node_put(np);
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of_node_put(np);
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if (!xlb) {
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if (!xlb) {
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printk(KERN_ERR __FILE__ ": "
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printk(KERN_ERR __FILE__ ": "
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"Error mapping XLB in mpc52xx_setup_cpu(). "
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"Error mapping XLB in mpc52xx_setup_cpu(). "
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"Expect some abnormal behavior\n");
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"Expect some abnormal behavior\n");
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return;
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return;
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}
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}
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@ -216,7 +216,8 @@ mpc52xx_restart(char *cmd)
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out_be32(&mpc52xx_wdt->count, 0x000000ff);
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out_be32(&mpc52xx_wdt->count, 0x000000ff);
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out_be32(&mpc52xx_wdt->mode, 0x00009004);
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out_be32(&mpc52xx_wdt->mode, 0x00009004);
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} else
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} else
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printk("mpc52xx_restart: Can't access wdt. "
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printk(KERN_ERR __FILE__ ": "
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"mpc52xx_restart: Can't access wdt. "
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"Restart impossible, system halted.\n");
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"Restart impossible, system halted.\n");
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while (1);
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while (1);
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@ -265,8 +265,11 @@ mpc52xx_pci_setup(struct pci_controller *hose,
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/* Memory windows */
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/* Memory windows */
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res = &hose->mem_resources[0];
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res = &hose->mem_resources[0];
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if (res->flags) {
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if (res->flags) {
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pr_debug("mem_resource[0] = {.start=%x, .end=%x, .flags=%lx}\n",
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pr_debug("mem_resource[0] = "
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res->start, res->end, res->flags);
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"{.start=%llx, .end=%llx, .flags=%llx}\n",
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(unsigned long long)res->start,
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(unsigned long long)res->end,
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(unsigned long long)res->flags);
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out_be32(&pci_regs->iw0btar,
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out_be32(&pci_regs->iw0btar,
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MPC52xx_PCI_IWBTAR_TRANSLATION(res->start, res->start,
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MPC52xx_PCI_IWBTAR_TRANSLATION(res->start, res->start,
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res->end - res->start + 1));
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res->end - res->start + 1));
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@ -297,9 +300,11 @@ mpc52xx_pci_setup(struct pci_controller *hose,
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printk(KERN_ERR "%s: Didn't find IO resources\n", __FILE__);
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printk(KERN_ERR "%s: Didn't find IO resources\n", __FILE__);
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return;
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return;
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}
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}
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pr_debug(".io_resource={.start=%x,.end=%x,.flags=%lx} "
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pr_debug(".io_resource={.start=%llx,.end=%llx,.flags=%llx} "
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".io_base_phys=0x%p\n",
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".io_base_phys=0x%p\n",
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res->start, res->end, res->flags, (void*)hose->io_base_phys);
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(unsigned long long)res->start,
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(unsigned long long)res->end,
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(unsigned long long)res->flags, (void*)hose->io_base_phys);
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out_be32(&pci_regs->iw2btar,
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out_be32(&pci_regs->iw2btar,
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MPC52xx_PCI_IWBTAR_TRANSLATION(hose->io_base_phys,
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MPC52xx_PCI_IWBTAR_TRANSLATION(hose->io_base_phys,
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res->start,
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res->start,
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@ -312,7 +312,6 @@ static struct i2c_adapter mpc_ops = {
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.name = "MPC adapter",
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.name = "MPC adapter",
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.id = I2C_HW_MPC107,
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.id = I2C_HW_MPC107,
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.algo = &mpc_algo,
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.algo = &mpc_algo,
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.class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
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.timeout = 1,
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.timeout = 1,
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};
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};
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@ -410,7 +410,7 @@ struct of_modalias_table {
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char *modalias;
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char *modalias;
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};
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};
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static struct of_modalias_table of_modalias_table[] = {
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static struct of_modalias_table of_modalias_table[] = {
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/* Empty for now; add entries as needed */
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{ "fsl,mcu-mpc8349emitx", "mcu-mpc8349emitx" },
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};
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};
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/**
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/**
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@ -108,13 +108,13 @@ static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi)
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* Because psc->ccr is defined as 16bit register instead of 32bit
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* Because psc->ccr is defined as 16bit register instead of 32bit
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* just set the lower byte of BitClkDiv
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* just set the lower byte of BitClkDiv
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*/
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*/
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ccr = in_be16(&psc->ccr);
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ccr = in_be16((u16 __iomem *)&psc->ccr);
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ccr &= 0xFF00;
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ccr &= 0xFF00;
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if (cs->speed_hz)
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if (cs->speed_hz)
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ccr |= (MCLK / cs->speed_hz - 1) & 0xFF;
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ccr |= (MCLK / cs->speed_hz - 1) & 0xFF;
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else /* by default SPI Clk 1MHz */
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else /* by default SPI Clk 1MHz */
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ccr |= (MCLK / 1000000 - 1) & 0xFF;
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ccr |= (MCLK / 1000000 - 1) & 0xFF;
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out_be16(&psc->ccr, ccr);
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out_be16((u16 __iomem *)&psc->ccr, ccr);
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mps->bits_per_word = cs->bits_per_word;
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mps->bits_per_word = cs->bits_per_word;
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if (mps->activate_cs)
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if (mps->activate_cs)
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@ -347,7 +347,7 @@ static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps)
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/* Configure 8bit codec mode as a SPI master and use EOF flags */
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/* Configure 8bit codec mode as a SPI master and use EOF flags */
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/* SICR_SIM_CODEC8|SICR_GENCLK|SICR_SPI|SICR_MSTR|SICR_USEEOF */
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/* SICR_SIM_CODEC8|SICR_GENCLK|SICR_SPI|SICR_MSTR|SICR_USEEOF */
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out_be32(&psc->sicr, 0x0180C800);
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out_be32(&psc->sicr, 0x0180C800);
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out_be16(&psc->ccr, 0x070F); /* by default SPI Clk 1MHz */
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out_be16((u16 __iomem *)&psc->ccr, 0x070F); /* default SPI Clk 1MHz */
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/* Set 2ms DTL delay */
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/* Set 2ms DTL delay */
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out_8(&psc->ctur, 0x00);
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out_8(&psc->ctur, 0x00);
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