mirror of https://gitee.com/openkylin/linux.git
clk-divider: make sure read-only dividers do not write to their register
Commite6d5e7d90b
("clk-divider: Fix READ_ONLY when divider > 1") removed the special ops struct for read-only clocks and instead opted to handle them inside the regular ops. On the rk3368 this results in breakage as aclkm now gets set a value. While it is the same divider value, the A53 core still doesn't like it, which can result in the cpu ending up in a hang. The reason being that "ACLKENMasserts one clock cycle before the rising edge of ACLKM" and the clock should only be touched when STANDBYWFIL2 is asserted. To fix this, reintroduce the read-only ops but do include the round_rate callback. That way no writes that may be unsafe are done to the divider register in any case. The Rockchip use of the clk_divider_ops is adapted to this split again, as is the nxp, lpc18xx-ccu driver that was included since the original commit. On lpc18xx-ccu the divider seems to always be read-only so only uses the new ops now. Fixes:e6d5e7d90b
("clk-divider: Fix READ_ONLY when divider > 1") Reported-by: Zhang Qing <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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@ -423,6 +423,12 @@ const struct clk_ops clk_divider_ops = {
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};
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EXPORT_SYMBOL_GPL(clk_divider_ops);
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const struct clk_ops clk_divider_ro_ops = {
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.recalc_rate = clk_divider_recalc_rate,
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.round_rate = clk_divider_round_rate,
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};
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EXPORT_SYMBOL_GPL(clk_divider_ro_ops);
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static struct clk *_register_divider(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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@ -446,7 +452,10 @@ static struct clk *_register_divider(struct device *dev, const char *name,
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &clk_divider_ops;
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if (clk_divider_flags & CLK_DIVIDER_READ_ONLY)
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init.ops = &clk_divider_ro_ops;
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else
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init.ops = &clk_divider_ops;
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init.flags = flags | CLK_IS_BASIC;
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init.parent_names = (parent_name ? &parent_name: NULL);
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init.num_parents = (parent_name ? 1 : 0);
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@ -222,7 +222,7 @@ static void lpc18xx_ccu_register_branch_gate_div(struct lpc18xx_clk_branch *bran
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div->width = 1;
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div_hw = &div->hw;
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div_ops = &clk_divider_ops;
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div_ops = &clk_divider_ro_ops;
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}
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branch->gate.reg = branch->offset + reg_base;
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@ -90,7 +90,9 @@ static struct clk *rockchip_clk_register_branch(const char *name,
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div->width = div_width;
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div->lock = lock;
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div->table = div_table;
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div_ops = &clk_divider_ops;
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div_ops = (div_flags & CLK_DIVIDER_READ_ONLY)
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? &clk_divider_ro_ops
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: &clk_divider_ops;
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}
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clk = clk_register_composite(NULL, name, parent_names, num_parents,
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@ -385,6 +385,7 @@ struct clk_divider {
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#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
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extern const struct clk_ops clk_divider_ops;
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extern const struct clk_ops clk_divider_ro_ops;
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unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
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unsigned int val, const struct clk_div_table *table,
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