mirror of https://gitee.com/openkylin/linux.git
ALSA: firewire-motu: refactoring protocol v2 for fetching mode switch
This commit splits the method to switch fetching mode for protocol version 2 so that model-dependent operations are explicitly defined. Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp> Link: https://lore.kernel.org/r/20200519111641.123211-15-o-takashi@sakamocchi.jp Signed-off-by: Takashi Iwai <tiwai@suse.de>
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@ -170,52 +170,69 @@ int snd_motu_protocol_v2_get_clock_source(struct snd_motu *motu,
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return get_clock_source(motu, be32_to_cpu(reg), src);
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}
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// Expected for Traveler and 896HD, which implements Altera Cyclone EP1C3.
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static int switch_fetching_mode_cyclone(struct snd_motu *motu, u32 *data,
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bool enable)
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{
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*data |= V2_CLOCK_MODEL_SPECIFIC;
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return 0;
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}
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// For UltraLite and 8pre, which implements Xilinx Spartan XC3S200.
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static int switch_fetching_mode_spartan(struct snd_motu *motu, u32 *data,
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bool enable)
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{
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unsigned int rate;
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enum snd_motu_clock_source src;
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int err;
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err = get_clock_source(motu, *data, &src);
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if (err < 0)
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return err;
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err = get_clock_rate(*data, &rate);
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if (err < 0)
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return err;
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if (src == SND_MOTU_CLOCK_SOURCE_SPH && rate > 48000)
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*data |= V2_CLOCK_MODEL_SPECIFIC;
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return 0;
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}
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int snd_motu_protocol_v2_switch_fetching_mode(struct snd_motu *motu,
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bool enable)
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{
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enum snd_motu_clock_source src;
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__be32 reg;
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u32 data;
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int err = 0;
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// 828mkII implements Altera ACEX 1K EP1K30. Nothing to do.
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if (motu->spec == &snd_motu_spec_828mk2)
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if (motu->spec == &snd_motu_spec_828mk2) {
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// 828mkII implements Altera ACEX 1K EP1K30. Nothing to do.
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return 0;
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err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, ®,
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sizeof(reg));
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if (err < 0)
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return err;
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data = be32_to_cpu(reg);
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err = get_clock_source(motu, data, &src);
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if (err < 0)
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return err;
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data &= ~(V2_CLOCK_FETCH_ENABLE | V2_CLOCK_MODEL_SPECIFIC);
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if (enable)
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data |= V2_CLOCK_FETCH_ENABLE;
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if (motu->spec == &snd_motu_spec_traveler) {
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// Expected for Traveler and 896HD, which implements Altera
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// Cyclone EP1C3.
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data |= V2_CLOCK_MODEL_SPECIFIC;
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} else {
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// For UltraLite and 8pre, which implements Xilinx Spartan
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// XC3S200.
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unsigned int rate;
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__be32 reg;
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u32 data;
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int err;
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err = get_clock_rate(data, &rate);
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err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET,
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®, sizeof(reg));
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if (err < 0)
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return err;
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data = be32_to_cpu(reg);
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data &= ~(V2_CLOCK_FETCH_ENABLE | V2_CLOCK_MODEL_SPECIFIC);
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if (enable)
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data |= V2_CLOCK_FETCH_ENABLE;
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if (motu->spec == &snd_motu_spec_traveler)
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err = switch_fetching_mode_cyclone(motu, &data, enable);
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else
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err = switch_fetching_mode_spartan(motu, &data, enable);
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if (err < 0)
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return err;
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if (src == SND_MOTU_CLOCK_SOURCE_SPH && rate > 48000)
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data |= V2_CLOCK_MODEL_SPECIFIC;
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reg = cpu_to_be32(data);
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return snd_motu_transaction_write(motu, V2_CLOCK_STATUS_OFFSET,
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®, sizeof(reg));
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}
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reg = cpu_to_be32(data);
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return snd_motu_transaction_write(motu, V2_CLOCK_STATUS_OFFSET, ®,
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sizeof(reg));
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}
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static int detect_packet_formats_828mk2(struct snd_motu *motu, u32 data)
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