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x86: bitops take an unsigned long * 

All (or most) other architectures do this.  So should x86.  Fix.

Cc: Andrea Arcangeli <andrea@qumranet.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Andrew Morton 2008-05-14 16:10:41 -07:00 committed by Thomas Gleixner
parent 75d3bce2fc
commit 5136dea573
1 changed files with 17 additions and 17 deletions
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34
include/asm-x86/bitops.h
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@ -43,7 +43,7 @@
* Note that @nr may be almost arbitrarily large; this function is not * Note that @nr may be almost arbitrarily large; this function is not
* restricted to acting on a single-word quantity. * restricted to acting on a single-word quantity.
*/ */
static inline void set_bit(int nr, volatile void *addr) static inline void set_bit(int nr, volatile unsigned long *addr)
{ {
asm volatile(LOCK_PREFIX "bts %1,%0" : ADDR : "Ir" (nr) : "memory"); asm volatile(LOCK_PREFIX "bts %1,%0" : ADDR : "Ir" (nr) : "memory");
} }
@ -57,7 +57,7 @@ static inline void set_bit(int nr, volatile void *addr)
* If it's called on the same region of memory simultaneously, the effect * If it's called on the same region of memory simultaneously, the effect
* may be that only one operation succeeds. * may be that only one operation succeeds.
*/ */
static inline void __set_bit(int nr, volatile void *addr) static inline void __set_bit(int nr, volatile unsigned long *addr)
{ {
asm volatile("bts %1,%0" : ADDR : "Ir" (nr) : "memory"); asm volatile("bts %1,%0" : ADDR : "Ir" (nr) : "memory");
} }
@ -72,7 +72,7 @@ static inline void __set_bit(int nr, volatile void *addr)
* you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
* in order to ensure changes are visible on other processors. * in order to ensure changes are visible on other processors.
*/ */
static inline void clear_bit(int nr, volatile void *addr) static inline void clear_bit(int nr, volatile unsigned long *addr)
{ {
asm volatile(LOCK_PREFIX "btr %1,%0" : ADDR : "Ir" (nr)); asm volatile(LOCK_PREFIX "btr %1,%0" : ADDR : "Ir" (nr));
} }
@ -85,13 +85,13 @@ static inline void clear_bit(int nr, volatile void *addr)
* clear_bit() is atomic and implies release semantics before the memory * clear_bit() is atomic and implies release semantics before the memory
* operation. It can be used for an unlock. * operation. It can be used for an unlock.
*/ */
static inline void clear_bit_unlock(unsigned nr, volatile void *addr) static inline void clear_bit_unlock(unsigned nr, volatile unsigned long *addr)
{ {
barrier(); barrier();
clear_bit(nr, addr); clear_bit(nr, addr);
} }
static inline void __clear_bit(int nr, volatile void *addr) static inline void __clear_bit(int nr, volatile unsigned long *addr)
{ {
asm volatile("btr %1,%0" : ADDR : "Ir" (nr)); asm volatile("btr %1,%0" : ADDR : "Ir" (nr));
} }
@ -108,7 +108,7 @@ static inline void __clear_bit(int nr, volatile void *addr)
* No memory barrier is required here, because x86 cannot reorder stores past * No memory barrier is required here, because x86 cannot reorder stores past
* older loads. Same principle as spin_unlock. * older loads. Same principle as spin_unlock.
*/ */
static inline void __clear_bit_unlock(unsigned nr, volatile void *addr) static inline void __clear_bit_unlock(unsigned nr, volatile unsigned long *addr)
{ {
barrier(); barrier();
__clear_bit(nr, addr); __clear_bit(nr, addr);
@ -126,7 +126,7 @@ static inline void __clear_bit_unlock(unsigned nr, volatile void *addr)
* If it's called on the same region of memory simultaneously, the effect * If it's called on the same region of memory simultaneously, the effect
* may be that only one operation succeeds. * may be that only one operation succeeds.
*/ */
static inline void __change_bit(int nr, volatile void *addr) static inline void __change_bit(int nr, volatile unsigned long *addr)
{ {
asm volatile("btc %1,%0" : ADDR : "Ir" (nr)); asm volatile("btc %1,%0" : ADDR : "Ir" (nr));
} }
@ -140,7 +140,7 @@ static inline void __change_bit(int nr, volatile void *addr)
* Note that @nr may be almost arbitrarily large; this function is not * Note that @nr may be almost arbitrarily large; this function is not
* restricted to acting on a single-word quantity. * restricted to acting on a single-word quantity.
*/ */
static inline void change_bit(int nr, volatile void *addr) static inline void change_bit(int nr, volatile unsigned long *addr)
{ {
asm volatile(LOCK_PREFIX "btc %1,%0" : ADDR : "Ir" (nr)); asm volatile(LOCK_PREFIX "btc %1,%0" : ADDR : "Ir" (nr));
} }
@ -153,7 +153,7 @@ static inline void change_bit(int nr, volatile void *addr)
* This operation is atomic and cannot be reordered. * This operation is atomic and cannot be reordered.
* It also implies a memory barrier. * It also implies a memory barrier.
*/ */
static inline int test_and_set_bit(int nr, volatile void *addr) static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
{ {
int oldbit; int oldbit;
@ -170,7 +170,7 @@ static inline int test_and_set_bit(int nr, volatile void *addr)
* *
* This is the same as test_and_set_bit on x86. * This is the same as test_and_set_bit on x86.
*/ */
static inline int test_and_set_bit_lock(int nr, volatile void *addr) static inline int test_and_set_bit_lock(int nr, volatile unsigned long *addr)
{ {
return test_and_set_bit(nr, addr); return test_and_set_bit(nr, addr);
} }
@ -184,7 +184,7 @@ static inline int test_and_set_bit_lock(int nr, volatile void *addr)
* If two examples of this operation race, one can appear to succeed * If two examples of this operation race, one can appear to succeed
* but actually fail. You must protect multiple accesses with a lock. * but actually fail. You must protect multiple accesses with a lock.
*/ */
static inline int __test_and_set_bit(int nr, volatile void *addr) static inline int __test_and_set_bit(int nr, volatile unsigned long *addr)
{ {
int oldbit; int oldbit;
@ -203,7 +203,7 @@ static inline int __test_and_set_bit(int nr, volatile void *addr)
* This operation is atomic and cannot be reordered. * This operation is atomic and cannot be reordered.
* It also implies a memory barrier. * It also implies a memory barrier.
*/ */
static inline int test_and_clear_bit(int nr, volatile void *addr) static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
{ {
int oldbit; int oldbit;
@ -223,7 +223,7 @@ static inline int test_and_clear_bit(int nr, volatile void *addr)
* If two examples of this operation race, one can appear to succeed * If two examples of this operation race, one can appear to succeed
* but actually fail. You must protect multiple accesses with a lock. * but actually fail. You must protect multiple accesses with a lock.
*/ */
static inline int __test_and_clear_bit(int nr, volatile void *addr) static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr)
{ {
int oldbit; int oldbit;
@ -235,7 +235,7 @@ static inline int __test_and_clear_bit(int nr, volatile void *addr)
} }
/* WARNING: non atomic and it can be reordered! */ /* WARNING: non atomic and it can be reordered! */
static inline int __test_and_change_bit(int nr, volatile void *addr) static inline int __test_and_change_bit(int nr, volatile unsigned long *addr)
{ {
int oldbit; int oldbit;
@ -255,7 +255,7 @@ static inline int __test_and_change_bit(int nr, volatile void *addr)
* This operation is atomic and cannot be reordered. * This operation is atomic and cannot be reordered.
* It also implies a memory barrier. * It also implies a memory barrier.
*/ */
static inline int test_and_change_bit(int nr, volatile void *addr) static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
{ {
int oldbit; int oldbit;
@ -266,13 +266,13 @@ static inline int test_and_change_bit(int nr, volatile void *addr)
return oldbit; return oldbit;
} }
static inline int constant_test_bit(int nr, const volatile void *addr) static inline int constant_test_bit(int nr, const volatile unsigned long *addr)
{ {
return ((1UL << (nr % BITS_PER_LONG)) & return ((1UL << (nr % BITS_PER_LONG)) &
(((unsigned long *)addr)[nr / BITS_PER_LONG])) != 0; (((unsigned long *)addr)[nr / BITS_PER_LONG])) != 0;
} }
static inline int variable_test_bit(int nr, volatile const void *addr) static inline int variable_test_bit(int nr, volatile const unsigned long *addr)
{ {
int oldbit; int oldbit;