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Merge branch 'next/devel-samsung-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into late/soc 

* 'next/devel-samsung-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  ARM: EXYNOS: Support suspend and resume for EXYNOS5250
  ARM: EXYNOS: Add Clock register list for save and restore
  ARM: EXYNOS: Add PMU table for EXYNOS5250
  ARM: EXYNOS: Rename of function for pm.c
  ARM: EXYNOS: Remove GIC save & restore function
  ARM: dts: Add node for interrupt combiner controller on EXYNOS5250
  ARM: S3C24XX: add support for second irq set of S3C2416
  + dependent branches
This commit is contained in:
Olof Johansson 2012-05-19 15:46:29 -07:00
parent 36be50515f 60e49ca654
commit 516fb7a22a
73 changed files with 3095 additions and 1357 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

52
Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt Normal file
View File

@ -0,0 +1,52 @@
* Samsung Exynos Interrupt Combiner Controller
Samsung's Exynos4 architecture includes a interrupt combiner controller which
can combine interrupt sources as a group and provide a single interrupt request
for the group. The interrupt request from each group are connected to a parent
interrupt controller, such as GIC in case of Exynos4210.
The interrupt combiner controller consists of multiple combiners. Upto eight
interrupt sources can be connected to a combiner. The combiner outputs one
combined interrupt for its eight interrupt sources. The combined interrupt
is usually connected to a parent interrupt controller.
A single node in the device tree is used to describe the interrupt combiner
controller module (which includes multiple combiners). A combiner in the
interrupt controller module shares config/control registers with other
combiners. For example, a 32-bit interrupt enable/disable config register
can accommodate upto 4 interrupt combiners (with each combiner supporting
upto 8 interrupt sources).
Required properties:
- compatible: should be "samsung,exynos4210-combiner".
- interrupt-controller: Identifies the node as an interrupt controller.
- #interrupt-cells: should be <2>. The meaning of the cells are
* First Cell: Combiner Group Number.
* Second Cell: Interrupt number within the group.
- reg: Base address and size of interrupt combiner registers.
- interrupts: The list of interrupts generated by the combiners which are then
connected to a parent interrupt controller. The format of the interrupt
specifier depends in the interrupt parent controller.
Optional properties:
- samsung,combiner-nr: The number of interrupt combiners supported. If this
property is not specified, the default number of combiners is assumed
to be 16.
- interrupt-parent: pHandle of the parent interrupt controller, if not
inherited from the parent node.
Example:
The following is a an example from the Exynos4210 SoC dtsi file.
combiner:interrupt-controller@10440000 {
compatible = "samsung,exynos4210-combiner";
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x10440000 0x1000>;
interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
};

1
arch/arm/Kconfig
View File

@ -1088,7 +1088,6 @@ source "arch/arm/mach-sa1100/Kconfig"
source "arch/arm/plat-samsung/Kconfig"
source "arch/arm/plat-s3c24xx/Kconfig"
source "arch/arm/plat-s5p/Kconfig"
source "arch/arm/plat-spear/Kconfig"

2
arch/arm/Makefile
View File

@ -209,7 +209,7 @@ plat-$(CONFIG_PLAT_NOMADIK) := nomadik
plat-$(CONFIG_PLAT_ORION) := orion
plat-$(CONFIG_PLAT_PXA) := pxa
plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx samsung
plat-$(CONFIG_PLAT_S5P) := s5p samsung
plat-$(CONFIG_PLAT_S5P) := samsung
plat-$(CONFIG_PLAT_SPEAR) := spear
plat-$(CONFIG_PLAT_VERSATILE) := versatile

48
arch/arm/boot/dts/exynos5250-smdk5250.dts
View File

@ -23,4 +23,52 @@ memory {
chosen {
bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
};
i2c@12C60000 {
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <20000>;
gpios = <&gpb3 0 2 3 0>,
<&gpb3 1 2 3 0>;
eeprom@50 {
compatible = "samsung,s524ad0xd1";
reg = <0x50>;
};
};
i2c@12C70000 {
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <20000>;
gpios = <&gpb3 2 2 3 0>,
<&gpb3 3 2 3 0>;
eeprom@51 {
compatible = "samsung,s524ad0xd1";
reg = <0x51>;
};
};
i2c@12C80000 {
status = "disabled";
};
i2c@12C90000 {
status = "disabled";
};
i2c@12CA0000 {
status = "disabled";
};
i2c@12CB0000 {
status = "disabled";
};
i2c@12CC0000 {
status = "disabled";
};
i2c@12CD0000 {
status = "disabled";
};
};

76
arch/arm/boot/dts/exynos5250.dtsi
View File

@ -23,11 +23,27 @@ / {
compatible = "samsung,exynos5250";
interrupt-parent = <&gic>;
gic:interrupt-controller@10490000 {
gic:interrupt-controller@10481000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x10490000 0x1000>, <0x10480000 0x100>;
reg = <0x10481000 0x1000>, <0x10482000 0x2000>;
};
combiner:interrupt-controller@10440000 {
compatible = "samsung,exynos4210-combiner";
#interrupt-cells = <2>;
interrupt-controller;
samsung,combiner-nr = <32>;
reg = <0x10440000 0x1000>;
interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
<0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
<0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
};
watchdog {
@ -42,30 +58,6 @@ rtc {
interrupts = <0 43 0>, <0 44 0>;
};
sdhci@12200000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12200000 0x100>;
interrupts = <0 75 0>;
};
sdhci@12210000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12210000 0x100>;
interrupts = <0 76 0>;
};
sdhci@12220000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12220000 0x100>;
interrupts = <0 77 0>;
};
sdhci@12230000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12230000 0x100>;
interrupts = <0 78 0>;
};
serial@12C00000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C00000 0x100>;
@ -94,48 +86,64 @@ i2c@12C60000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C60000 0x100>;
interrupts = <0 56 0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@12C70000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C70000 0x100>;
interrupts = <0 57 0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@12C80000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C80000 0x100>;
interrupts = <0 58 0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@12C90000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C90000 0x100>;
interrupts = <0 59 0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@12CA0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CA0000 0x100>;
interrupts = <0 60 0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@12CB0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CB0000 0x100>;
interrupts = <0 61 0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@12CC0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CC0000 0x100>;
interrupts = <0 62 0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@12CD0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CD0000 0x100>;
interrupts = <0 63 0>;
#address-cells = <1>;
#size-cells = <0>;
};
amba {
@ -157,13 +165,13 @@ pdma1: pdma@121B0000 {
interrupts = <0 35 0>;
};
mdma0: pdma@10800000 {
mdma0: mdma@10800000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x10800000 0x1000>;
interrupts = <0 33 0>;
};
mdma1: pdma@11C10000 {
mdma1: mdma@11C10000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x11C10000 0x1000>;
interrupts = <0 124 0>;
@ -242,6 +250,12 @@ gpc3: gpio-controller@11400140 {
#gpio-cells = <4>;
};
gpc4: gpio-controller@114002E0 {
compatible = "samsung,exynos4-gpio";
reg = <0x114002E0 0x20>;
#gpio-cells = <4>;
};
gpd0: gpio-controller@11400160 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400160 0x20>;
@ -388,19 +402,19 @@ gpv1: gpio-controller@10D10020 {
gpv2: gpio-controller@10D10040 {
compatible = "samsung,exynos4-gpio";
reg = <0x10D10040 0x20>;
reg = <0x10D10060 0x20>;
#gpio-cells = <4>;
};
gpv3: gpio-controller@10D10060 {
compatible = "samsung,exynos4-gpio";
reg = <0x10D10060 0x20>;
reg = <0x10D10080 0x20>;
#gpio-cells = <4>;
};
gpv4: gpio-controller@10D10080 {
compatible = "samsung,exynos4-gpio";
reg = <0x10D10080 0x20>;
reg = <0x10D100C0 0x20>;
#gpio-cells = <4>;
};

26
arch/arm/mach-exynos/Kconfig
View File

@ -61,6 +61,9 @@ config SOC_EXYNOS5250
bool "SAMSUNG EXYNOS5250"
default y
depends on ARCH_EXYNOS5
select SAMSUNG_DMADEV
select S5P_PM if PM
select S5P_SLEEP if PM
help
Enable EXYNOS5250 SoC support
@ -70,7 +73,7 @@ config EXYNOS4_MCT
help
Use MCT (Multi Core Timer) as kernel timers
config EXYNOS4_DEV_DMA
config EXYNOS_DEV_DMA
bool
help
Compile in amba device definitions for DMA controller
@ -80,15 +83,20 @@ config EXYNOS4_DEV_AHCI
help
Compile in platform device definitions for AHCI
config EXYNOS_DEV_DRM
bool
help
Compile in platform device definitions for core DRM device
config EXYNOS4_SETUP_FIMD0
bool
help
Common setup code for FIMD0.
config EXYNOS4_DEV_SYSMMU
config EXYNOS_DEV_SYSMMU
bool
help
Common setup code for SYSTEM MMU in EXYNOS4
Common setup code for SYSTEM MMU in EXYNOS platforms
config EXYNOS4_DEV_DWMCI
bool
@ -161,7 +169,7 @@ config EXYNOS4_SETUP_USB_PHY
help
Common setup code for USB PHY controller
config EXYNOS4_SETUP_SPI
config EXYNOS_SETUP_SPI
bool
help
Common setup code for SPI GPIO configurations.
@ -200,12 +208,12 @@ config MACH_SMDKV310
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
select SAMSUNG_DEV_BACKLIGHT
select EXYNOS_DEV_SYSMMU
select EXYNOS4_DEV_AHCI
select SAMSUNG_DEV_KEYPAD
select EXYNOS4_DEV_DMA
select SAMSUNG_DEV_PWM
select EXYNOS4_DEV_USB_OHCI
select EXYNOS4_DEV_SYSMMU
select EXYNOS4_SETUP_FIMD0
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_KEYPAD
@ -223,8 +231,7 @@ config MACH_ARMLEX4210
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
select EXYNOS4_DEV_AHCI
select EXYNOS4_DEV_DMA
select EXYNOS4_DEV_SYSMMU
select EXYNOS_DEV_DMA
select EXYNOS4_SETUP_SDHCI
help
Machine support for Samsung ARMLEX4210 based on EXYNOS4210
@ -254,6 +261,7 @@ config MACH_UNIVERSAL_C210
select S5P_DEV_MFC
select S5P_DEV_ONENAND
select S5P_DEV_TV
select EXYNOS_DEV_SYSMMU
select EXYNOS4_DEV_DMA
select EXYNOS4_SETUP_FIMD0
select EXYNOS4_SETUP_I2C1
@ -325,6 +333,7 @@ config MACH_ORIGEN
select S5P_DEV_USB_EHCI
select SAMSUNG_DEV_BACKLIGHT
select SAMSUNG_DEV_PWM
select EXYNOS_DEV_SYSMMU
select EXYNOS4_DEV_DMA
select EXYNOS4_DEV_USB_OHCI
select EXYNOS4_SETUP_FIMD0
@ -348,7 +357,8 @@ config MACH_SMDK4212
select SAMSUNG_DEV_BACKLIGHT
select SAMSUNG_DEV_KEYPAD
select SAMSUNG_DEV_PWM
select EXYNOS4_DEV_DMA
select EXYNOS_DEV_SYSMMU
select EXYNOS_DEV_DMA
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_I2C3
select EXYNOS4_SETUP_I2C7

9
arch/arm/mach-exynos/Makefile
View File

@ -22,7 +22,7 @@ obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_ARCH_EXYNOS4) += pmu.o
obj-$(CONFIG_ARCH_EXYNOS) += pmu.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
@ -50,10 +50,11 @@ obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o
obj-y += dev-uart.o
obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o
obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o
obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o
obj-$(CONFIG_EXYNOS4_DEV_DMA) += dma.o
obj-$(CONFIG_EXYNOS_DEV_DMA) += dma.o
obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o
obj-$(CONFIG_EXYNOS_DEV_DRM) += dev-drm.o
obj-$(CONFIG_EXYNOS_DEV_SYSMMU) += dev-sysmmu.o
obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o
obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
@ -68,4 +69,4 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o
obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o
obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o
obj-$(CONFIG_EXYNOS4_SETUP_SPI) += setup-spi.o
obj-$(CONFIG_EXYNOS_SETUP_SPI) += setup-spi.o

3
arch/arm/mach-exynos/Makefile.boot
View File

@ -1,2 +1,5 @@
zreladdr-y += 0x40008000
params_phys-y := 0x40000100
dtb-$(CONFIG_MACH_EXYNOS4_DT) += exynos4210-origen.dtb exynos4210-smdkv310.dtb
dtb-$(CONFIG_MACH_EXYNOS5_DT) += exynos5250-smdk5250.dtb

101
arch/arm/mach-exynos/clock-exynos4.c
View File

@ -168,7 +168,7 @@ static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
}
static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
}
@ -198,6 +198,11 @@ static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
}
int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS4_CLKGATE_IP_DMC, clk, enable);
}
static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
@ -678,61 +683,55 @@ static struct clk exynos4_init_clocks_off[] = {
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 14),
}, {
.name = "SYSMMU_MDMA",
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "SYSMMU_FIMC0",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "SYSMMU_FIMC1",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "SYSMMU_FIMC2",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = "SYSMMU_FIMC3",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 10),
}, {
.name = "SYSMMU_JPEG",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 11),
}, {
.name = "SYSMMU_FIMD0",
.enable = exynos4_clk_ip_lcd0_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "SYSMMU_FIMD1",
.enable = exynos4_clk_ip_lcd1_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "SYSMMU_PCIe",
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 18),
}, {
.name = "SYSMMU_G2D",
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "SYSMMU_ROTATOR",
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "SYSMMU_TV",
.enable = exynos4_clk_ip_tv_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "SYSMMU_MFC_L",
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
.enable = exynos4_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "SYSMMU_MFC_R",
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
.enable = exynos4_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(tv, 2),
.enable = exynos4_clk_ip_tv_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(jpeg, 3),
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 11),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(rot, 4),
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(fimc0, 5),
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(fimc1, 6),
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(fimc2, 7),
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(fimc3, 8),
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 10),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(fimd0, 10),
.enable = exynos4_clk_ip_lcd0_ctrl,
.ctrlbit = (1 << 4),
}
};

2
arch/arm/mach-exynos/clock-exynos4.h
View File

@ -26,5 +26,7 @@ extern struct clk *exynos4_clkset_group_list[];
extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
extern int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable);
extern int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable);
#endif /* __ASM_ARCH_CLOCK_H */

11
arch/arm/mach-exynos/clock-exynos4210.c
View File

@ -26,6 +26,7 @@
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/sysmmu.h>
#include "common.h"
#include "clock-exynos4.h"
@ -94,6 +95,16 @@ static struct clk init_clocks_off[] = {
.devname = "exynos4-fb.1",
.enable = exynos4_clk_ip_lcd1_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(2d, 14),
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(fimd1, 11),
.enable = exynos4_clk_ip_lcd1_ctrl,
.ctrlbit = (1 << 4),
},
};

38
arch/arm/mach-exynos/clock-exynos4212.c
View File

@ -26,6 +26,7 @@
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/sysmmu.h>
#include "common.h"
#include "clock-exynos4.h"
@ -39,6 +40,16 @@ static struct sleep_save exynos4212_clock_save[] = {
};
#endif
static int exynos4212_clk_ip_isp0_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP0, clk, enable);
}
static int exynos4212_clk_ip_isp1_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP1, clk, enable);
}
static struct clk *clk_src_mpll_user_list[] = {
[0] = &clk_fin_mpll,
[1] = &exynos4_clk_mout_mpll.clk,
@ -66,7 +77,32 @@ static struct clksrc_clk clksrcs[] = {
};
static struct clk init_clocks_off[] = {
/* nothing here yet */
{
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(2d, 14),
.enable = exynos4_clk_ip_dmc_ctrl,
.ctrlbit = (1 << 24),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
.enable = exynos4212_clk_ip_isp0_ctrl,
.ctrlbit = (7 << 8),
}, {
.name = SYSMMU_CLOCK_NAME2,
.devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
.enable = exynos4212_clk_ip_isp1_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "flite",
.devname = "exynos-fimc-lite.0",
.enable = exynos4212_clk_ip_isp0_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "flite",
.devname = "exynos-fimc-lite.1",
.enable = exynos4212_clk_ip_isp0_ctrl,
.ctrlbit = (1 << 3),
}
};
#ifdef CONFIG_PM_SLEEP

192
arch/arm/mach-exynos/clock-exynos5.c
View File

@ -30,7 +30,56 @@
#ifdef CONFIG_PM_SLEEP
static struct sleep_save exynos5_clock_save[] = {
/* will be implemented */
SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP),
SAVE_ITEM(EXYNOS5_CLKSRC_MASK_GSCL),
SAVE_ITEM(EXYNOS5_CLKSRC_MASK_DISP1_0),
SAVE_ITEM(EXYNOS5_CLKSRC_MASK_FSYS),
SAVE_ITEM(EXYNOS5_CLKSRC_MASK_MAUDIO),
SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC0),
SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC1),
SAVE_ITEM(EXYNOS5_CLKGATE_IP_GSCL),
SAVE_ITEM(EXYNOS5_CLKGATE_IP_DISP1),
SAVE_ITEM(EXYNOS5_CLKGATE_IP_MFC),
SAVE_ITEM(EXYNOS5_CLKGATE_IP_G3D),
SAVE_ITEM(EXYNOS5_CLKGATE_IP_GEN),
SAVE_ITEM(EXYNOS5_CLKGATE_IP_FSYS),
SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIC),
SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIS),
SAVE_ITEM(EXYNOS5_CLKGATE_BLOCK),
SAVE_ITEM(EXYNOS5_CLKDIV_TOP0),
SAVE_ITEM(EXYNOS5_CLKDIV_TOP1),
SAVE_ITEM(EXYNOS5_CLKDIV_GSCL),
SAVE_ITEM(EXYNOS5_CLKDIV_DISP1_0),
SAVE_ITEM(EXYNOS5_CLKDIV_GEN),
SAVE_ITEM(EXYNOS5_CLKDIV_MAUDIO),
SAVE_ITEM(EXYNOS5_CLKDIV_FSYS0),
SAVE_ITEM(EXYNOS5_CLKDIV_FSYS1),
SAVE_ITEM(EXYNOS5_CLKDIV_FSYS2),
SAVE_ITEM(EXYNOS5_CLKDIV_FSYS3),
SAVE_ITEM(EXYNOS5_CLKDIV_PERIC0),
SAVE_ITEM(EXYNOS5_CLKDIV_PERIC1),
SAVE_ITEM(EXYNOS5_CLKDIV_PERIC2),
SAVE_ITEM(EXYNOS5_CLKDIV_PERIC3),
SAVE_ITEM(EXYNOS5_CLKDIV_PERIC4),
SAVE_ITEM(EXYNOS5_CLKDIV_PERIC5),
SAVE_ITEM(EXYNOS5_SCLK_DIV_ISP),
SAVE_ITEM(EXYNOS5_CLKSRC_TOP0),
SAVE_ITEM(EXYNOS5_CLKSRC_TOP1),
SAVE_ITEM(EXYNOS5_CLKSRC_TOP2),
SAVE_ITEM(EXYNOS5_CLKSRC_TOP3),
SAVE_ITEM(EXYNOS5_CLKSRC_GSCL),
SAVE_ITEM(EXYNOS5_CLKSRC_DISP1_0),
SAVE_ITEM(EXYNOS5_CLKSRC_MAUDIO),
SAVE_ITEM(EXYNOS5_CLKSRC_FSYS),
SAVE_ITEM(EXYNOS5_CLKSRC_PERIC0),
SAVE_ITEM(EXYNOS5_CLKSRC_PERIC1),
SAVE_ITEM(EXYNOS5_SCLK_SRC_ISP),
SAVE_ITEM(EXYNOS5_EPLL_CON0),
SAVE_ITEM(EXYNOS5_EPLL_CON1),
SAVE_ITEM(EXYNOS5_EPLL_CON2),
SAVE_ITEM(EXYNOS5_VPLL_CON0),
SAVE_ITEM(EXYNOS5_VPLL_CON1),
SAVE_ITEM(EXYNOS5_VPLL_CON2),
};
#endif
@ -82,6 +131,11 @@ static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
}
static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
}
static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
@ -127,6 +181,21 @@ static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
}
static int exynos5_clk_ip_gscl_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GSCL, clk, enable);
}
static int exynos5_clk_ip_isp0_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP0, clk, enable);
}
static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable);
}
/* Core list of CMU_CPU side */
static struct clksrc_clk exynos5_clk_mout_apll = {
@ -145,11 +214,29 @@ static struct clksrc_clk exynos5_clk_sclk_apll = {
.reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
};
static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
.clk = {
.name = "mout_bpll_fout",
},
.sources = &clk_src_bpll_fout,
.reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
};
static struct clk *exynos5_clk_src_bpll_list[] = {
[0] = &clk_fin_bpll,
[1] = &exynos5_clk_mout_bpll_fout.clk,
};
static struct clksrc_sources exynos5_clk_src_bpll = {
.sources = exynos5_clk_src_bpll_list,
.nr_sources = ARRAY_SIZE(exynos5_clk_src_bpll_list),
};
static struct clksrc_clk exynos5_clk_mout_bpll = {
.clk = {
.name = "mout_bpll",
},
.sources = &clk_src_bpll,
.sources = &exynos5_clk_src_bpll,
.reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
};
@ -187,11 +274,29 @@ static struct clksrc_clk exynos5_clk_mout_epll = {
.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
};
static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
.clk = {
.name = "mout_mpll_fout",
},
.sources = &clk_src_mpll_fout,
.reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
};
static struct clk *exynos5_clk_src_mpll_list[] = {
[0] = &clk_fin_mpll,
[1] = &exynos5_clk_mout_mpll_fout.clk,
};
static struct clksrc_sources exynos5_clk_src_mpll = {
.sources = exynos5_clk_src_mpll_list,
.nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_list),
};
struct clksrc_clk exynos5_clk_mout_mpll = {
.clk = {
.name = "mout_mpll",
},
.sources = &clk_src_mpll,
.sources = &exynos5_clk_src_mpll,
.reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
};
@ -453,6 +558,11 @@ static struct clk exynos5_init_clocks_off[] = {
.parent = &exynos5_clk_aclk_66.clk,
.enable = exynos5_clk_ip_peris_ctrl,
.ctrlbit = (1 << 20),
}, {
.name = "watchdog",
.parent = &exynos5_clk_aclk_66.clk,
.enable = exynos5_clk_ip_peris_ctrl,
.ctrlbit = (1 << 19),
}, {
.name = "hsmmc",
.devname = "exynos4-sdhci.0",
@ -630,6 +740,76 @@ static struct clk exynos5_init_clocks_off[] = {
.parent = &exynos5_clk_aclk_66.clk,
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit = (1 << 14),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
.enable = &exynos5_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
.enable = &exynos5_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(tv, 2),
.enable = &exynos5_clk_ip_disp1_ctrl,
.ctrlbit = (1 << 9)
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(jpeg, 3),
.enable = &exynos5_clk_ip_gen_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(rot, 4),
.enable = &exynos5_clk_ip_gen_ctrl,
.ctrlbit = (1 << 6)
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(gsc0, 5),
.enable = &exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(gsc1, 6),
.enable = &exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(gsc2, 7),
.enable = &exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(gsc3, 8),
.enable = &exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 10),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
.enable = &exynos5_clk_ip_isp0_ctrl,
.ctrlbit = (0x3F << 8),
}, {
.name = SYSMMU_CLOCK_NAME2,
.devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
.enable = &exynos5_clk_ip_isp1_ctrl,
.ctrlbit = (0xF << 4),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(camif0, 12),
.enable = &exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 11),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(camif1, 13),
.enable = &exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(2d, 14),
.enable = &exynos5_clk_ip_acp_ctrl,
.ctrlbit = (1 << 7)
}
};
@ -941,10 +1121,12 @@ static struct clksrc_clk *exynos5_sysclks[] = {
&exynos5_clk_mout_apll,
&exynos5_clk_sclk_apll,
&exynos5_clk_mout_bpll,
&exynos5_clk_mout_bpll_fout,
&exynos5_clk_mout_bpll_user,
&exynos5_clk_mout_cpll,
&exynos5_clk_mout_epll,
&exynos5_clk_mout_mpll,
&exynos5_clk_mout_mpll_fout,
&exynos5_clk_mout_mpll_user,
&exynos5_clk_vpllsrc,
&exynos5_clk_sclk_vpll,
@ -1008,7 +1190,9 @@ static struct clk *exynos5_clks[] __initdata = {
&exynos5_clk_sclk_hdmi27m,
&exynos5_clk_sclk_hdmiphy,
&clk_fout_bpll,
&clk_fout_bpll_div2,
&clk_fout_cpll,
&clk_fout_mpll_div2,
&exynos5_clk_armclk,
};
@ -1173,8 +1357,10 @@ void __init_or_cpufreq exynos5_setup_clocks(void)
clk_fout_apll.ops = &exynos5_fout_apll_ops;
clk_fout_bpll.rate = bpll;
clk_fout_bpll_div2.rate = bpll >> 1;
clk_fout_cpll.rate = cpll;
clk_fout_mpll.rate = mpll;
clk_fout_mpll_div2.rate = mpll >> 1;
clk_fout_epll.rate = epll;
clk_fout_vpll.rate = vpll;

178
arch/arm/mach-exynos/common.c
View File

@ -19,6 +19,9 @@
#include <linux/serial_core.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/export.h>
#include <linux/irqdomain.h>
#include <linux/of_address.h>
#include <asm/proc-fns.h>
#include <asm/exception.h>
@ -265,12 +268,12 @@ static struct map_desc exynos5_iodesc[] __initdata = {
}, {
.virtual = (unsigned long)S5P_VA_GIC_CPU,
.pfn = __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
.length = SZ_64K,
.length = SZ_8K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GIC_DIST,
.pfn = __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
.length = SZ_64K,
.length = SZ_4K,
.type = MT_DEVICE,
},
};
@ -399,6 +402,7 @@ struct combiner_chip_data {
void __iomem *base;
};
static struct irq_domain *combiner_irq_domain;
static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
static inline void __iomem *combiner_base(struct irq_data *data)
@ -411,14 +415,14 @@ static inline void __iomem *combiner_base(struct irq_data *data)
static void combiner_mask_irq(struct irq_data *data)
{
u32 mask = 1 << (data->irq % 32);
u32 mask = 1 << (data->hwirq % 32);
__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
}
static void combiner_unmask_irq(struct irq_data *data)
{
u32 mask = 1 << (data->irq % 32);
u32 mask = 1 << (data->hwirq % 32);
__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
}
@ -474,49 +478,127 @@ static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int i
irq_set_chained_handler(irq, combiner_handle_cascade_irq);
}
static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
unsigned int irq_start)
static void __init combiner_init_one(unsigned int combiner_nr,
void __iomem *base)
{
unsigned int i;
unsigned int max_nr;
if (soc_is_exynos5250())
max_nr = EXYNOS5_MAX_COMBINER_NR;
else
max_nr = EXYNOS4_MAX_COMBINER_NR;
if (combiner_nr >= max_nr)
BUG();
combiner_data[combiner_nr].base = base;
combiner_data[combiner_nr].irq_offset = irq_start;
combiner_data[combiner_nr].irq_offset = irq_find_mapping(
combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
/* Disable all interrupts */
__raw_writel(combiner_data[combiner_nr].irq_mask,
base + COMBINER_ENABLE_CLEAR);
}
/* Setup the Linux IRQ subsystem */
#ifdef CONFIG_OF
static int combiner_irq_domain_xlate(struct irq_domain *d,
struct device_node *controller,
const u32 *intspec, unsigned int intsize,
unsigned long *out_hwirq,
unsigned int *out_type)
{
if (d->of_node != controller)
return -EINVAL;
for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
+ MAX_IRQ_IN_COMBINER; i++) {
irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
irq_set_chip_data(i, &combiner_data[combiner_nr]);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
if (intsize < 2)
return -EINVAL;
*out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1];
*out_type = 0;
return 0;
}
#else
static int combiner_irq_domain_xlate(struct irq_domain *d,
struct device_node *controller,
const u32 *intspec, unsigned int intsize,
unsigned long *out_hwirq,
unsigned int *out_type)
{
return -EINVAL;
}
#endif
static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hw)
{
irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
irq_set_chip_data(irq, &combiner_data[hw >> 3]);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
return 0;
}
static struct irq_domain_ops combiner_irq_domain_ops = {
.xlate = combiner_irq_domain_xlate,
.map = combiner_irq_domain_map,
};
void __init combiner_init(void __iomem *combiner_base, struct device_node *np)
{
int i, irq, irq_base;
unsigned int max_nr, nr_irq;
if (np) {
if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
pr_warning("%s: number of combiners not specified, "
"setting default as %d.\n",
__func__, EXYNOS4_MAX_COMBINER_NR);
max_nr = EXYNOS4_MAX_COMBINER_NR;
}
} else {
max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
EXYNOS4_MAX_COMBINER_NR;
}
nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
if (IS_ERR_VALUE(irq_base)) {
irq_base = COMBINER_IRQ(0, 0);
pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base);
}
combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
&combiner_irq_domain_ops, &combiner_data);
if (WARN_ON(!combiner_irq_domain)) {
pr_warning("%s: irq domain init failed\n", __func__);
return;
}
for (i = 0; i < max_nr; i++) {
combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
irq = np ? irq_of_parse_and_map(np, i) : IRQ_SPI(i);
combiner_cascade_irq(i, irq);
}
}
#ifdef CONFIG_OF
int __init combiner_of_init(struct device_node *np, struct device_node *parent)
{
void __iomem *combiner_base;
combiner_base = of_iomap(np, 0);
if (!combiner_base) {
pr_err("%s: failed to map combiner registers\n", __func__);
return -ENXIO;
}
combiner_init(combiner_base, np);
return 0;
}
static const struct of_device_id exynos4_dt_irq_match[] = {
{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
{ .compatible = "samsung,exynos4210-combiner",
.data = combiner_of_init, },
{},
};
#endif
void __init exynos4_init_irq(void)
{
int irq;
unsigned int gic_bank_offset;
gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
@ -528,12 +610,8 @@ void __init exynos4_init_irq(void)
of_irq_init(exynos4_dt_irq_match);
#endif
for (irq = 0; irq < EXYNOS4_MAX_COMBINER_NR; irq++) {
combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
COMBINER_IRQ(irq, 0));
combiner_cascade_irq(irq, IRQ_SPI(irq));
}
if (!of_have_populated_dt())
combiner_init(S5P_VA_COMBINER_BASE, NULL);
/*
* The parameters of s5p_init_irq() are for VIC init.
@ -545,18 +623,9 @@ void __init exynos4_init_irq(void)
void __init exynos5_init_irq(void)
{
int irq;
#ifdef CONFIG_OF
of_irq_init(exynos4_dt_irq_match);
#endif
for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
COMBINER_IRQ(irq, 0));
combiner_cascade_irq(irq, IRQ_SPI(irq));
}
/*
* The parameters of s5p_init_irq() are for VIC init.
* Theses parameters should be NULL and 0 because EXYNOS4
@ -565,30 +634,18 @@ void __init exynos5_init_irq(void)
s5p_init_irq(NULL, 0);
}
struct bus_type exynos4_subsys = {
.name = "exynos4-core",
.dev_name = "exynos4-core",
};
struct bus_type exynos5_subsys = {
.name = "exynos5-core",
.dev_name = "exynos5-core",
struct bus_type exynos_subsys = {
.name = "exynos-core",
.dev_name = "exynos-core",
};
static struct device exynos4_dev = {
.bus = &exynos4_subsys,
};
static struct device exynos5_dev = {
.bus = &exynos5_subsys,
.bus = &exynos_subsys,
};
static int __init exynos_core_init(void)
{
if (soc_is_exynos5250())
return subsys_system_register(&exynos5_subsys, NULL);
else
return subsys_system_register(&exynos4_subsys, NULL);
return subsys_system_register(&exynos_subsys, NULL);
}
core_initcall(exynos_core_init);
@ -675,10 +732,7 @@ static int __init exynos_init(void)
{
printk(KERN_INFO "EXYNOS: Initializing architecture\n");
if (soc_is_exynos5250())
return device_register(&exynos5_dev);
else
return device_register(&exynos4_dev);
return device_register(&exynos4_dev);
}
/* uart registration process */

2
arch/arm/mach-exynos/cpuidle.c
View File

@ -113,7 +113,7 @@ static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
exynos4_set_wakeupmask();
/* Set value of power down register for aftr mode */
exynos4_sys_powerdown_conf(SYS_AFTR);
exynos_sys_powerdown_conf(SYS_AFTR);
__raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
__raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);

29
arch/arm/mach-exynos/dev-drm.c Normal file
View File

@ -0,0 +1,29 @@
/*
* linux/arch/arm/mach-exynos/dev-drm.c
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS - core DRM device
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/kernel.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <plat/devs.h>
static u64 exynos_drm_dma_mask = DMA_BIT_MASK(32);
struct platform_device exynos_device_drm = {
.name = "exynos-drm",
.dev = {
.dma_mask = &exynos_drm_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
}
};

463
arch/arm/mach-exynos/dev-sysmmu.c
View File

@ -1,9 +1,9 @@
/* linux/arch/arm/mach-exynos4/dev-sysmmu.c
/* linux/arch/arm/mach-exynos/dev-sysmmu.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS4 - System MMU support
* EXYNOS - System MMU support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@ -12,222 +12,263 @@
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/export.h>
#include <plat/cpu.h>
#include <mach/map.h>
#include <mach/irqs.h>
#include <mach/sysmmu.h>
#include <plat/s5p-clock.h>
/* These names must be equal to the clock names in mach-exynos4/clock.c */
const char *sysmmu_ips_name[EXYNOS4_SYSMMU_TOTAL_IPNUM] = {
"SYSMMU_MDMA" ,
"SYSMMU_SSS" ,
"SYSMMU_FIMC0" ,
"SYSMMU_FIMC1" ,
"SYSMMU_FIMC2" ,
"SYSMMU_FIMC3" ,
"SYSMMU_JPEG" ,
"SYSMMU_FIMD0" ,
"SYSMMU_FIMD1" ,
"SYSMMU_PCIe" ,
"SYSMMU_G2D" ,
"SYSMMU_ROTATOR",
"SYSMMU_MDMA2" ,
"SYSMMU_TV" ,
"SYSMMU_MFC_L" ,
"SYSMMU_MFC_R" ,
};
static u64 exynos_sysmmu_dma_mask = DMA_BIT_MASK(32);
static struct resource exynos4_sysmmu_resource[] = {
[0] = {
.start = EXYNOS4_PA_SYSMMU_MDMA,
.end = EXYNOS4_PA_SYSMMU_MDMA + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_SYSMMU_MDMA0_0,
.end = IRQ_SYSMMU_MDMA0_0,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = EXYNOS4_PA_SYSMMU_SSS,
.end = EXYNOS4_PA_SYSMMU_SSS + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[3] = {
.start = IRQ_SYSMMU_SSS_0,
.end = IRQ_SYSMMU_SSS_0,
.flags = IORESOURCE_IRQ,
},
[4] = {
.start = EXYNOS4_PA_SYSMMU_FIMC0,
.end = EXYNOS4_PA_SYSMMU_FIMC0 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[5] = {
.start = IRQ_SYSMMU_FIMC0_0,
.end = IRQ_SYSMMU_FIMC0_0,
.flags = IORESOURCE_IRQ,
},
[6] = {
.start = EXYNOS4_PA_SYSMMU_FIMC1,
.end = EXYNOS4_PA_SYSMMU_FIMC1 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[7] = {
.start = IRQ_SYSMMU_FIMC1_0,
.end = IRQ_SYSMMU_FIMC1_0,
.flags = IORESOURCE_IRQ,
},
[8] = {
.start = EXYNOS4_PA_SYSMMU_FIMC2,
.end = EXYNOS4_PA_SYSMMU_FIMC2 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[9] = {
.start = IRQ_SYSMMU_FIMC2_0,
.end = IRQ_SYSMMU_FIMC2_0,
.flags = IORESOURCE_IRQ,
},
[10] = {
.start = EXYNOS4_PA_SYSMMU_FIMC3,
.end = EXYNOS4_PA_SYSMMU_FIMC3 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[11] = {
.start = IRQ_SYSMMU_FIMC3_0,
.end = IRQ_SYSMMU_FIMC3_0,
.flags = IORESOURCE_IRQ,
},
[12] = {
.start = EXYNOS4_PA_SYSMMU_JPEG,
.end = EXYNOS4_PA_SYSMMU_JPEG + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[13] = {
.start = IRQ_SYSMMU_JPEG_0,
.end = IRQ_SYSMMU_JPEG_0,
.flags = IORESOURCE_IRQ,
},
[14] = {
.start = EXYNOS4_PA_SYSMMU_FIMD0,
.end = EXYNOS4_PA_SYSMMU_FIMD0 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[15] = {
.start = IRQ_SYSMMU_LCD0_M0_0,
.end = IRQ_SYSMMU_LCD0_M0_0,
.flags = IORESOURCE_IRQ,
},
[16] = {
.start = EXYNOS4_PA_SYSMMU_FIMD1,
.end = EXYNOS4_PA_SYSMMU_FIMD1 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[17] = {
.start = IRQ_SYSMMU_LCD1_M1_0,
.end = IRQ_SYSMMU_LCD1_M1_0,
.flags = IORESOURCE_IRQ,
},
[18] = {
.start = EXYNOS4_PA_SYSMMU_PCIe,
.end = EXYNOS4_PA_SYSMMU_PCIe + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[19] = {
.start = IRQ_SYSMMU_PCIE_0,
.end = IRQ_SYSMMU_PCIE_0,
.flags = IORESOURCE_IRQ,
},
[20] = {
.start = EXYNOS4_PA_SYSMMU_G2D,
.end = EXYNOS4_PA_SYSMMU_G2D + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[21] = {
.start = IRQ_SYSMMU_2D_0,
.end = IRQ_SYSMMU_2D_0,
.flags = IORESOURCE_IRQ,
},
[22] = {
.start = EXYNOS4_PA_SYSMMU_ROTATOR,
.end = EXYNOS4_PA_SYSMMU_ROTATOR + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[23] = {
.start = IRQ_SYSMMU_ROTATOR_0,
.end = IRQ_SYSMMU_ROTATOR_0,
.flags = IORESOURCE_IRQ,
},
[24] = {
.start = EXYNOS4_PA_SYSMMU_MDMA2,
.end = EXYNOS4_PA_SYSMMU_MDMA2 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[25] = {
.start = IRQ_SYSMMU_MDMA1_0,
.end = IRQ_SYSMMU_MDMA1_0,
.flags = IORESOURCE_IRQ,
},
[26] = {
.start = EXYNOS4_PA_SYSMMU_TV,
.end = EXYNOS4_PA_SYSMMU_TV + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[27] = {
.start = IRQ_SYSMMU_TV_M0_0,
.end = IRQ_SYSMMU_TV_M0_0,
.flags = IORESOURCE_IRQ,
},
[28] = {
.start = EXYNOS4_PA_SYSMMU_MFC_L,
.end = EXYNOS4_PA_SYSMMU_MFC_L + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[29] = {
.start = IRQ_SYSMMU_MFC_M0_0,
.end = IRQ_SYSMMU_MFC_M0_0,
.flags = IORESOURCE_IRQ,
},
[30] = {
.start = EXYNOS4_PA_SYSMMU_MFC_R,
.end = EXYNOS4_PA_SYSMMU_MFC_R + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[31] = {
.start = IRQ_SYSMMU_MFC_M1_0,
.end = IRQ_SYSMMU_MFC_M1_0,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device exynos4_device_sysmmu = {
.name = "s5p-sysmmu",
.id = 32,
.num_resources = ARRAY_SIZE(exynos4_sysmmu_resource),
.resource = exynos4_sysmmu_resource,
};
EXPORT_SYMBOL(exynos4_device_sysmmu);
static struct clk *sysmmu_clk[S5P_SYSMMU_TOTAL_IPNUM];
void sysmmu_clk_init(struct device *dev, sysmmu_ips ips)
{
sysmmu_clk[ips] = clk_get(dev, sysmmu_ips_name[ips]);
if (IS_ERR(sysmmu_clk[ips]))
sysmmu_clk[ips] = NULL;
else
clk_put(sysmmu_clk[ips]);
#define SYSMMU_PLATFORM_DEVICE(ipname, devid) \
static struct sysmmu_platform_data platdata_##ipname = { \
.dbgname = #ipname, \
}; \
struct platform_device SYSMMU_PLATDEV(ipname) = \
{ \
.name = SYSMMU_DEVNAME_BASE, \
.id = devid, \
.dev = { \
.dma_mask = &exynos_sysmmu_dma_mask, \
.coherent_dma_mask = DMA_BIT_MASK(32), \
.platform_data = &platdata_##ipname, \
}, \
}
void sysmmu_clk_enable(sysmmu_ips ips)
{
if (sysmmu_clk[ips])
clk_enable(sysmmu_clk[ips]);
SYSMMU_PLATFORM_DEVICE(mfc_l, 0);
SYSMMU_PLATFORM_DEVICE(mfc_r, 1);
SYSMMU_PLATFORM_DEVICE(tv, 2);
SYSMMU_PLATFORM_DEVICE(jpeg, 3);
SYSMMU_PLATFORM_DEVICE(rot, 4);
SYSMMU_PLATFORM_DEVICE(fimc0, 5); /* fimc* and gsc* exist exclusively */
SYSMMU_PLATFORM_DEVICE(fimc1, 6);
SYSMMU_PLATFORM_DEVICE(fimc2, 7);
SYSMMU_PLATFORM_DEVICE(fimc3, 8);
SYSMMU_PLATFORM_DEVICE(gsc0, 5);
SYSMMU_PLATFORM_DEVICE(gsc1, 6);
SYSMMU_PLATFORM_DEVICE(gsc2, 7);
SYSMMU_PLATFORM_DEVICE(gsc3, 8);
SYSMMU_PLATFORM_DEVICE(isp, 9);
SYSMMU_PLATFORM_DEVICE(fimd0, 10);
SYSMMU_PLATFORM_DEVICE(fimd1, 11);
SYSMMU_PLATFORM_DEVICE(camif0, 12);
SYSMMU_PLATFORM_DEVICE(camif1, 13);
SYSMMU_PLATFORM_DEVICE(2d, 14);
#define SYSMMU_RESOURCE_NAME(core, ipname) sysmmures_##core##_##ipname
#define SYSMMU_RESOURCE(core, ipname) \
static struct resource SYSMMU_RESOURCE_NAME(core, ipname)[] __initdata =
#define DEFINE_SYSMMU_RESOURCE(core, mem, irq) \
DEFINE_RES_MEM_NAMED(core##_PA_SYSMMU_##mem, SZ_4K, #mem), \
DEFINE_RES_IRQ_NAMED(core##_IRQ_SYSMMU_##irq##_0, #mem)
#define SYSMMU_RESOURCE_DEFINE(core, ipname, mem, irq) \
SYSMMU_RESOURCE(core, ipname) { \
DEFINE_SYSMMU_RESOURCE(core, mem, irq) \
}
struct sysmmu_resource_map {
struct platform_device *pdev;
struct resource *res;
u32 rnum;
struct device *pdd;
char *clocknames;
};
#define SYSMMU_RESOURCE_MAPPING(core, ipname, resname) { \
.pdev = &SYSMMU_PLATDEV(ipname), \
.res = SYSMMU_RESOURCE_NAME(EXYNOS##core, resname), \
.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
.clocknames = SYSMMU_CLOCK_NAME, \
}
void sysmmu_clk_disable(sysmmu_ips ips)
{
if (sysmmu_clk[ips])
clk_disable(sysmmu_clk[ips]);
#define SYSMMU_RESOURCE_MAPPING_MC(core, ipname, resname, pdata) { \
.pdev = &SYSMMU_PLATDEV(ipname), \
.res = SYSMMU_RESOURCE_NAME(EXYNOS##core, resname), \
.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
.clocknames = SYSMMU_CLOCK_NAME "," SYSMMU_CLOCK_NAME2, \
}
#ifdef CONFIG_EXYNOS_DEV_PD
#define SYSMMU_RESOURCE_MAPPING_PD(core, ipname, resname, pd) { \
.pdev = &SYSMMU_PLATDEV(ipname), \
.res = &SYSMMU_RESOURCE_NAME(EXYNOS##core, resname), \
.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
.clocknames = SYSMMU_CLOCK_NAME, \
.pdd = &exynos##core##_device_pd[pd].dev, \
}
#define SYSMMU_RESOURCE_MAPPING_MCPD(core, ipname, resname, pd, pdata) {\
.pdev = &SYSMMU_PLATDEV(ipname), \
.res = &SYSMMU_RESOURCE_NAME(EXYNOS##core, resname), \
.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
.clocknames = SYSMMU_CLOCK_NAME "," SYSMMU_CLOCK_NAME2, \
.pdd = &exynos##core##_device_pd[pd].dev, \
}
#else
#define SYSMMU_RESOURCE_MAPPING_PD(core, ipname, resname, pd) \
SYSMMU_RESOURCE_MAPPING(core, ipname, resname)
#define SYSMMU_RESOURCE_MAPPING_MCPD(core, ipname, resname, pd, pdata) \
SYSMMU_RESOURCE_MAPPING_MC(core, ipname, resname, pdata)
#endif /* CONFIG_EXYNOS_DEV_PD */
#ifdef CONFIG_ARCH_EXYNOS4
SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc0, FIMC0, FIMC0);
SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc1, FIMC1, FIMC1);
SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc2, FIMC2, FIMC2);
SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc3, FIMC3, FIMC3);
SYSMMU_RESOURCE_DEFINE(EXYNOS4, jpeg, JPEG, JPEG);
SYSMMU_RESOURCE_DEFINE(EXYNOS4, 2d, G2D, 2D);
SYSMMU_RESOURCE_DEFINE(EXYNOS4, tv, TV, TV_M0);
SYSMMU_RESOURCE_DEFINE(EXYNOS4, 2d_acp, 2D_ACP, 2D);
SYSMMU_RESOURCE_DEFINE(EXYNOS4, rot, ROTATOR, ROTATOR);
SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimd0, FIMD0, LCD0_M0);
SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimd1, FIMD1, LCD1_M1);
SYSMMU_RESOURCE_DEFINE(EXYNOS4, flite0, FIMC_LITE0, FIMC_LITE0);
SYSMMU_RESOURCE_DEFINE(EXYNOS4, flite1, FIMC_LITE1, FIMC_LITE1);
SYSMMU_RESOURCE_DEFINE(EXYNOS4, mfc_r, MFC_R, MFC_M0);
SYSMMU_RESOURCE_DEFINE(EXYNOS4, mfc_l, MFC_L, MFC_M1);
SYSMMU_RESOURCE(EXYNOS4, isp) {
DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_ISP, FIMC_ISP),
DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_DRC, FIMC_DRC),
DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_FD, FIMC_FD),
DEFINE_SYSMMU_RESOURCE(EXYNOS4, ISPCPU, FIMC_CX),
};
static struct sysmmu_resource_map sysmmu_resmap4[] __initdata = {
SYSMMU_RESOURCE_MAPPING_PD(4, fimc0, fimc0, PD_CAM),
SYSMMU_RESOURCE_MAPPING_PD(4, fimc1, fimc1, PD_CAM),
SYSMMU_RESOURCE_MAPPING_PD(4, fimc2, fimc2, PD_CAM),
SYSMMU_RESOURCE_MAPPING_PD(4, fimc3, fimc3, PD_CAM),
SYSMMU_RESOURCE_MAPPING_PD(4, tv, tv, PD_TV),
SYSMMU_RESOURCE_MAPPING_PD(4, mfc_r, mfc_r, PD_MFC),
SYSMMU_RESOURCE_MAPPING_PD(4, mfc_l, mfc_l, PD_MFC),
SYSMMU_RESOURCE_MAPPING_PD(4, rot, rot, PD_LCD0),
SYSMMU_RESOURCE_MAPPING_PD(4, jpeg, jpeg, PD_CAM),
SYSMMU_RESOURCE_MAPPING_PD(4, fimd0, fimd0, PD_LCD0),
};
static struct sysmmu_resource_map sysmmu_resmap4210[] __initdata = {
SYSMMU_RESOURCE_MAPPING_PD(4, 2d, 2d, PD_LCD0),
SYSMMU_RESOURCE_MAPPING_PD(4, fimd1, fimd1, PD_LCD1),
};
static struct sysmmu_resource_map sysmmu_resmap4212[] __initdata = {
SYSMMU_RESOURCE_MAPPING(4, 2d, 2d_acp),
SYSMMU_RESOURCE_MAPPING_PD(4, camif0, flite0, PD_ISP),
SYSMMU_RESOURCE_MAPPING_PD(4, camif1, flite1, PD_ISP),
SYSMMU_RESOURCE_MAPPING_PD(4, isp, isp, PD_ISP),
};
#endif /* CONFIG_ARCH_EXYNOS4 */
#ifdef CONFIG_ARCH_EXYNOS5
SYSMMU_RESOURCE_DEFINE(EXYNOS5, jpeg, JPEG, JPEG);
SYSMMU_RESOURCE_DEFINE(EXYNOS5, fimd1, FIMD1, FIMD1);
SYSMMU_RESOURCE_DEFINE(EXYNOS5, 2d, 2D, 2D);
SYSMMU_RESOURCE_DEFINE(EXYNOS5, rot, ROTATOR, ROTATOR);
SYSMMU_RESOURCE_DEFINE(EXYNOS5, tv, TV, TV);
SYSMMU_RESOURCE_DEFINE(EXYNOS5, flite0, LITE0, LITE0);
SYSMMU_RESOURCE_DEFINE(EXYNOS5, flite1, LITE1, LITE1);
SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc0, GSC0, GSC0);
SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc1, GSC1, GSC1);
SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc2, GSC2, GSC2);
SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc3, GSC3, GSC3);
SYSMMU_RESOURCE_DEFINE(EXYNOS5, mfc_r, MFC_R, MFC_R);
SYSMMU_RESOURCE_DEFINE(EXYNOS5, mfc_l, MFC_L, MFC_L);
SYSMMU_RESOURCE(EXYNOS5, isp) {
DEFINE_SYSMMU_RESOURCE(EXYNOS5, ISP, ISP),
DEFINE_SYSMMU_RESOURCE(EXYNOS5, DRC, DRC),
DEFINE_SYSMMU_RESOURCE(EXYNOS5, FD, FD),
DEFINE_SYSMMU_RESOURCE(EXYNOS5, ISPCPU, MCUISP),
DEFINE_SYSMMU_RESOURCE(EXYNOS5, SCALERC, SCALERCISP),
DEFINE_SYSMMU_RESOURCE(EXYNOS5, SCALERP, SCALERPISP),
DEFINE_SYSMMU_RESOURCE(EXYNOS5, ODC, ODC),
DEFINE_SYSMMU_RESOURCE(EXYNOS5, DIS0, DIS0),
DEFINE_SYSMMU_RESOURCE(EXYNOS5, DIS1, DIS1),
DEFINE_SYSMMU_RESOURCE(EXYNOS5, 3DNR, 3DNR),
};
static struct sysmmu_resource_map sysmmu_resmap5[] __initdata = {
SYSMMU_RESOURCE_MAPPING(5, jpeg, jpeg),
SYSMMU_RESOURCE_MAPPING(5, fimd1, fimd1),
SYSMMU_RESOURCE_MAPPING(5, 2d, 2d),
SYSMMU_RESOURCE_MAPPING(5, rot, rot),
SYSMMU_RESOURCE_MAPPING_PD(5, tv, tv, PD_DISP1),
SYSMMU_RESOURCE_MAPPING_PD(5, camif0, flite0, PD_GSCL),
SYSMMU_RESOURCE_MAPPING_PD(5, camif1, flite1, PD_GSCL),
SYSMMU_RESOURCE_MAPPING_PD(5, gsc0, gsc0, PD_GSCL),
SYSMMU_RESOURCE_MAPPING_PD(5, gsc1, gsc1, PD_GSCL),
SYSMMU_RESOURCE_MAPPING_PD(5, gsc2, gsc2, PD_GSCL),
SYSMMU_RESOURCE_MAPPING_PD(5, gsc3, gsc3, PD_GSCL),
SYSMMU_RESOURCE_MAPPING_PD(5, mfc_r, mfc_r, PD_MFC),
SYSMMU_RESOURCE_MAPPING_PD(5, mfc_l, mfc_l, PD_MFC),
SYSMMU_RESOURCE_MAPPING_MCPD(5, isp, isp, PD_ISP, mc_platdata),
};
#endif /* CONFIG_ARCH_EXYNOS5 */
static int __init init_sysmmu_platform_device(void)
{
int i, j;
struct sysmmu_resource_map *resmap[2] = {NULL, NULL};
int nmap[2] = {0, 0};
#ifdef CONFIG_ARCH_EXYNOS5
if (soc_is_exynos5250()) {
resmap[0] = sysmmu_resmap5;
nmap[0] = ARRAY_SIZE(sysmmu_resmap5);
nmap[1] = 0;
}
#endif
#ifdef CONFIG_ARCH_EXYNOS4
if (resmap[0] == NULL) {
resmap[0] = sysmmu_resmap4;
nmap[0] = ARRAY_SIZE(sysmmu_resmap4);
}
if (soc_is_exynos4210()) {
resmap[1] = sysmmu_resmap4210;
nmap[1] = ARRAY_SIZE(sysmmu_resmap4210);
}
if (soc_is_exynos4412() || soc_is_exynos4212()) {
resmap[1] = sysmmu_resmap4212;
nmap[1] = ARRAY_SIZE(sysmmu_resmap4212);
}
#endif
for (j = 0; j < 2; j++) {
for (i = 0; i < nmap[j]; i++) {
struct sysmmu_resource_map *map;
struct sysmmu_platform_data *platdata;
map = &resmap[j][i];
map->pdev->dev.parent = map->pdd;
platdata = map->pdev->dev.platform_data;
platdata->clockname = map->clocknames;
if (platform_device_add_resources(map->pdev, map->res,
map->rnum)) {
pr_err("%s: Failed to add device resources for "
"%s.%d\n", __func__,
map->pdev->name, map->pdev->id);
continue;
}
if (platform_device_register(map->pdev)) {
pr_err("%s: Failed to register %s.%d\n",
__func__, map->pdev->name,
map->pdev->id);
}
}
}
return 0;
}
arch_initcall(init_sysmmu_platform_device);

141
arch/arm/mach-exynos/dma.c
View File

@ -103,10 +103,45 @@ static u8 exynos4212_pdma0_peri[] = {
DMACH_MIPI_HSI5,
};
struct dma_pl330_platdata exynos4_pdma0_pdata;
static u8 exynos5250_pdma0_peri[] = {
DMACH_PCM0_RX,
DMACH_PCM0_TX,
DMACH_PCM2_RX,
DMACH_PCM2_TX,
DMACH_SPI0_RX,
DMACH_SPI0_TX,
DMACH_SPI2_RX,
DMACH_SPI2_TX,
DMACH_I2S0S_TX,
DMACH_I2S0_RX,
DMACH_I2S0_TX,
DMACH_I2S2_RX,
DMACH_I2S2_TX,
DMACH_UART0_RX,
DMACH_UART0_TX,
DMACH_UART2_RX,
DMACH_UART2_TX,
DMACH_UART4_RX,
DMACH_UART4_TX,
DMACH_SLIMBUS0_RX,
DMACH_SLIMBUS0_TX,
DMACH_SLIMBUS2_RX,
DMACH_SLIMBUS2_TX,
DMACH_SLIMBUS4_RX,
DMACH_SLIMBUS4_TX,
DMACH_AC97_MICIN,
DMACH_AC97_PCMIN,
DMACH_AC97_PCMOUT,
DMACH_MIPI_HSI0,
DMACH_MIPI_HSI2,
DMACH_MIPI_HSI4,
DMACH_MIPI_HSI6,
};
static AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330,
EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos4_pdma0_pdata);
static struct dma_pl330_platdata exynos_pdma0_pdata;
static AMBA_AHB_DEVICE(exynos_pdma0, "dma-pl330.0", 0x00041330,
EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos_pdma0_pdata);
static u8 exynos4210_pdma1_peri[] = {
DMACH_PCM0_RX,
@ -169,10 +204,45 @@ static u8 exynos4212_pdma1_peri[] = {
DMACH_MIPI_HSI7,
};
static struct dma_pl330_platdata exynos4_pdma1_pdata;
static u8 exynos5250_pdma1_peri[] = {
DMACH_PCM0_RX,
DMACH_PCM0_TX,
DMACH_PCM1_RX,
DMACH_PCM1_TX,
DMACH_SPI1_RX,
DMACH_SPI1_TX,
DMACH_PWM,
DMACH_SPDIF,
DMACH_I2S0S_TX,
DMACH_I2S0_RX,
DMACH_I2S0_TX,
DMACH_I2S1_RX,
DMACH_I2S1_TX,
DMACH_UART0_RX,
DMACH_UART0_TX,
DMACH_UART1_RX,
DMACH_UART1_TX,
DMACH_UART3_RX,
DMACH_UART3_TX,
DMACH_SLIMBUS1_RX,
DMACH_SLIMBUS1_TX,
DMACH_SLIMBUS3_RX,
DMACH_SLIMBUS3_TX,
DMACH_SLIMBUS5_RX,
DMACH_SLIMBUS5_TX,
DMACH_SLIMBUS0AUX_RX,
DMACH_SLIMBUS0AUX_TX,
DMACH_DISP1,
DMACH_MIPI_HSI1,
DMACH_MIPI_HSI3,
DMACH_MIPI_HSI5,
DMACH_MIPI_HSI7,
};
static AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330,
EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos4_pdma1_pdata);
static struct dma_pl330_platdata exynos_pdma1_pdata;
static AMBA_AHB_DEVICE(exynos_pdma1, "dma-pl330.1", 0x00041330,
EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos_pdma1_pdata);
static u8 mdma_peri[] = {
DMACH_MTOM_0,
@ -185,46 +255,63 @@ static u8 mdma_peri[] = {
DMACH_MTOM_7,
};
static struct dma_pl330_platdata exynos4_mdma1_pdata = {
static struct dma_pl330_platdata exynos_mdma1_pdata = {
.nr_valid_peri = ARRAY_SIZE(mdma_peri),
.peri_id = mdma_peri,
};
static AMBA_AHB_DEVICE(exynos4_mdma1, "dma-pl330.2", 0x00041330,
EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos4_mdma1_pdata);
static AMBA_AHB_DEVICE(exynos_mdma1, "dma-pl330.2", 0x00041330,
EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos_mdma1_pdata);
static int __init exynos4_dma_init(void)
static int __init exynos_dma_init(void)
{
if (of_have_populated_dt())
return 0;
if (soc_is_exynos4210()) {
exynos4_pdma0_pdata.nr_valid_peri =
exynos_pdma0_pdata.nr_valid_peri =
ARRAY_SIZE(exynos4210_pdma0_peri);
exynos4_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
exynos4_pdma1_pdata.nr_valid_peri =
exynos_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
exynos_pdma1_pdata.nr_valid_peri =
ARRAY_SIZE(exynos4210_pdma1_peri);
exynos4_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
exynos_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
exynos4_pdma0_pdata.nr_valid_peri =
exynos_pdma0_pdata.nr_valid_peri =
ARRAY_SIZE(exynos4212_pdma0_peri);
exynos4_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
exynos4_pdma1_pdata.nr_valid_peri =
exynos_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
exynos_pdma1_pdata.nr_valid_peri =
ARRAY_SIZE(exynos4212_pdma1_peri);
exynos4_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
exynos_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
} else if (soc_is_exynos5250()) {
exynos_pdma0_pdata.nr_valid_peri =
ARRAY_SIZE(exynos5250_pdma0_peri);
exynos_pdma0_pdata.peri_id = exynos5250_pdma0_peri;
exynos_pdma1_pdata.nr_valid_peri =
ARRAY_SIZE(exynos5250_pdma1_peri);
exynos_pdma1_pdata.peri_id = exynos5250_pdma1_peri;
exynos_pdma0_device.res.start = EXYNOS5_PA_PDMA0;
exynos_pdma0_device.res.end = EXYNOS5_PA_PDMA0 + SZ_4K;
exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA0;
exynos_pdma1_device.res.start = EXYNOS5_PA_PDMA1;
exynos_pdma1_device.res.end = EXYNOS5_PA_PDMA1 + SZ_4K;
exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA1;
exynos_mdma1_device.res.start = EXYNOS5_PA_MDMA1;
exynos_mdma1_device.res.end = EXYNOS5_PA_MDMA1 + SZ_4K;
exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_MDMA1;
}
dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask);
dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask);
amba_device_register(&exynos4_pdma0_device, &iomem_resource);
dma_cap_set(DMA_SLAVE, exynos_pdma0_pdata.cap_mask);
dma_cap_set(DMA_CYCLIC, exynos_pdma0_pdata.cap_mask);
amba_device_register(&exynos_pdma0_device, &iomem_resource);
dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask);
dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);
amba_device_register(&exynos4_pdma1_device, &iomem_resource);
dma_cap_set(DMA_SLAVE, exynos_pdma1_pdata.cap_mask);
dma_cap_set(DMA_CYCLIC, exynos_pdma1_pdata.cap_mask);
amba_device_register(&exynos_pdma1_device, &iomem_resource);
dma_cap_set(DMA_MEMCPY, exynos4_mdma1_pdata.cap_mask);
amba_device_register(&exynos4_mdma1_device, &iomem_resource);
dma_cap_set(DMA_MEMCPY, exynos_mdma1_pdata.cap_mask);
amba_device_register(&exynos_mdma1_device, &iomem_resource);
return 0;
}
arch_initcall(exynos4_dma_init);
arch_initcall(exynos_dma_init);

9
arch/arm/mach-exynos/include/mach/gpio.h
View File

@ -153,10 +153,11 @@ enum exynos4_gpio_number {
#define EXYNOS5_GPIO_B2_NR (4)
#define EXYNOS5_GPIO_B3_NR (4)
#define EXYNOS5_GPIO_C0_NR (7)
#define EXYNOS5_GPIO_C1_NR (7)
#define EXYNOS5_GPIO_C1_NR (4)
#define EXYNOS5_GPIO_C2_NR (7)
#define EXYNOS5_GPIO_C3_NR (7)
#define EXYNOS5_GPIO_D0_NR (8)
#define EXYNOS5_GPIO_C4_NR (7)
#define EXYNOS5_GPIO_D0_NR (4)
#define EXYNOS5_GPIO_D1_NR (8)
#define EXYNOS5_GPIO_Y0_NR (6)
#define EXYNOS5_GPIO_Y1_NR (4)
@ -199,7 +200,8 @@ enum exynos5_gpio_number {
EXYNOS5_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0),
EXYNOS5_GPIO_C2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1),
EXYNOS5_GPIO_C3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2),
EXYNOS5_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
EXYNOS5_GPIO_C4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
EXYNOS5_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C4),
EXYNOS5_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0),
EXYNOS5_GPIO_Y0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1),
EXYNOS5_GPIO_Y1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0),
@ -242,6 +244,7 @@ enum exynos5_gpio_number {
#define EXYNOS5_GPC1(_nr) (EXYNOS5_GPIO_C1_START + (_nr))
#define EXYNOS5_GPC2(_nr) (EXYNOS5_GPIO_C2_START + (_nr))
#define EXYNOS5_GPC3(_nr) (EXYNOS5_GPIO_C3_START + (_nr))
#define EXYNOS5_GPC4(_nr) (EXYNOS5_GPIO_C4_START + (_nr))
#define EXYNOS5_GPD0(_nr) (EXYNOS5_GPIO_D0_START + (_nr))
#define EXYNOS5_GPD1(_nr) (EXYNOS5_GPIO_D1_START + (_nr))
#define EXYNOS5_GPY0(_nr) (EXYNOS5_GPIO_Y0_START + (_nr))

65
arch/arm/mach-exynos/include/mach/irqs.h
View File

@ -154,6 +154,13 @@
#define EXYNOS4_IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6)
#define EXYNOS4_IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7)
#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE0_0 COMBINER_IRQ(16, 0)
#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE1_0 COMBINER_IRQ(16, 1)
#define EXYNOS4_IRQ_SYSMMU_FIMC_ISP_0 COMBINER_IRQ(16, 2)
#define EXYNOS4_IRQ_SYSMMU_FIMC_DRC_0 COMBINER_IRQ(16, 3)
#define EXYNOS4_IRQ_SYSMMU_FIMC_FD_0 COMBINER_IRQ(16, 4)
#define EXYNOS4_IRQ_SYSMMU_FIMC_CX_0 COMBINER_IRQ(16, 5)
#define EXYNOS4_IRQ_FIMD0_FIFO COMBINER_IRQ(11, 0)
#define EXYNOS4_IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1)
#define EXYNOS4_IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2)
@ -220,24 +227,6 @@
#define IRQ_KEYPAD EXYNOS4_IRQ_KEYPAD
#define IRQ_PMU EXYNOS4_IRQ_PMU
#define IRQ_SYSMMU_MDMA0_0 EXYNOS4_IRQ_SYSMMU_MDMA0_0
#define IRQ_SYSMMU_SSS_0 EXYNOS4_IRQ_SYSMMU_SSS_0
#define IRQ_SYSMMU_FIMC0_0 EXYNOS4_IRQ_SYSMMU_FIMC0_0
#define IRQ_SYSMMU_FIMC1_0 EXYNOS4_IRQ_SYSMMU_FIMC1_0
#define IRQ_SYSMMU_FIMC2_0 EXYNOS4_IRQ_SYSMMU_FIMC2_0
#define IRQ_SYSMMU_FIMC3_0 EXYNOS4_IRQ_SYSMMU_FIMC3_0
#define IRQ_SYSMMU_JPEG_0 EXYNOS4_IRQ_SYSMMU_JPEG_0
#define IRQ_SYSMMU_2D_0 EXYNOS4_IRQ_SYSMMU_2D_0
#define IRQ_SYSMMU_ROTATOR_0 EXYNOS4_IRQ_SYSMMU_ROTATOR_0
#define IRQ_SYSMMU_MDMA1_0 EXYNOS4_IRQ_SYSMMU_MDMA1_0
#define IRQ_SYSMMU_LCD0_M0_0 EXYNOS4_IRQ_SYSMMU_LCD0_M0_0
#define IRQ_SYSMMU_LCD1_M1_0 EXYNOS4_IRQ_SYSMMU_LCD1_M1_0
#define IRQ_SYSMMU_TV_M0_0 EXYNOS4_IRQ_SYSMMU_TV_M0_0
#define IRQ_SYSMMU_MFC_M0_0 EXYNOS4_IRQ_SYSMMU_MFC_M0_0
#define IRQ_SYSMMU_MFC_M1_0 EXYNOS4_IRQ_SYSMMU_MFC_M1_0
#define IRQ_SYSMMU_PCIE_0 EXYNOS4_IRQ_SYSMMU_PCIE_0
#define IRQ_FIMD0_FIFO EXYNOS4_IRQ_FIMD0_FIFO
#define IRQ_FIMD0_VSYNC EXYNOS4_IRQ_FIMD0_VSYNC
#define IRQ_FIMD0_SYSTEM EXYNOS4_IRQ_FIMD0_SYSTEM
@ -297,6 +286,7 @@
#define EXYNOS5_IRQ_MIPICSI1 IRQ_SPI(80)
#define EXYNOS5_IRQ_EFNFCON_DMA_ABORT IRQ_SPI(81)
#define EXYNOS5_IRQ_MIPIDSI0 IRQ_SPI(82)
#define EXYNOS5_IRQ_WDT_IOP IRQ_SPI(83)
#define EXYNOS5_IRQ_ROTATOR IRQ_SPI(84)
#define EXYNOS5_IRQ_GSC0 IRQ_SPI(85)
#define EXYNOS5_IRQ_GSC1 IRQ_SPI(86)
@ -305,8 +295,8 @@
#define EXYNOS5_IRQ_JPEG IRQ_SPI(89)
#define EXYNOS5_IRQ_EFNFCON_DMA IRQ_SPI(90)
#define EXYNOS5_IRQ_2D IRQ_SPI(91)
#define EXYNOS5_IRQ_SFMC0 IRQ_SPI(92)
#define EXYNOS5_IRQ_SFMC1 IRQ_SPI(93)
#define EXYNOS5_IRQ_EFNFCON_0 IRQ_SPI(92)
#define EXYNOS5_IRQ_EFNFCON_1 IRQ_SPI(93)
#define EXYNOS5_IRQ_MIXER IRQ_SPI(94)
#define EXYNOS5_IRQ_HDMI IRQ_SPI(95)
#define EXYNOS5_IRQ_MFC IRQ_SPI(96)
@ -320,7 +310,7 @@
#define EXYNOS5_IRQ_PCM2 IRQ_SPI(104)
#define EXYNOS5_IRQ_SPDIF IRQ_SPI(105)
#define EXYNOS5_IRQ_ADC0 IRQ_SPI(106)
#define EXYNOS5_IRQ_ADC1 IRQ_SPI(107)
#define EXYNOS5_IRQ_SATA_PHY IRQ_SPI(108)
#define EXYNOS5_IRQ_SATA_PMEMREQ IRQ_SPI(109)
#define EXYNOS5_IRQ_CAM_C IRQ_SPI(110)
@ -329,8 +319,9 @@
#define EXYNOS5_IRQ_DP1_INTP1 IRQ_SPI(113)
#define EXYNOS5_IRQ_CEC IRQ_SPI(114)
#define EXYNOS5_IRQ_SATA IRQ_SPI(115)
#define EXYNOS5_IRQ_NFCON IRQ_SPI(116)
#define EXYNOS5_IRQ_MCT_L0 IRQ_SPI(120)
#define EXYNOS5_IRQ_MCT_L1 IRQ_SPI(121)
#define EXYNOS5_IRQ_MMC44 IRQ_SPI(123)
#define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124)
#define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125)
@ -338,7 +329,6 @@
#define EXYNOS5_IRQ_RP_TIMER IRQ_SPI(127)
#define EXYNOS5_IRQ_PMU COMBINER_IRQ(1, 2)
#define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(1, 6)
#define EXYNOS5_IRQ_SYSMMU_GSC0_0 COMBINER_IRQ(2, 0)
#define EXYNOS5_IRQ_SYSMMU_GSC0_1 COMBINER_IRQ(2, 1)
@ -349,6 +339,8 @@
#define EXYNOS5_IRQ_SYSMMU_GSC3_0 COMBINER_IRQ(2, 6)
#define EXYNOS5_IRQ_SYSMMU_GSC3_1 COMBINER_IRQ(2, 7)
#define EXYNOS5_IRQ_SYSMMU_LITE2_0 COMBINER_IRQ(3, 0)
#define EXYNOS5_IRQ_SYSMMU_LITE2_1 COMBINER_IRQ(3, 1)
#define EXYNOS5_IRQ_SYSMMU_FIMD1_0 COMBINER_IRQ(3, 2)
#define EXYNOS5_IRQ_SYSMMU_FIMD1_1 COMBINER_IRQ(3, 3)
#define EXYNOS5_IRQ_SYSMMU_LITE0_0 COMBINER_IRQ(3, 4)
@ -372,8 +364,8 @@
#define EXYNOS5_IRQ_SYSMMU_ARM_0 COMBINER_IRQ(6, 0)
#define EXYNOS5_IRQ_SYSMMU_ARM_1 COMBINER_IRQ(6, 1)
#define EXYNOS5_IRQ_SYSMMU_MFC_L_0 COMBINER_IRQ(6, 2)
#define EXYNOS5_IRQ_SYSMMU_MFC_L_1 COMBINER_IRQ(6, 3)
#define EXYNOS5_IRQ_SYSMMU_MFC_R_0 COMBINER_IRQ(6, 2)
#define EXYNOS5_IRQ_SYSMMU_MFC_R_1 COMBINER_IRQ(6, 3)
#define EXYNOS5_IRQ_SYSMMU_RTIC_0 COMBINER_IRQ(6, 4)
#define EXYNOS5_IRQ_SYSMMU_RTIC_1 COMBINER_IRQ(6, 5)
#define EXYNOS5_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(6, 6)
@ -385,11 +377,9 @@
#define EXYNOS5_IRQ_SYSMMU_MDMA1_1 COMBINER_IRQ(7, 3)
#define EXYNOS5_IRQ_SYSMMU_TV_0 COMBINER_IRQ(7, 4)
#define EXYNOS5_IRQ_SYSMMU_TV_1 COMBINER_IRQ(7, 5)
#define EXYNOS5_IRQ_SYSMMU_GPSX_0 COMBINER_IRQ(7, 6)
#define EXYNOS5_IRQ_SYSMMU_GPSX_1 COMBINER_IRQ(7, 7)
#define EXYNOS5_IRQ_SYSMMU_MFC_R_0 COMBINER_IRQ(8, 5)
#define EXYNOS5_IRQ_SYSMMU_MFC_R_1 COMBINER_IRQ(8, 6)
#define EXYNOS5_IRQ_SYSMMU_MFC_L_0 COMBINER_IRQ(8, 5)
#define EXYNOS5_IRQ_SYSMMU_MFC_L_1 COMBINER_IRQ(8, 6)
#define EXYNOS5_IRQ_SYSMMU_DIS1_0 COMBINER_IRQ(9, 4)
#define EXYNOS5_IRQ_SYSMMU_DIS1_1 COMBINER_IRQ(9, 5)
@ -405,17 +395,24 @@
#define EXYNOS5_IRQ_SYSMMU_DRC_0 COMBINER_IRQ(11, 6)
#define EXYNOS5_IRQ_SYSMMU_DRC_1 COMBINER_IRQ(11, 7)
#define EXYNOS5_IRQ_MDMA1_ABORT COMBINER_IRQ(13, 1)
#define EXYNOS5_IRQ_MDMA0_ABORT COMBINER_IRQ(15, 3)
#define EXYNOS5_IRQ_FIMD1_FIFO COMBINER_IRQ(18, 4)
#define EXYNOS5_IRQ_FIMD1_VSYNC COMBINER_IRQ(18, 5)
#define EXYNOS5_IRQ_FIMD1_SYSTEM COMBINER_IRQ(18, 6)
#define EXYNOS5_IRQ_ARMIOP_GIC COMBINER_IRQ(19, 0)
#define EXYNOS5_IRQ_ARMISP_GIC COMBINER_IRQ(19, 1)
#define EXYNOS5_IRQ_IOP_GIC COMBINER_IRQ(19, 3)
#define EXYNOS5_IRQ_ISP_GIC COMBINER_IRQ(19, 4)
#define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(22, 4)
#define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0)
#define EXYNOS5_IRQ_MCT_L0 COMBINER_IRQ(23, 1)
#define EXYNOS5_IRQ_MCT_L1 COMBINER_IRQ(23, 2)
#define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3)
#define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4)
#define EXYNOS5_IRQ_MCT_G2 COMBINER_IRQ(23, 5)
#define EXYNOS5_IRQ_MCT_G3 COMBINER_IRQ(23, 6)
#define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0)
#define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1)
@ -446,7 +443,7 @@
#define EXYNOS5_MAX_COMBINER_NR 32
#define EXYNOS5_IRQ_GPIO1_NR_GROUPS 13
#define EXYNOS5_IRQ_GPIO1_NR_GROUPS 14
#define EXYNOS5_IRQ_GPIO2_NR_GROUPS 9
#define EXYNOS5_IRQ_GPIO3_NR_GROUPS 5
#define EXYNOS5_IRQ_GPIO4_NR_GROUPS 1

45
arch/arm/mach-exynos/include/mach/map.h
View File

@ -34,6 +34,9 @@
#define EXYNOS4_PA_JPEG 0x11840000
/* x = 0...1 */
#define EXYNOS4_PA_FIMC_LITE(x) (0x12390000 + ((x) * 0x10000))
#define EXYNOS4_PA_G2D 0x12800000
#define EXYNOS4_PA_I2S0 0x03830000
@ -78,8 +81,8 @@
#define EXYNOS4_PA_GIC_CPU 0x10480000
#define EXYNOS4_PA_GIC_DIST 0x10490000
#define EXYNOS5_PA_GIC_CPU 0x10480000
#define EXYNOS5_PA_GIC_DIST 0x10490000
#define EXYNOS5_PA_GIC_CPU 0x10482000
#define EXYNOS5_PA_GIC_DIST 0x10481000
#define EXYNOS4_PA_COREPERI 0x10500000
#define EXYNOS4_PA_TWD 0x10500600
@ -95,6 +98,7 @@
#define EXYNOS5_PA_PDMA1 0x121B0000
#define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000
#define EXYNOS4_PA_SYSMMU_2D_ACP 0x10A40000
#define EXYNOS4_PA_SYSMMU_SSS 0x10A50000
#define EXYNOS4_PA_SYSMMU_FIMC0 0x11A20000
#define EXYNOS4_PA_SYSMMU_FIMC1 0x11A30000
@ -103,6 +107,12 @@
#define EXYNOS4_PA_SYSMMU_JPEG 0x11A60000
#define EXYNOS4_PA_SYSMMU_FIMD0 0x11E20000
#define EXYNOS4_PA_SYSMMU_FIMD1 0x12220000
#define EXYNOS4_PA_SYSMMU_FIMC_ISP 0x12260000
#define EXYNOS4_PA_SYSMMU_FIMC_DRC 0x12270000
#define EXYNOS4_PA_SYSMMU_FIMC_FD 0x122A0000
#define EXYNOS4_PA_SYSMMU_ISPCPU 0x122B0000
#define EXYNOS4_PA_SYSMMU_FIMC_LITE0 0x123B0000
#define EXYNOS4_PA_SYSMMU_FIMC_LITE1 0x123C0000
#define EXYNOS4_PA_SYSMMU_PCIe 0x12620000
#define EXYNOS4_PA_SYSMMU_G2D 0x12A20000
#define EXYNOS4_PA_SYSMMU_ROTATOR 0x12A30000
@ -110,6 +120,37 @@
#define EXYNOS4_PA_SYSMMU_TV 0x12E20000
#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000
#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000
#define EXYNOS5_PA_SYSMMU_MDMA1 0x10A40000
#define EXYNOS5_PA_SYSMMU_SSS 0x10A50000
#define EXYNOS5_PA_SYSMMU_2D 0x10A60000
#define EXYNOS5_PA_SYSMMU_MFC_L 0x11200000
#define EXYNOS5_PA_SYSMMU_MFC_R 0x11210000
#define EXYNOS5_PA_SYSMMU_ROTATOR 0x11D40000
#define EXYNOS5_PA_SYSMMU_MDMA2 0x11D50000
#define EXYNOS5_PA_SYSMMU_JPEG 0x11F20000
#define EXYNOS5_PA_SYSMMU_IOP 0x12360000
#define EXYNOS5_PA_SYSMMU_RTIC 0x12370000
#define EXYNOS5_PA_SYSMMU_GPS 0x12630000
#define EXYNOS5_PA_SYSMMU_ISP 0x13260000
#define EXYNOS5_PA_SYSMMU_DRC 0x12370000
#define EXYNOS5_PA_SYSMMU_SCALERC 0x13280000
#define EXYNOS5_PA_SYSMMU_SCALERP 0x13290000
#define EXYNOS5_PA_SYSMMU_FD 0x132A0000
#define EXYNOS5_PA_SYSMMU_ISPCPU 0x132B0000
#define EXYNOS5_PA_SYSMMU_ODC 0x132C0000
#define EXYNOS5_PA_SYSMMU_DIS0 0x132D0000
#define EXYNOS5_PA_SYSMMU_DIS1 0x132E0000
#define EXYNOS5_PA_SYSMMU_3DNR 0x132F0000
#define EXYNOS5_PA_SYSMMU_LITE0 0x13C40000
#define EXYNOS5_PA_SYSMMU_LITE1 0x13C50000
#define EXYNOS5_PA_SYSMMU_GSC0 0x13E80000
#define EXYNOS5_PA_SYSMMU_GSC1 0x13E90000
#define EXYNOS5_PA_SYSMMU_GSC2 0x13EA0000
#define EXYNOS5_PA_SYSMMU_GSC3 0x13EB0000
#define EXYNOS5_PA_SYSMMU_FIMD1 0x14640000
#define EXYNOS5_PA_SYSMMU_TV 0x14650000
#define EXYNOS4_PA_SPI0 0x13920000
#define EXYNOS4_PA_SPI1 0x13930000
#define EXYNOS4_PA_SPI2 0x13940000

2
arch/arm/mach-exynos/include/mach/pm-core.h
View File

@ -33,7 +33,7 @@ static inline void s3c_pm_arch_prepare_irqs(void)
__raw_writel(tmp, S5P_WAKEUP_MASK);
__raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK);
__raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
__raw_writel(s3c_irqwake_eintmask & 0xFFFFFFFE, S5P_EINT_WAKEUP_MASK);
}
static inline void s3c_pm_arch_stop_clocks(void)

4
arch/arm/mach-exynos/include/mach/pmu.h
View File

@ -23,12 +23,12 @@ enum sys_powerdown {
};
extern unsigned long l2x0_regs_phys;
struct exynos4_pmu_conf {
struct exynos_pmu_conf {
void __iomem *reg;
unsigned int val[NUM_SYS_POWERDOWN];
};
extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
extern void s3c_cpu_resume(void);
#endif /* __ASM_ARCH_PMU_H */

25
arch/arm/mach-exynos/include/mach/regs-clock.h
View File

@ -135,6 +135,9 @@
#define EXYNOS4_CLKGATE_SCLKCPU EXYNOS_CLKREG(0x14800)
#define EXYNOS4_CLKGATE_IP_CPU EXYNOS_CLKREG(0x14900)
#define EXYNOS4_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x18800)
#define EXYNOS4_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x18804)
#define EXYNOS4_APLL_LOCKTIME (0x1C20) /* 300us */
#define EXYNOS4_APLLCON0_ENABLE_SHIFT (31)
@ -271,41 +274,59 @@
#define EXYNOS5_CLKDIV_ACP EXYNOS_CLKREG(0x08500)
#define EXYNOS5_CLKSRC_TOP2 EXYNOS_CLKREG(0x10218)
#define EXYNOS5_EPLL_CON0 EXYNOS_CLKREG(0x10130)
#define EXYNOS5_EPLL_CON1 EXYNOS_CLKREG(0x10134)
#define EXYNOS5_EPLL_CON2 EXYNOS_CLKREG(0x10138)
#define EXYNOS5_VPLL_CON0 EXYNOS_CLKREG(0x10140)
#define EXYNOS5_VPLL_CON1 EXYNOS_CLKREG(0x10144)
#define EXYNOS5_VPLL_CON2 EXYNOS_CLKREG(0x10148)
#define EXYNOS5_CPLL_CON0 EXYNOS_CLKREG(0x10120)
#define EXYNOS5_CLKSRC_TOP0 EXYNOS_CLKREG(0x10210)
#define EXYNOS5_CLKSRC_TOP1 EXYNOS_CLKREG(0x10214)
#define EXYNOS5_CLKSRC_TOP2 EXYNOS_CLKREG(0x10218)
#define EXYNOS5_CLKSRC_TOP3 EXYNOS_CLKREG(0x1021C)
#define EXYNOS5_CLKSRC_GSCL EXYNOS_CLKREG(0x10220)
#define EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C)
#define EXYNOS5_CLKSRC_MAUDIO EXYNOS_CLKREG(0x10240)
#define EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244)
#define EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250)
#define EXYNOS5_CLKSRC_PERIC1 EXYNOS_CLKREG(0x10254)
#define EXYNOS5_SCLK_SRC_ISP EXYNOS_CLKREG(0x10270)
#define EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310)
#define EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320)
#define EXYNOS5_CLKSRC_MASK_DISP1_0 EXYNOS_CLKREG(0x1032C)
#define EXYNOS5_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x10334)
#define EXYNOS5_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x10340)
#define EXYNOS5_CLKSRC_MASK_PERIC0 EXYNOS_CLKREG(0x10350)
#define EXYNOS5_CLKSRC_MASK_PERIC1 EXYNOS_CLKREG(0x10354)
#define EXYNOS5_CLKDIV_TOP0 EXYNOS_CLKREG(0x10510)
#define EXYNOS5_CLKDIV_TOP1 EXYNOS_CLKREG(0x10514)
#define EXYNOS5_CLKDIV_GSCL EXYNOS_CLKREG(0x10520)
#define EXYNOS5_CLKDIV_DISP1_0 EXYNOS_CLKREG(0x1052C)
#define EXYNOS5_CLKDIV_GEN EXYNOS_CLKREG(0x1053C)
#define EXYNOS5_CLKDIV_MAUDIO EXYNOS_CLKREG(0x10544)
#define EXYNOS5_CLKDIV_FSYS0 EXYNOS_CLKREG(0x10548)
#define EXYNOS5_CLKDIV_FSYS1 EXYNOS_CLKREG(0x1054C)
#define EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550)
#define EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554)
#define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558)
#define EXYNOS5_CLKDIV_PERIC1 EXYNOS_CLKREG(0x1055C)
#define EXYNOS5_CLKDIV_PERIC2 EXYNOS_CLKREG(0x10560)
#define EXYNOS5_CLKDIV_PERIC3 EXYNOS_CLKREG(0x10564)
#define EXYNOS5_CLKDIV_PERIC4 EXYNOS_CLKREG(0x10568)
#define EXYNOS5_CLKDIV_PERIC5 EXYNOS_CLKREG(0x1056C)
#define EXYNOS5_SCLK_DIV_ISP EXYNOS_CLKREG(0x10580)
#define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800)
#define EXYNOS5_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x0C800)
#define EXYNOS5_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x0C804)
#define EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920)
#define EXYNOS5_CLKGATE_IP_DISP1 EXYNOS_CLKREG(0x10928)
#define EXYNOS5_CLKGATE_IP_MFC EXYNOS_CLKREG(0x1092C)
#define EXYNOS5_CLKGATE_IP_G3D EXYNOS_CLKREG(0x10930)
#define EXYNOS5_CLKGATE_IP_GEN EXYNOS_CLKREG(0x10934)
#define EXYNOS5_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x10944)
#define EXYNOS5_CLKGATE_IP_GPS EXYNOS_CLKREG(0x1094C)
@ -317,6 +338,8 @@
#define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200)
#define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500)
#define EXYNOS5_PLL_DIV2_SEL EXYNOS_CLKREG(0x20A24)
#define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030)
#define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29)

151
arch/arm/mach-exynos/include/mach/regs-pmu.h
View File

@ -1,9 +1,8 @@
/* linux/arch/arm/mach-exynos4/include/mach/regs-pmu.h
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
/*
* Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS4 - Power management unit definition
* EXYNOS - Power management unit definition
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@ -177,7 +176,7 @@
#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0)
/* Only for EXYNOS4212 */
/* Only for EXYNOS4x12 */
#define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050)
#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054)
#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR S5P_PMUREG(0x1058)
@ -218,4 +217,146 @@
#define S5P_SECSS_MEM_OPTION S5P_PMUREG(0x2EC8)
#define S5P_ROTATOR_MEM_OPTION S5P_PMUREG(0x2F48)
/* Only for EXYNOS4412 */
#define S5P_ARM_CORE2_LOWPWR S5P_PMUREG(0x1020)
#define S5P_DIS_IRQ_CORE2 S5P_PMUREG(0x1024)
#define S5P_DIS_IRQ_CENTRAL2 S5P_PMUREG(0x1028)
#define S5P_ARM_CORE3_LOWPWR S5P_PMUREG(0x1030)
#define S5P_DIS_IRQ_CORE3 S5P_PMUREG(0x1034)
#define S5P_DIS_IRQ_CENTRAL3 S5P_PMUREG(0x1038)
/* For EXYNOS5 */
#define EXYNOS5_USB_CFG S5P_PMUREG(0x0230)
#define EXYNOS5_ARM_CORE0_SYS_PWR_REG S5P_PMUREG(0x1000)
#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1004)
#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1008)
#define EXYNOS5_ARM_CORE1_SYS_PWR_REG S5P_PMUREG(0x1010)
#define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1014)
#define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1018)
#define EXYNOS5_FSYS_ARM_SYS_PWR_REG S5P_PMUREG(0x1040)
#define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1048)
#define EXYNOS5_ISP_ARM_SYS_PWR_REG S5P_PMUREG(0x1050)
#define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1054)
#define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1058)
#define EXYNOS5_ARM_COMMON_SYS_PWR_REG S5P_PMUREG(0x1080)
#define EXYNOS5_ARM_L2_SYS_PWR_REG S5P_PMUREG(0x10C0)
#define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1100)
#define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1104)
#define EXYNOS5_CMU_RESET_SYS_PWR_REG S5P_PMUREG(0x110C)
#define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1120)
#define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1124)
#define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x112C)
#define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG S5P_PMUREG(0x1130)
#define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG S5P_PMUREG(0x1134)
#define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG S5P_PMUREG(0x1138)
#define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1140)
#define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1144)
#define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1148)
#define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x114C)
#define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1150)
#define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1154)
#define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1164)
#define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1170)
#define EXYNOS5_TOP_BUS_SYS_PWR_REG S5P_PMUREG(0x1180)
#define EXYNOS5_TOP_RETENTION_SYS_PWR_REG S5P_PMUREG(0x1184)
#define EXYNOS5_TOP_PWR_SYS_PWR_REG S5P_PMUREG(0x1188)
#define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1190)
#define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1194)
#define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1198)
#define EXYNOS5_LOGIC_RESET_SYS_PWR_REG S5P_PMUREG(0x11A0)
#define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG S5P_PMUREG(0x11A4)
#define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B0)
#define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B4)
#define EXYNOS5_USBOTG_MEM_SYS_PWR_REG S5P_PMUREG(0x11C0)
#define EXYNOS5_G2D_MEM_SYS_PWR_REG S5P_PMUREG(0x11C8)
#define EXYNOS5_USBDRD_MEM_SYS_PWR_REG S5P_PMUREG(0x11CC)
#define EXYNOS5_SDMMC_MEM_SYS_PWR_REG S5P_PMUREG(0x11D0)
#define EXYNOS5_CSSYS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D4)
#define EXYNOS5_SECSS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D8)
#define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG S5P_PMUREG(0x11DC)
#define EXYNOS5_INTRAM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E0)
#define EXYNOS5_INTROM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E4)
#define EXYNOS5_JPEG_MEM_SYS_PWR_REG S5P_PMUREG(0x11E8)
#define EXYNOS5_HSI_MEM_SYS_PWR_REG S5P_PMUREG(0x11EC)
#define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG S5P_PMUREG(0x11F4)
#define EXYNOS5_SATA_MEM_SYS_PWR_REG S5P_PMUREG(0x11FC)
#define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG S5P_PMUREG(0x1200)
#define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG S5P_PMUREG(0x1204)
#define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG S5P_PMUREG(0x1208)
#define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG S5P_PMUREG(0x1220)
#define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG S5P_PMUREG(0x1224)
#define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG S5P_PMUREG(0x1228)
#define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG S5P_PMUREG(0x122C)
#define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG S5P_PMUREG(0x1230)
#define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG S5P_PMUREG(0x1234)
#define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG S5P_PMUREG(0x1238)
#define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x123C)
#define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1240)
#define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1250)
#define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG S5P_PMUREG(0x1260)
#define EXYNOS5_XUSBXTI_SYS_PWR_REG S5P_PMUREG(0x1280)
#define EXYNOS5_XXTI_SYS_PWR_REG S5P_PMUREG(0x1284)
#define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG S5P_PMUREG(0x12C0)
#define EXYNOS5_GPIO_MODE_SYS_PWR_REG S5P_PMUREG(0x1300)
#define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1320)
#define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG S5P_PMUREG(0x1340)
#define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG S5P_PMUREG(0x1344)
#define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1348)
#define EXYNOS5_GSCL_SYS_PWR_REG S5P_PMUREG(0x1400)
#define EXYNOS5_ISP_SYS_PWR_REG S5P_PMUREG(0x1404)
#define EXYNOS5_MFC_SYS_PWR_REG S5P_PMUREG(0x1408)
#define EXYNOS5_G3D_SYS_PWR_REG S5P_PMUREG(0x140C)
#define EXYNOS5_DISP1_SYS_PWR_REG S5P_PMUREG(0x1414)
#define EXYNOS5_MAU_SYS_PWR_REG S5P_PMUREG(0x1418)
#define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG S5P_PMUREG(0x1480)
#define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG S5P_PMUREG(0x1484)
#define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG S5P_PMUREG(0x1488)
#define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG S5P_PMUREG(0x148C)
#define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG S5P_PMUREG(0x1494)
#define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG S5P_PMUREG(0x1498)
#define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG S5P_PMUREG(0x14C0)
#define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG S5P_PMUREG(0x14C4)
#define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG S5P_PMUREG(0x14C8)
#define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG S5P_PMUREG(0x14CC)
#define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG S5P_PMUREG(0x14D4)
#define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG S5P_PMUREG(0x14D8)
#define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG S5P_PMUREG(0x1580)
#define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG S5P_PMUREG(0x1584)
#define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG S5P_PMUREG(0x1588)
#define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG S5P_PMUREG(0x158C)
#define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG S5P_PMUREG(0x1594)
#define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG S5P_PMUREG(0x1598)
#define EXYNOS5_ARM_CORE0_OPTION S5P_PMUREG(0x2008)
#define EXYNOS5_ARM_CORE1_OPTION S5P_PMUREG(0x2088)
#define EXYNOS5_FSYS_ARM_OPTION S5P_PMUREG(0x2208)
#define EXYNOS5_ISP_ARM_OPTION S5P_PMUREG(0x2288)
#define EXYNOS5_ARM_COMMON_OPTION S5P_PMUREG(0x2408)
#define EXYNOS5_TOP_PWR_OPTION S5P_PMUREG(0x2C48)
#define EXYNOS5_TOP_PWR_SYSMEM_OPTION S5P_PMUREG(0x2CC8)
#define EXYNOS5_JPEG_MEM_OPTION S5P_PMUREG(0x2F48)
#define EXYNOS5_GSCL_STATUS S5P_PMUREG(0x4004)
#define EXYNOS5_ISP_STATUS S5P_PMUREG(0x4024)
#define EXYNOS5_GSCL_OPTION S5P_PMUREG(0x4008)
#define EXYNOS5_ISP_OPTION S5P_PMUREG(0x4028)
#define EXYNOS5_MFC_OPTION S5P_PMUREG(0x4048)
#define EXYNOS5_G3D_CONFIGURATION S5P_PMUREG(0x4060)
#define EXYNOS5_G3D_STATUS S5P_PMUREG(0x4064)
#define EXYNOS5_G3D_OPTION S5P_PMUREG(0x4068)
#define EXYNOS5_DISP1_OPTION S5P_PMUREG(0x40A8)
#define EXYNOS5_MAU_OPTION S5P_PMUREG(0x40C8)
#define EXYNOS5_USE_SC_FEEDBACK (1 << 1)
#define EXYNOS5_USE_SC_COUNTER (1 << 0)
#define EXYNOS5_MANUAL_L2RSTDISABLE_CONTROL (1 << 2)
#define EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN (1 << 7)
#define EXYNOS5_OPTION_USE_STANDBYWFE (1 << 24)
#define EXYNOS5_OPTION_USE_STANDBYWFI (1 << 16)
#define EXYNOS5_OPTION_USE_RETENTION (1 << 4)
#endif /* __ASM_ARCH_REGS_PMU_H */

28
arch/arm/mach-exynos/include/mach/regs-sysmmu.h
View File

@ -1,28 +0,0 @@
/* linux/arch/arm/mach-exynos4/include/mach/regs-sysmmu.h
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS4 - System MMU register
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_REGS_SYSMMU_H
#define __ASM_ARCH_REGS_SYSMMU_H __FILE__
#define S5P_MMU_CTRL 0x000
#define S5P_MMU_CFG 0x004
#define S5P_MMU_STATUS 0x008
#define S5P_MMU_FLUSH 0x00C
#define S5P_PT_BASE_ADDR 0x014
#define S5P_INT_STATUS 0x018
#define S5P_INT_CLEAR 0x01C
#define S5P_PAGE_FAULT_ADDR 0x024
#define S5P_AW_FAULT_ADDR 0x028
#define S5P_AR_FAULT_ADDR 0x02C
#define S5P_DEFAULT_SLAVE_ADDR 0x030
#endif /* __ASM_ARCH_REGS_SYSMMU_H */

2
arch/arm/mach-exynos/include/mach/spi-clocks.h
View File

@ -11,6 +11,6 @@
#define __ASM_ARCH_SPI_CLKS_H __FILE__
/* Must source from SCLK_SPI */
#define EXYNOS4_SPI_SRCCLK_SCLK 0
#define EXYNOS_SPI_SRCCLK_SCLK 0
#endif /* __ASM_ARCH_SPI_CLKS_H */

84
arch/arm/mach-exynos/include/mach/sysmmu.h
View File

@ -1,46 +1,66 @@
/* linux/arch/arm/mach-exynos4/include/mach/sysmmu.h
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
/*
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Samsung sysmmu driver for EXYNOS4
* EXYNOS - System MMU support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
*/
#ifndef __ASM_ARM_ARCH_SYSMMU_H
#define __ASM_ARM_ARCH_SYSMMU_H __FILE__
#ifndef _ARM_MACH_EXYNOS_SYSMMU_H_
#define _ARM_MACH_EXYNOS_SYSMMU_H_
enum exynos4_sysmmu_ips {
SYSMMU_MDMA,
SYSMMU_SSS,
SYSMMU_FIMC0,
SYSMMU_FIMC1,
SYSMMU_FIMC2,
SYSMMU_FIMC3,
SYSMMU_JPEG,
SYSMMU_FIMD0,
SYSMMU_FIMD1,
SYSMMU_PCIe,
SYSMMU_G2D,
SYSMMU_ROTATOR,
SYSMMU_MDMA2,
SYSMMU_TV,
SYSMMU_MFC_L,
SYSMMU_MFC_R,
EXYNOS4_SYSMMU_TOTAL_IPNUM,
struct sysmmu_platform_data {
char *dbgname;
/* comma(,) separated list of clock names for clock gating */
char *clockname;
};
#define S5P_SYSMMU_TOTAL_IPNUM EXYNOS4_SYSMMU_TOTAL_IPNUM
#define SYSMMU_DEVNAME_BASE "exynos-sysmmu"
extern const char *sysmmu_ips_name[EXYNOS4_SYSMMU_TOTAL_IPNUM];
#define SYSMMU_CLOCK_NAME "sysmmu"
#define SYSMMU_CLOCK_NAME2 "sysmmu_mc"
typedef enum exynos4_sysmmu_ips sysmmu_ips;
#ifdef CONFIG_EXYNOS_DEV_SYSMMU
#include <linux/device.h>
struct platform_device;
void sysmmu_clk_init(struct device *dev, sysmmu_ips ips);
void sysmmu_clk_enable(sysmmu_ips ips);
void sysmmu_clk_disable(sysmmu_ips ips);
#define SYSMMU_PLATDEV(ipname) exynos_device_sysmmu_##ipname
#endif /* __ASM_ARM_ARCH_SYSMMU_H */
extern struct platform_device SYSMMU_PLATDEV(mfc_l);
extern struct platform_device SYSMMU_PLATDEV(mfc_r);
extern struct platform_device SYSMMU_PLATDEV(tv);
extern struct platform_device SYSMMU_PLATDEV(jpeg);
extern struct platform_device SYSMMU_PLATDEV(rot);
extern struct platform_device SYSMMU_PLATDEV(fimc0);
extern struct platform_device SYSMMU_PLATDEV(fimc1);
extern struct platform_device SYSMMU_PLATDEV(fimc2);
extern struct platform_device SYSMMU_PLATDEV(fimc3);
extern struct platform_device SYSMMU_PLATDEV(gsc0);
extern struct platform_device SYSMMU_PLATDEV(gsc1);
extern struct platform_device SYSMMU_PLATDEV(gsc2);
extern struct platform_device SYSMMU_PLATDEV(gsc3);
extern struct platform_device SYSMMU_PLATDEV(isp);
extern struct platform_device SYSMMU_PLATDEV(fimd0);
extern struct platform_device SYSMMU_PLATDEV(fimd1);
extern struct platform_device SYSMMU_PLATDEV(camif0);
extern struct platform_device SYSMMU_PLATDEV(camif1);
extern struct platform_device SYSMMU_PLATDEV(2d);
#ifdef CONFIG_IOMMU_API
static inline void platform_set_sysmmu(
struct device *sysmmu, struct device *dev)
{
dev->archdata.iommu = sysmmu;
}
#endif
#else /* !CONFIG_EXYNOS_DEV_SYSMMU */
#define platform_set_sysmmu(dev, sysmmu) do { } while (0)
#endif
#define SYSMMU_CLOCK_DEVNAME(ipname, id) (SYSMMU_DEVNAME_BASE "." #id)
#endif /* _ARM_MACH_EXYNOS_SYSMMU_H_ */

1
arch/arm/mach-exynos/mach-armlex4210.c
View File

@ -157,7 +157,6 @@ static struct platform_device *armlex4210_devices[] __initdata = {
&s3c_device_hsmmc3,
&s3c_device_rtc,
&s3c_device_wdt,
&exynos4_device_sysmmu,
&samsung_asoc_dma,
&armlex4210_smsc911x,
&exynos4_device_ahci,

4
arch/arm/mach-exynos/mach-exynos5-dt.c
View File

@ -43,6 +43,10 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
"exynos4210-uart.2", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
"exynos4210-uart.3", NULL),
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0),
"s3c2440-i2c.0", NULL),
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
"s3c2440-i2c.1", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),

1
arch/arm/mach-exynos/mach-smdkv310.c
View File

@ -281,7 +281,6 @@ static struct platform_device *smdkv310_devices[] __initdata = {
&s5p_device_mfc_l,
&s5p_device_mfc_r,
&exynos4_device_spdif,
&exynos4_device_sysmmu,
&samsung_asoc_dma,
&samsung_asoc_idma,
&s5p_device_fimd0,

17
arch/arm/mach-exynos/mct.c
View File

@ -388,6 +388,7 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
{
struct mct_clock_event_device *mevt;
unsigned int cpu = smp_processor_id();
int mct_lx_irq;
mevt = this_cpu_ptr(&percpu_mct_tick);
mevt->evt = evt;
@ -414,14 +415,18 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
if (mct_int_type == MCT_INT_SPI) {
if (cpu == 0) {
mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L0 :
EXYNOS5_IRQ_MCT_L0;
mct_tick0_event_irq.dev_id = mevt;
evt->irq = EXYNOS4_IRQ_MCT_L0;
setup_irq(EXYNOS4_IRQ_MCT_L0, &mct_tick0_event_irq);
evt->irq = mct_lx_irq;
setup_irq(mct_lx_irq, &mct_tick0_event_irq);
} else {
mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L1 :
EXYNOS5_IRQ_MCT_L1;
mct_tick1_event_irq.dev_id = mevt;
evt->irq = EXYNOS4_IRQ_MCT_L1;
setup_irq(EXYNOS4_IRQ_MCT_L1, &mct_tick1_event_irq);
irq_set_affinity(EXYNOS4_IRQ_MCT_L1, cpumask_of(1));
evt->irq = mct_lx_irq;
setup_irq(mct_lx_irq, &mct_tick1_event_irq);
irq_set_affinity(mct_lx_irq, cpumask_of(1));
}
} else {
enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);
@ -473,7 +478,7 @@ static void __init exynos4_timer_resources(void)
static void __init exynos4_timer_init(void)
{
if (soc_is_exynos4210())
if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
mct_int_type = MCT_INT_SPI;
else
mct_int_type = MCT_INT_PPI;

225
arch/arm/mach-exynos/pm.c
View File

@ -1,9 +1,8 @@
/* linux/arch/arm/mach-exynos4/pm.c
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
/*
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS4210 - Power Management support
* EXYNOS - Power Management support
*
* Based on arch/arm/mach-s3c2410/pm.c
* Copyright (c) 2006 Simtec Electronics
@ -63,90 +62,7 @@ static struct sleep_save exynos4_vpll_save[] = {
SAVE_ITEM(EXYNOS4_VPLL_CON1),
};
static struct sleep_save exynos4_core_save[] = {
/* GIC side */
SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
SAVE_ITEM(S5P_VA_GIC_CPU + 0x008),
SAVE_ITEM(S5P_VA_GIC_CPU + 0x00C),
SAVE_ITEM(S5P_VA_GIC_CPU + 0x014),
SAVE_ITEM(S5P_VA_GIC_CPU + 0x018),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x000),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x004),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x100),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x104),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x108),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x300),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x304),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x308),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x400),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x404),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x408),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x40C),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x410),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x414),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x418),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x41C),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x420),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x424),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x428),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x42C),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x430),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x434),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x438),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x43C),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x440),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x444),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x448),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x44C),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x450),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x454),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x458),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x45C),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x800),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x804),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x808),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x80C),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x810),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x814),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x818),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x81C),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x820),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x824),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x828),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x82C),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x830),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x834),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x838),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x83C),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x840),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x844),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x848),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x84C),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x850),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x854),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x858),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x85C),
SAVE_ITEM(S5P_VA_GIC_DIST + 0xC00),
SAVE_ITEM(S5P_VA_GIC_DIST + 0xC04),
SAVE_ITEM(S5P_VA_GIC_DIST + 0xC08),
SAVE_ITEM(S5P_VA_GIC_DIST + 0xC0C),
SAVE_ITEM(S5P_VA_GIC_DIST + 0xC10),
SAVE_ITEM(S5P_VA_GIC_DIST + 0xC14),
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x000),
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x010),
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x020),
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x030),
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x040),
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x050),
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x060),
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070),
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080),
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090),
static struct sleep_save exynos_core_save[] = {
/* SROM side */
SAVE_ITEM(S5P_SROM_BW),
SAVE_ITEM(S5P_SROM_BC0),
@ -159,9 +75,11 @@ static struct sleep_save exynos4_core_save[] = {
/* For Cortex-A9 Diagnostic and Power control register */
static unsigned int save_arm_register[2];
static int exynos4_cpu_suspend(unsigned long arg)
static int exynos_cpu_suspend(unsigned long arg)
{
#ifdef CONFIG_CACHE_L2X0
outer_flush_all();
#endif
/* issue the standby signal into the pm unit. */
cpu_do_idle();
@ -170,19 +88,25 @@ static int exynos4_cpu_suspend(unsigned long arg)
panic("sleep resumed to originator?");
}
static void exynos4_pm_prepare(void)
static void exynos_pm_prepare(void)
{
u32 tmp;
unsigned int tmp;
s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
tmp = __raw_readl(S5P_INFORM1);
if (!soc_is_exynos5250()) {
s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
} else {
/* Disable USE_RETENTION of JPEG_MEM_OPTION */
tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
__raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
}
/* Set value of power down register for sleep mode */
exynos4_sys_powerdown_conf(SYS_SLEEP);
exynos_sys_powerdown_conf(SYS_SLEEP);
__raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
/* ensure at least INFORM0 has the resume address */
@ -191,17 +115,18 @@ static void exynos4_pm_prepare(void)
/* Before enter central sequence mode, clock src register have to set */
s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
if (!soc_is_exynos5250())
s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
if (soc_is_exynos4210())
s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
}
static int exynos4_pm_add(struct device *dev, struct subsys_interface *sif)
static int exynos_pm_add(struct device *dev, struct subsys_interface *sif)
{
pm_cpu_prep = exynos4_pm_prepare;
pm_cpu_sleep = exynos4_cpu_suspend;
pm_cpu_prep = exynos_pm_prepare;
pm_cpu_sleep = exynos_cpu_suspend;
return 0;
}
@ -273,13 +198,13 @@ static void exynos4_restore_pll(void)
} while (epll_wait || vpll_wait);
}
static struct subsys_interface exynos4_pm_interface = {
.name = "exynos4_pm",
.subsys = &exynos4_subsys,
.add_dev = exynos4_pm_add,
static struct subsys_interface exynos_pm_interface = {
.name = "exynos_pm",
.subsys = &exynos_subsys,
.add_dev = exynos_pm_add,
};
static __init int exynos4_pm_drvinit(void)
static __init int exynos_pm_drvinit(void)
{
struct clk *pll_base;
unsigned int tmp;
@ -292,18 +217,20 @@ static __init int exynos4_pm_drvinit(void)
tmp |= ((0xFF << 8) | (0x1F << 1));
__raw_writel(tmp, S5P_WAKEUP_MASK);
pll_base = clk_get(NULL, "xtal");
if (!soc_is_exynos5250()) {
pll_base = clk_get(NULL, "xtal");
if (!IS_ERR(pll_base)) {
pll_base_rate = clk_get_rate(pll_base);
clk_put(pll_base);
if (!IS_ERR(pll_base)) {
pll_base_rate = clk_get_rate(pll_base);
clk_put(pll_base);
}
}
return subsys_interface_register(&exynos4_pm_interface);
return subsys_interface_register(&exynos_pm_interface);
}
arch_initcall(exynos4_pm_drvinit);
arch_initcall(exynos_pm_drvinit);
static int exynos4_pm_suspend(void)
static int exynos_pm_suspend(void)
{
unsigned long tmp;
@ -313,27 +240,27 @@ static int exynos4_pm_suspend(void)
tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
if (soc_is_exynos4212()) {
tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
tmp &= ~(S5P_USE_STANDBYWFI_ISP_ARM |
S5P_USE_STANDBYWFE_ISP_ARM);
__raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
/* Setting SEQ_OPTION register */
tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
__raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
if (!soc_is_exynos5250()) {
/* Save Power control register */
asm ("mrc p15, 0, %0, c15, c0, 0"
: "=r" (tmp) : : "cc");
save_arm_register[0] = tmp;
/* Save Diagnostic register */
asm ("mrc p15, 0, %0, c15, c0, 1"
: "=r" (tmp) : : "cc");
save_arm_register[1] = tmp;
}
/* Save Power control register */
asm ("mrc p15, 0, %0, c15, c0, 0"
: "=r" (tmp) : : "cc");
save_arm_register[0] = tmp;
/* Save Diagnostic register */
asm ("mrc p15, 0, %0, c15, c0, 1"
: "=r" (tmp) : : "cc");
save_arm_register[1] = tmp;
return 0;
}
static void exynos4_pm_resume(void)
static void exynos_pm_resume(void)
{
unsigned long tmp;
@ -350,17 +277,19 @@ static void exynos4_pm_resume(void)
/* No need to perform below restore code */
goto early_wakeup;
}
/* Restore Power control register */
tmp = save_arm_register[0];
asm volatile ("mcr p15, 0, %0, c15, c0, 0"
: : "r" (tmp)
: "cc");
if (!soc_is_exynos5250()) {
/* Restore Power control register */
tmp = save_arm_register[0];
asm volatile ("mcr p15, 0, %0, c15, c0, 0"
: : "r" (tmp)
: "cc");
/* Restore Diagnostic register */
tmp = save_arm_register[1];
asm volatile ("mcr p15, 0, %0, c15, c0, 1"
: : "r" (tmp)
: "cc");
/* Restore Diagnostic register */
tmp = save_arm_register[1];
asm volatile ("mcr p15, 0, %0, c15, c0, 1"
: : "r" (tmp)
: "cc");
}
/* For release retention */
@ -372,26 +301,28 @@ static void exynos4_pm_resume(void)
__raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
exynos4_restore_pll();
if (!soc_is_exynos5250()) {
exynos4_restore_pll();
#ifdef CONFIG_SMP
scu_enable(S5P_VA_SCU);
scu_enable(S5P_VA_SCU);
#endif
}
early_wakeup:
return;
}
static struct syscore_ops exynos4_pm_syscore_ops = {
.suspend = exynos4_pm_suspend,
.resume = exynos4_pm_resume,
static struct syscore_ops exynos_pm_syscore_ops = {
.suspend = exynos_pm_suspend,
.resume = exynos_pm_resume,
};
static __init int exynos4_pm_syscore_init(void)
static __init int exynos_pm_syscore_init(void)
{
register_syscore_ops(&exynos4_pm_syscore_ops);
register_syscore_ops(&exynos_pm_syscore_ops);
return 0;
}
arch_initcall(exynos4_pm_syscore_init);
arch_initcall(exynos_pm_syscore_init);

218
arch/arm/mach-exynos/pmu.c
View File

@ -1,9 +1,8 @@
/* linux/arch/arm/mach-exynos4/pmu.c
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
/*
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* EXYNOS4210 - CPU PMU(Power Management Unit) support
* EXYNOS - CPU PMU(Power Management Unit) support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@ -12,13 +11,14 @@
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/bug.h>
#include <mach/regs-clock.h>
#include <mach/pmu.h>
static struct exynos4_pmu_conf *exynos4_pmu_config;
static struct exynos_pmu_conf *exynos_pmu_config;
static struct exynos4_pmu_conf exynos4210_pmu_config[] = {
static struct exynos_pmu_conf exynos4210_pmu_config[] = {
/* { .reg = address, .val = { AFTR, LPA, SLEEP } */
{ S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
{ S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
@ -94,7 +94,7 @@ static struct exynos4_pmu_conf exynos4210_pmu_config[] = {
{ PMU_TABLE_END,},
};
static struct exynos4_pmu_conf exynos4212_pmu_config[] = {
static struct exynos_pmu_conf exynos4x12_pmu_config[] = {
{ S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
{ S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
{ S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
@ -202,29 +202,209 @@ static struct exynos4_pmu_conf exynos4212_pmu_config[] = {
{ PMU_TABLE_END,},
};
void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
static struct exynos_pmu_conf exynos4412_pmu_config[] = {
{ S5P_ARM_CORE2_LOWPWR, { 0x0, 0x0, 0x2 } },
{ S5P_DIS_IRQ_CORE2, { 0x0, 0x0, 0x0 } },
{ S5P_DIS_IRQ_CENTRAL2, { 0x0, 0x0, 0x0 } },
{ S5P_ARM_CORE3_LOWPWR, { 0x0, 0x0, 0x2 } },
{ S5P_DIS_IRQ_CORE3, { 0x0, 0x0, 0x0 } },
{ S5P_DIS_IRQ_CENTRAL3, { 0x0, 0x0, 0x0 } },
{ PMU_TABLE_END,},
};
static struct exynos_pmu_conf exynos5250_pmu_config[] = {
/* { .reg = address, .val = { AFTR, LPA, SLEEP } */
{ EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
{ EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
{ EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
{ EXYNOS5_ARM_CORE1_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
{ EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
{ EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
{ EXYNOS5_FSYS_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
{ EXYNOS5_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
{ EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
{ EXYNOS5_ARM_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
{ EXYNOS5_ARM_L2_SYS_PWR_REG, { 0x3, 0x3, 0x3} },
{ EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
{ EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
{ EXYNOS5_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
{ EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
{ EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
{ EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
{ EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
{ EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
{ EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
{ EXYNOS5_APLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
{ EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_TOP_BUS_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
{ EXYNOS5_TOP_RETENTION_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
{ EXYNOS5_TOP_PWR_SYS_PWR_REG, { 0x3, 0x0, 0x3} },
{ EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
{ EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
{ EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x3} },
{ EXYNOS5_LOGIC_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
{ EXYNOS5_OSCCLK_GATE_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
{ EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
{ EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
{ EXYNOS5_USBOTG_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
{ EXYNOS5_G2D_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
{ EXYNOS5_USBDRD_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
{ EXYNOS5_SDMMC_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
{ EXYNOS5_CSSYS_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
{ EXYNOS5_SECSS_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
{ EXYNOS5_ROTATOR_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
{ EXYNOS5_INTRAM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
{ EXYNOS5_INTROM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
{ EXYNOS5_JPEG_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
{ EXYNOS5_HSI_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
{ EXYNOS5_MCUIOP_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
{ EXYNOS5_SATA_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
{ EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
{ EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_PAD_ISOLATION_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_XUSBXTI_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
{ EXYNOS5_XXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
{ EXYNOS5_EXT_REGULATOR_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
{ EXYNOS5_GPIO_MODE_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
{ EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
{ EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
{ EXYNOS5_GSCL_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
{ EXYNOS5_ISP_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
{ EXYNOS5_MFC_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
{ EXYNOS5_G3D_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
{ EXYNOS5_DISP1_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
{ EXYNOS5_MAU_SYS_PWR_REG, { 0x7, 0x7, 0x0} },
{ EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
{ EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
{ EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
{ EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
{ PMU_TABLE_END,},
};
void __iomem *exynos5_list_both_cnt_feed[] = {
EXYNOS5_ARM_CORE0_OPTION,
EXYNOS5_ARM_CORE1_OPTION,
EXYNOS5_ARM_COMMON_OPTION,
EXYNOS5_GSCL_OPTION,
EXYNOS5_ISP_OPTION,
EXYNOS5_MFC_OPTION,
EXYNOS5_G3D_OPTION,
EXYNOS5_DISP1_OPTION,
EXYNOS5_MAU_OPTION,
EXYNOS5_TOP_PWR_OPTION,
EXYNOS5_TOP_PWR_SYSMEM_OPTION,
};
void __iomem *exynos5_list_diable_wfi_wfe[] = {
EXYNOS5_ARM_CORE1_OPTION,
EXYNOS5_FSYS_ARM_OPTION,
EXYNOS5_ISP_ARM_OPTION,
};
static void exynos5_init_pmu(void)
{
unsigned int i;
unsigned int tmp;
/*
* Enable both SC_FEEDBACK and SC_COUNTER
*/
for (i = 0 ; i < ARRAY_SIZE(exynos5_list_both_cnt_feed) ; i++) {
tmp = __raw_readl(exynos5_list_both_cnt_feed[i]);
tmp |= (EXYNOS5_USE_SC_FEEDBACK |
EXYNOS5_USE_SC_COUNTER);
__raw_writel(tmp, exynos5_list_both_cnt_feed[i]);
}
/*
* SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable
* MANUAL_L2RSTDISABLE_CONTROL_BITFIELD Enable
*/
tmp = __raw_readl(EXYNOS5_ARM_COMMON_OPTION);
tmp |= (EXYNOS5_MANUAL_L2RSTDISABLE_CONTROL |
EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN);
__raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION);
/*
* Disable WFI/WFE on XXX_OPTION
*/
for (i = 0 ; i < ARRAY_SIZE(exynos5_list_diable_wfi_wfe) ; i++) {
tmp = __raw_readl(exynos5_list_diable_wfi_wfe[i]);
tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE |
EXYNOS5_OPTION_USE_STANDBYWFI);
__raw_writel(tmp, exynos5_list_diable_wfi_wfe[i]);
}
}
void exynos_sys_powerdown_conf(enum sys_powerdown mode)
{
unsigned int i;
for (i = 0; (exynos4_pmu_config[i].reg != PMU_TABLE_END) ; i++)
__raw_writel(exynos4_pmu_config[i].val[mode],
exynos4_pmu_config[i].reg);
if (soc_is_exynos5250())
exynos5_init_pmu();
for (i = 0; (exynos_pmu_config[i].reg != PMU_TABLE_END) ; i++)
__raw_writel(exynos_pmu_config[i].val[mode],
exynos_pmu_config[i].reg);
if (soc_is_exynos4412()) {
for (i = 0; exynos4412_pmu_config[i].reg != PMU_TABLE_END ; i++)
__raw_writel(exynos4412_pmu_config[i].val[mode],
exynos4412_pmu_config[i].reg);
}
}
static int __init exynos4_pmu_init(void)
static int __init exynos_pmu_init(void)
{
exynos4_pmu_config = exynos4210_pmu_config;
exynos_pmu_config = exynos4210_pmu_config;
if (soc_is_exynos4210()) {
exynos4_pmu_config = exynos4210_pmu_config;
exynos_pmu_config = exynos4210_pmu_config;
pr_info("EXYNOS4210 PMU Initialize\n");
} else if (soc_is_exynos4212()) {
exynos4_pmu_config = exynos4212_pmu_config;
pr_info("EXYNOS4212 PMU Initialize\n");
} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
exynos_pmu_config = exynos4x12_pmu_config;
pr_info("EXYNOS4x12 PMU Initialize\n");
} else if (soc_is_exynos5250()) {
exynos_pmu_config = exynos5250_pmu_config;
pr_info("EXYNOS5250 PMU Initialize\n");
} else {
pr_info("EXYNOS4: PMU not supported\n");
pr_info("EXYNOS: PMU not supported\n");
}
return 0;
}
arch_initcall(exynos4_pmu_init);
arch_initcall(exynos_pmu_init);

5
arch/arm/mach-s3c24xx/Kconfig
View File

@ -518,6 +518,11 @@ config S3C2443_DMA
help
Internal config node for S3C2443 DMA support
config S3C2443_SETUP_SPI
bool
help
Common setup code for SPI GPIO configurations
endif # CPU_S3C2443 || CPU_S3C2416
if CPU_S3C2443

1
arch/arm/mach-s3c24xx/Makefile
View File

@ -91,5 +91,6 @@ obj-$(CONFIG_MACH_OSIRIS_DVS) += mach-osiris-dvs.o
# device setup
obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
obj-$(CONFIG_S3C2443_SETUP_SPI) += setup-spi.o
obj-$(CONFIG_ARCH_S3C24XX) += setup-i2c.o
obj-$(CONFIG_S3C24XX_SETUP_TS) += setup-ts.o

1
arch/arm/mach-s3c24xx/clock-s3c2416.c
View File

@ -144,6 +144,7 @@ static struct clk_lookup s3c2416_clk_lookup[] = {
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &hsspi_mux.clk),
};
void __init s3c2416_init_clocks(int xtal)

6
arch/arm/mach-s3c24xx/clock-s3c2443.c
View File

@ -179,6 +179,11 @@ static struct clk *clks[] __initdata = {
&clk_hsmmc,
};
static struct clk_lookup s3c2443_clk_lookup[] = {
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_hsmmc),
CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_hsspi.clk),
};
void __init s3c2443_init_clocks(int xtal)
{
unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
@ -210,6 +215,7 @@ void __init s3c2443_init_clocks(int xtal)
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup));
s3c_pwmclk_init();
}

15
arch/arm/mach-s3c24xx/common-s3c2443.c
View File

@ -423,11 +423,6 @@ static struct clk init_clocks_off[] = {
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_IIS,
}, {
.name = "hsspi",
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_HSSPI,
}, {
.name = "adc",
.parent = &clk_p,
@ -562,6 +557,14 @@ static struct clk hsmmc1_clk = {
.ctrlbit = S3C2443_HCLKCON_HSMMC,
};
static struct clk hsspi_clk = {
.name = "spi",
.devname = "s3c64xx-spi.0",
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_HSSPI,
};
/* EPLLCON compatible enough to get on/off information */
void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll)
@ -612,6 +615,7 @@ static struct clk *clks[] __initdata = {
&clk_usb_bus,
&clk_armdiv,
&hsmmc1_clk,
&hsspi_clk,
};
static struct clksrc_clk *clksrcs[] __initdata = {
@ -629,6 +633,7 @@ static struct clk_lookup s3c2443_clk_lookup[] = {
CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk),
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk),
CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &hsspi_clk),
};
void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,

16
arch/arm/mach-s3c24xx/dma-s3c2443.c
View File

@ -55,12 +55,20 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
.name = "sdi",
.channels = MAP(S3C2443_DMAREQSEL_SDI),
},
[DMACH_SPI0] = {
.name = "spi0",
[DMACH_SPI0_RX] = {
.name = "spi0-rx",
.channels = MAP(S3C2443_DMAREQSEL_SPI0RX),
},
[DMACH_SPI0_TX] = {
.name = "spi0-tx",
.channels = MAP(S3C2443_DMAREQSEL_SPI0TX),
},
[DMACH_SPI1] = { /* only on S3C2443/S3C2450 */
.name = "spi1",
[DMACH_SPI1_RX] = { /* only on S3C2443/S3C2450 */
.name = "spi1-rx",
.channels = MAP(S3C2443_DMAREQSEL_SPI1RX),
},
[DMACH_SPI1_TX] = { /* only on S3C2443/S3C2450 */
.name = "spi1-tx",
.channels = MAP(S3C2443_DMAREQSEL_SPI1TX),
},
[DMACH_UART0] = {

4
arch/arm/mach-s3c24xx/include/mach/dma.h
View File

@ -47,6 +47,10 @@ enum dma_ch {
DMACH_UART2_SRC2,
DMACH_UART3, /* s3c2443 has extra uart */
DMACH_UART3_SRC2,
DMACH_SPI0_TX, /* s3c2443/2416/2450 hsspi0 */
DMACH_SPI0_RX, /* s3c2443/2416/2450 hsspi0 */
DMACH_SPI1_TX, /* s3c2443/2450 hsspi1 */
DMACH_SPI1_RX, /* s3c2443/2450 hsspi1 */
DMACH_MAX, /* the end entry */
};

15
arch/arm/mach-s3c24xx/include/mach/irqs.h
View File

@ -134,6 +134,17 @@
#define IRQ_S32416_WDT S3C2410_IRQSUB(27)
#define IRQ_S32416_AC97 S3C2410_IRQSUB(28)
/* second interrupt-register of s3c2416/s3c2450 */
#define S3C2416_IRQ(x) S3C2410_IRQ((x) + 54 + 29)
#define IRQ_S3C2416_2D S3C2416_IRQ(0)
#define IRQ_S3C2416_IIC1 S3C2416_IRQ(1)
#define IRQ_S3C2416_RESERVED2 S3C2416_IRQ(2)
#define IRQ_S3C2416_RESERVED3 S3C2416_IRQ(3)
#define IRQ_S3C2416_PCM0 S3C2416_IRQ(4)
#define IRQ_S3C2416_PCM1 S3C2416_IRQ(5)
#define IRQ_S3C2416_I2S0 S3C2416_IRQ(6)
#define IRQ_S3C2416_I2S1 S3C2416_IRQ(7)
/* extra irqs for s3c2440 */
@ -175,7 +186,9 @@
#define IRQ_S3C2443_WDT S3C2410_IRQSUB(27)
#define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28)
#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
#if defined(CONFIG_CPU_S3C2416)
#define NR_IRQS (IRQ_S3C2416_I2S1 + 1)
#elif defined(CONFIG_CPU_S3C2443)
#define NR_IRQS (IRQ_S3C2443_AC97+1)
#else
#define NR_IRQS (IRQ_S3C2440_AC97+1)

5
arch/arm/mach-s3c24xx/include/mach/map.h
View File

@ -98,6 +98,8 @@
/* SPI */
#define S3C2410_PA_SPI (0x59000000)
#define S3C2443_PA_SPI0 (0x52000000)
#define S3C2443_PA_SPI1 S3C2410_PA_SPI
/* SDI */
#define S3C2410_PA_SDI (0x5A000000)
@ -162,4 +164,7 @@
#define S3C_PA_WDT S3C2410_PA_WATCHDOG
#define S3C_PA_NAND S3C24XX_PA_NAND
#define S3C_PA_SPI0 S3C2443_PA_SPI0
#define S3C_PA_SPI1 S3C2443_PA_SPI1
#endif /* __ASM_ARCH_MAP_H */

98
arch/arm/mach-s3c24xx/irq-s3c2416.c
View File

@ -27,6 +27,7 @@
#include <linux/ioport.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/syscore_ops.h>
#include <mach/hardware.h>
#include <asm/irq.h>
@ -192,6 +193,43 @@ static struct irq_chip s3c2416_irq_uart3 = {
.irq_ack = s3c2416_irq_uart3_ack,
};
/* second interrupt register */
static inline void s3c2416_irq_ack_second(struct irq_data *data)
{
unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D);
__raw_writel(bitval, S3C2416_SRCPND2);
__raw_writel(bitval, S3C2416_INTPND2);
}
static void s3c2416_irq_mask_second(struct irq_data *data)
{
unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D);
unsigned long mask;
mask = __raw_readl(S3C2416_INTMSK2);
mask |= bitval;
__raw_writel(mask, S3C2416_INTMSK2);
}
static void s3c2416_irq_unmask_second(struct irq_data *data)
{
unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D);
unsigned long mask;
mask = __raw_readl(S3C2416_INTMSK2);
mask &= ~bitval;
__raw_writel(mask, S3C2416_INTMSK2);
}
struct irq_chip s3c2416_irq_second = {
.irq_ack = s3c2416_irq_ack_second,
.irq_mask = s3c2416_irq_mask_second,
.irq_unmask = s3c2416_irq_unmask_second,
};
/* IRQ initialisation code */
static int __init s3c2416_add_sub(unsigned int base,
@ -213,6 +251,42 @@ static int __init s3c2416_add_sub(unsigned int base,
return 0;
}
static void __init s3c2416_irq_add_second(void)
{
unsigned long pend;
unsigned long last;
int irqno;
int i;
/* first, clear all interrupts pending... */
last = 0;
for (i = 0; i < 4; i++) {
pend = __raw_readl(S3C2416_INTPND2);
if (pend == 0 || pend == last)
break;
__raw_writel(pend, S3C2416_SRCPND2);
__raw_writel(pend, S3C2416_INTPND2);
printk(KERN_INFO "irq: clearing pending status %08x\n",
(int)pend);
last = pend;
}
for (irqno = IRQ_S3C2416_2D; irqno <= IRQ_S3C2416_I2S1; irqno++) {
switch (irqno) {
case IRQ_S3C2416_RESERVED2:
case IRQ_S3C2416_RESERVED3:
/* no IRQ here */
break;
default:
irq_set_chip_and_handler(irqno, &s3c2416_irq_second,
handle_edge_irq);
set_irq_flags(irqno, IRQF_VALID);
}
}
}
static int __init s3c2416_irq_add(struct device *dev,
struct subsys_interface *sif)
{
@ -232,6 +306,8 @@ static int __init s3c2416_irq_add(struct device *dev,
&s3c2416_irq_wdtac97,
IRQ_S3C2443_WDT, IRQ_S3C2443_AC97);
s3c2416_irq_add_second();
return 0;
}
@ -248,3 +324,25 @@ static int __init s3c2416_irq_init(void)
arch_initcall(s3c2416_irq_init);
#ifdef CONFIG_PM
static struct sleep_save irq_save[] = {
SAVE_ITEM(S3C2416_INTMSK2),
};
int s3c2416_irq_suspend(void)
{
s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
return 0;
}
void s3c2416_irq_resume(void)
{
s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
}
struct syscore_ops s3c2416_irq_syscore_ops = {
.suspend = s3c2416_irq_suspend,
.resume = s3c2416_irq_resume,
};
#endif

1
arch/arm/mach-s3c24xx/s3c2416.c
View File

@ -106,6 +106,7 @@ int __init s3c2416_init(void)
register_syscore_ops(&s3c2416_pm_syscore_ops);
#endif
register_syscore_ops(&s3c24xx_irq_syscore_ops);
register_syscore_ops(&s3c2416_irq_syscore_ops);
return device_register(&s3c2416_dev);
}

39
arch/arm/mach-s3c24xx/setup-spi.c Normal file
View File

@ -0,0 +1,39 @@
/*
* HS-SPI device setup for S3C2443/S3C2416
*
* Copyright (C) 2011 Samsung Electronics Ltd.
* http://www.samsung.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <plat/gpio-cfg.h>
#include <plat/s3c64xx-spi.h>
#include <mach/hardware.h>
#include <mach/regs-gpio.h>
#ifdef CONFIG_S3C64XX_DEV_SPI0
struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
.fifo_lvl_mask = 0x7f,
.rx_lvl_offset = 13,
.tx_st_done = 21,
.high_speed = 1,
};
int s3c64xx_spi0_cfg_gpio(struct platform_device *pdev)
{
/* enable hsspi bit in misccr */
s3c2410_modify_misccr(S3C2416_MISCCR_HSSPI_EN2, 1);
s3c_gpio_cfgall_range(S3C2410_GPE(11), 3,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
return 0;
}
#endif

140
arch/arm/plat-s5p/Kconfig
View File

@ -1,140 +0,0 @@
# arch/arm/plat-s5p/Kconfig
#
# Copyright (c) 2009 Samsung Electronics Co., Ltd.
# http://www.samsung.com/
#
# Licensed under GPLv2
config PLAT_S5P
bool
depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
default y
select ARM_VIC if !ARCH_EXYNOS
select ARM_GIC if ARCH_EXYNOS
select GIC_NON_BANKED if ARCH_EXYNOS4
select NO_IOPORT
select ARCH_REQUIRE_GPIOLIB
select S3C_GPIO_TRACK
select S5P_GPIO_DRVSTR
select SAMSUNG_GPIOLIB_4BIT
select PLAT_SAMSUNG
select SAMSUNG_CLKSRC
select SAMSUNG_IRQ_VIC_TIMER
help
Base platform code for Samsung's S5P series SoC.
config S5P_EXT_INT
bool
help
Use the external interrupts (other than GPIO interrupts.)
Note: Do not choose this for S5P6440 and S5P6450.
config S5P_GPIO_INT
bool
help
Common code for the GPIO interrupts (other than external interrupts.)
config S5P_HRT
bool
select SAMSUNG_DEV_PWM
help
Use the High Resolution timer support
config S5P_DEV_UART
def_bool y
depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210)
config S5P_PM
bool
help
Common code for power management support on S5P and newer SoCs
Note: Do not select this for S5P6440 and S5P6450.
comment "System MMU"
config S5P_SYSTEM_MMU
bool "S5P SYSTEM MMU"
depends on ARCH_EXYNOS4
help
Say Y here if you want to enable System MMU
config S5P_SLEEP
bool
help
Internal config node to apply common S5P sleep management code.
Can be selected by S5P and newer SoCs with similar sleep procedure.
config S5P_DEV_FIMC0
bool
help
Compile in platform device definitions for FIMC controller 0
config S5P_DEV_FIMC1
bool
help
Compile in platform device definitions for FIMC controller 1
config S5P_DEV_FIMC2
bool
help
Compile in platform device definitions for FIMC controller 2
config S5P_DEV_FIMC3
bool
help
Compile in platform device definitions for FIMC controller 3
config S5P_DEV_JPEG
bool
help
Compile in platform device definitions for JPEG codec
config S5P_DEV_G2D
bool
help
Compile in platform device definitions for G2D device
config S5P_DEV_FIMD0
bool
help
Compile in platform device definitions for FIMD controller 0
config S5P_DEV_I2C_HDMIPHY
bool
help
Compile in platform device definitions for I2C HDMIPHY controller
config S5P_DEV_MFC
bool
help
Compile in platform device definitions for MFC
config S5P_DEV_ONENAND
bool
help
Compile in platform device definition for OneNAND controller
config S5P_DEV_CSIS0
bool
help
Compile in platform device definitions for MIPI-CSIS channel 0
config S5P_DEV_CSIS1
bool
help
Compile in platform device definitions for MIPI-CSIS channel 1
config S5P_DEV_TV
bool
help
Compile in platform device definition for TV interface
config S5P_DEV_USB_EHCI
bool
help
Compile in platform device definition for USB EHCI
config S5P_SETUP_MIPIPHY
bool
help
Compile in common setup code for MIPI-CSIS and MIPI-DSIM devices

28
arch/arm/plat-s5p/Makefile
View File

@ -1,28 +0,0 @@
# arch/arm/plat-s5p/Makefile
#
# Copyright (c) 2009 Samsung Electronics Co., Ltd.
# http://www.samsung.com/
#
# Licensed under GPLv2
obj-y :=
obj-m :=
obj-n := dummy.o
obj- :=
# Core files
obj-y += clock.o
obj-y += irq.o
obj-$(CONFIG_S5P_EXT_INT) += irq-eint.o
obj-$(CONFIG_S5P_GPIO_INT) += irq-gpioint.o
obj-$(CONFIG_S5P_SYSTEM_MMU) += sysmmu.o
obj-$(CONFIG_S5P_PM) += pm.o irq-pm.o
obj-$(CONFIG_S5P_SLEEP) += sleep.o
obj-$(CONFIG_S5P_HRT) += s5p-time.o
# devices
obj-$(CONFIG_S5P_DEV_UART) += dev-uart.o
obj-$(CONFIG_S5P_DEV_MFC) += dev-mfc.o
obj-$(CONFIG_S5P_SETUP_MIPIPHY) += setup-mipiphy.o

313
arch/arm/plat-s5p/sysmmu.c
View File

@ -1,313 +0,0 @@
/* linux/arch/arm/plat-s5p/sysmmu.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/export.h>
#include <asm/pgtable.h>
#include <mach/map.h>
#include <mach/regs-sysmmu.h>
#include <plat/sysmmu.h>
#define CTRL_ENABLE 0x5
#define CTRL_BLOCK 0x7
#define CTRL_DISABLE 0x0
static struct device *dev;
static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = {
S5P_PAGE_FAULT_ADDR,
S5P_AR_FAULT_ADDR,
S5P_AW_FAULT_ADDR,
S5P_DEFAULT_SLAVE_ADDR,
S5P_AR_FAULT_ADDR,
S5P_AR_FAULT_ADDR,
S5P_AW_FAULT_ADDR,
S5P_AW_FAULT_ADDR
};
static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = {
"PAGE FAULT",
"AR MULTI-HIT FAULT",
"AW MULTI-HIT FAULT",
"BUS ERROR",
"AR SECURITY PROTECTION FAULT",
"AR ACCESS PROTECTION FAULT",
"AW SECURITY PROTECTION FAULT",
"AW ACCESS PROTECTION FAULT"
};
static int (*fault_handlers[S5P_SYSMMU_TOTAL_IPNUM])(
enum S5P_SYSMMU_INTERRUPT_TYPE itype,
unsigned long pgtable_base,
unsigned long fault_addr);
/*
* If adjacent 2 bits are true, the system MMU is enabled.
* The system MMU is disabled, otherwise.
*/
static unsigned long sysmmu_states;
static inline void set_sysmmu_active(sysmmu_ips ips)
{
sysmmu_states |= 3 << (ips * 2);
}
static inline void set_sysmmu_inactive(sysmmu_ips ips)
{
sysmmu_states &= ~(3 << (ips * 2));
}
static inline int is_sysmmu_active(sysmmu_ips ips)
{
return sysmmu_states & (3 << (ips * 2));
}
static void __iomem *sysmmusfrs[S5P_SYSMMU_TOTAL_IPNUM];
static inline void sysmmu_block(sysmmu_ips ips)
{
__raw_writel(CTRL_BLOCK, sysmmusfrs[ips] + S5P_MMU_CTRL);
dev_dbg(dev, "%s is blocked.\n", sysmmu_ips_name[ips]);
}
static inline void sysmmu_unblock(sysmmu_ips ips)
{
__raw_writel(CTRL_ENABLE, sysmmusfrs[ips] + S5P_MMU_CTRL);
dev_dbg(dev, "%s is unblocked.\n", sysmmu_ips_name[ips]);
}
static inline void __sysmmu_tlb_invalidate(sysmmu_ips ips)
{
__raw_writel(0x1, sysmmusfrs[ips] + S5P_MMU_FLUSH);
dev_dbg(dev, "TLB of %s is invalidated.\n", sysmmu_ips_name[ips]);
}
static inline void __sysmmu_set_ptbase(sysmmu_ips ips, unsigned long pgd)
{
if (unlikely(pgd == 0)) {
pgd = (unsigned long)ZERO_PAGE(0);
__raw_writel(0x20, sysmmusfrs[ips] + S5P_MMU_CFG); /* 4KB LV1 */
} else {
__raw_writel(0x0, sysmmusfrs[ips] + S5P_MMU_CFG); /* 16KB LV1 */
}
__raw_writel(pgd, sysmmusfrs[ips] + S5P_PT_BASE_ADDR);
dev_dbg(dev, "Page table base of %s is initialized with 0x%08lX.\n",
sysmmu_ips_name[ips], pgd);
__sysmmu_tlb_invalidate(ips);
}
void sysmmu_set_fault_handler(sysmmu_ips ips,
int (*handler)(enum S5P_SYSMMU_INTERRUPT_TYPE itype,
unsigned long pgtable_base,
unsigned long fault_addr))
{
BUG_ON(!((ips >= SYSMMU_MDMA) && (ips < S5P_SYSMMU_TOTAL_IPNUM)));
fault_handlers[ips] = handler;
}
static irqreturn_t s5p_sysmmu_irq(int irq, void *dev_id)
{
/* SYSMMU is in blocked when interrupt occurred. */
unsigned long base = 0;
sysmmu_ips ips = (sysmmu_ips)dev_id;
enum S5P_SYSMMU_INTERRUPT_TYPE itype;
itype = (enum S5P_SYSMMU_INTERRUPT_TYPE)
__ffs(__raw_readl(sysmmusfrs[ips] + S5P_INT_STATUS));
BUG_ON(!((itype >= 0) && (itype < 8)));
dev_alert(dev, "%s occurred by %s.\n", sysmmu_fault_name[itype],
sysmmu_ips_name[ips]);
if (fault_handlers[ips]) {
unsigned long addr;
base = __raw_readl(sysmmusfrs[ips] + S5P_PT_BASE_ADDR);
addr = __raw_readl(sysmmusfrs[ips] + fault_reg_offset[itype]);
if (fault_handlers[ips](itype, base, addr)) {
__raw_writel(1 << itype,
sysmmusfrs[ips] + S5P_INT_CLEAR);
dev_notice(dev, "%s from %s is resolved."
" Retrying translation.\n",
sysmmu_fault_name[itype], sysmmu_ips_name[ips]);
} else {
base = 0;
}
}
sysmmu_unblock(ips);
if (!base)
dev_notice(dev, "%s from %s is not handled.\n",
sysmmu_fault_name[itype], sysmmu_ips_name[ips]);
return IRQ_HANDLED;
}
void s5p_sysmmu_set_tablebase_pgd(sysmmu_ips ips, unsigned long pgd)
{
if (is_sysmmu_active(ips)) {
sysmmu_block(ips);
__sysmmu_set_ptbase(ips, pgd);
sysmmu_unblock(ips);
} else {
dev_dbg(dev, "%s is disabled. "
"Skipping initializing page table base.\n",
sysmmu_ips_name[ips]);
}
}
void s5p_sysmmu_enable(sysmmu_ips ips, unsigned long pgd)
{
if (!is_sysmmu_active(ips)) {
sysmmu_clk_enable(ips);
__sysmmu_set_ptbase(ips, pgd);
__raw_writel(CTRL_ENABLE, sysmmusfrs[ips] + S5P_MMU_CTRL);
set_sysmmu_active(ips);
dev_dbg(dev, "%s is enabled.\n", sysmmu_ips_name[ips]);
} else {
dev_dbg(dev, "%s is already enabled.\n", sysmmu_ips_name[ips]);
}
}
void s5p_sysmmu_disable(sysmmu_ips ips)
{
if (is_sysmmu_active(ips)) {
__raw_writel(CTRL_DISABLE, sysmmusfrs[ips] + S5P_MMU_CTRL);
set_sysmmu_inactive(ips);
sysmmu_clk_disable(ips);
dev_dbg(dev, "%s is disabled.\n", sysmmu_ips_name[ips]);
} else {
dev_dbg(dev, "%s is already disabled.\n", sysmmu_ips_name[ips]);
}
}
void s5p_sysmmu_tlb_invalidate(sysmmu_ips ips)
{
if (is_sysmmu_active(ips)) {
sysmmu_block(ips);
__sysmmu_tlb_invalidate(ips);
sysmmu_unblock(ips);
} else {
dev_dbg(dev, "%s is disabled. "
"Skipping invalidating TLB.\n", sysmmu_ips_name[ips]);
}
}
static int s5p_sysmmu_probe(struct platform_device *pdev)
{
int i, ret;
struct resource *res, *mem;
dev = &pdev->dev;
for (i = 0; i < S5P_SYSMMU_TOTAL_IPNUM; i++) {
int irq;
sysmmu_clk_init(dev, i);
sysmmu_clk_disable(i);
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
if (!res) {
dev_err(dev, "Failed to get the resource of %s.\n",
sysmmu_ips_name[i]);
ret = -ENODEV;
goto err_res;
}
mem = request_mem_region(res->start, resource_size(res),
pdev->name);
if (!mem) {
dev_err(dev, "Failed to request the memory region of %s.\n",
sysmmu_ips_name[i]);
ret = -EBUSY;
goto err_res;
}
sysmmusfrs[i] = ioremap(res->start, resource_size(res));
if (!sysmmusfrs[i]) {
dev_err(dev, "Failed to ioremap() for %s.\n",
sysmmu_ips_name[i]);
ret = -ENXIO;
goto err_reg;
}
irq = platform_get_irq(pdev, i);
if (irq <= 0) {
dev_err(dev, "Failed to get the IRQ resource of %s.\n",
sysmmu_ips_name[i]);
ret = -ENOENT;
goto err_map;
}
if (request_irq(irq, s5p_sysmmu_irq, IRQF_DISABLED,
pdev->name, (void *)i)) {
dev_err(dev, "Failed to request IRQ for %s.\n",
sysmmu_ips_name[i]);
ret = -ENOENT;
goto err_map;
}
}
return 0;
err_map:
iounmap(sysmmusfrs[i]);
err_reg:
release_mem_region(mem->start, resource_size(mem));
err_res:
return ret;
}
static int s5p_sysmmu_remove(struct platform_device *pdev)
{
return 0;
}
int s5p_sysmmu_runtime_suspend(struct device *dev)
{
return 0;
}
int s5p_sysmmu_runtime_resume(struct device *dev)
{
return 0;
}
const struct dev_pm_ops s5p_sysmmu_pm_ops = {
.runtime_suspend = s5p_sysmmu_runtime_suspend,
.runtime_resume = s5p_sysmmu_runtime_resume,
};
static struct platform_driver s5p_sysmmu_driver = {
.probe = s5p_sysmmu_probe,
.remove = s5p_sysmmu_remove,
.driver = {
.owner = THIS_MODULE,
.name = "s5p-sysmmu",
.pm = &s5p_sysmmu_pm_ops,
}
};
static int __init s5p_sysmmu_init(void)
{
return platform_driver_register(&s5p_sysmmu_driver);
}
arch_initcall(s5p_sysmmu_init);

142
arch/arm/plat-samsung/Kconfig
View File

@ -13,6 +13,24 @@ config PLAT_SAMSUNG
help
Base platform code for all Samsung SoC based systems
config PLAT_S5P
bool
depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
default y
select ARM_VIC if !ARCH_EXYNOS
select ARM_GIC if ARCH_EXYNOS
select GIC_NON_BANKED if ARCH_EXYNOS4
select NO_IOPORT
select ARCH_REQUIRE_GPIOLIB
select S3C_GPIO_TRACK
select S5P_GPIO_DRVSTR
select SAMSUNG_GPIOLIB_4BIT
select PLAT_SAMSUNG
select SAMSUNG_CLKSRC
select SAMSUNG_IRQ_VIC_TIMER
help
Base platform code for Samsung's S5P series SoC.
if PLAT_SAMSUNG
# boot configurations
@ -50,6 +68,14 @@ config S3C_LOWLEVEL_UART_PORT
this configuration should be between zero and two. The port
must have been initialised by the boot-loader before use.
# timer options
config S5P_HRT
bool
select SAMSUNG_DEV_PWM
help
Use the High Resolution timer support
# clock options
config SAMSUNG_CLKSRC
@ -58,6 +84,11 @@ config SAMSUNG_CLKSRC
Select the clock code for the clksrc implementation
used by newer systems such as the S3C64XX.
config S5P_CLOCK
def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
help
Support common clock part for ARCH_S5P and ARCH_EXYNOS SoCs
# options for IRQ support
config SAMSUNG_IRQ_VIC_TIMER
@ -65,6 +96,22 @@ config SAMSUNG_IRQ_VIC_TIMER
help
Internal configuration to build the VIC timer interrupt code.
config S5P_IRQ
def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
help
Support common interrup part for ARCH_S5P and ARCH_EXYNOS SoCs
config S5P_EXT_INT
bool
help
Use the external interrupts (other than GPIO interrupts.)
Note: Do not choose this for S5P6440 and S5P6450.
config S5P_GPIO_INT
bool
help
Common code for the GPIO interrupts (other than external interrupts.)
# options for gpio configuration support
config SAMSUNG_GPIOLIB_4BIT
@ -117,6 +164,12 @@ config S3C_GPIO_TRACK
Internal configuration option to enable the s3c specific gpio
chip tracking if the platform requires it.
# uart options
config S5P_DEV_UART
def_bool y
depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210)
# ADC driver
config S3C_ADC
@ -274,6 +327,76 @@ config SAMSUNG_DEV_BACKLIGHT
help
Compile in platform device definition LCD backlight with PWM Timer
config S5P_DEV_CSIS0
bool
help
Compile in platform device definitions for MIPI-CSIS channel 0
config S5P_DEV_CSIS1
bool
help
Compile in platform device definitions for MIPI-CSIS channel 1
config S5P_DEV_FIMC0
bool
help
Compile in platform device definitions for FIMC controller 0
config S5P_DEV_FIMC1
bool
help
Compile in platform device definitions for FIMC controller 1
config S5P_DEV_FIMC2
bool
help
Compile in platform device definitions for FIMC controller 2
config S5P_DEV_FIMC3
bool
help
Compile in platform device definitions for FIMC controller 3
config S5P_DEV_FIMD0
bool
help
Compile in platform device definitions for FIMD controller 0
config S5P_DEV_G2D
bool
help
Compile in platform device definitions for G2D device
config S5P_DEV_I2C_HDMIPHY
bool
help
Compile in platform device definitions for I2C HDMIPHY controller
config S5P_DEV_JPEG
bool
help
Compile in platform device definitions for JPEG codec
config S5P_DEV_MFC
bool
help
Compile in setup memory (init) code for MFC
config S5P_DEV_ONENAND
bool
help
Compile in platform device definition for OneNAND controller
config S5P_DEV_TV
bool
help
Compile in platform device definition for TV interface
config S5P_DEV_USB_EHCI
bool
help
Compile in platform device definition for USB EHCI
config S3C24XX_PWM
bool "PWM device support"
select HAVE_PWM
@ -281,6 +404,11 @@ config S3C24XX_PWM
Support for exporting the PWM timer blocks via the pwm device
system
config S5P_SETUP_MIPIPHY
bool
help
Compile in common setup code for MIPI-CSIS and MIPI-DSIM devices
# DMA
config S3C_DMA
@ -291,7 +419,7 @@ config S3C_DMA
config SAMSUNG_DMADEV
bool
select DMADEVICES
select PL330_DMA if (CPU_EXYNOS4210 || CPU_S5PV210 || CPU_S5PC100 || \
select PL330_DMA if (ARCH_EXYNOS5 || ARCH_EXYNOS4 || CPU_S5PV210 || CPU_S5PC100 || \
CPU_S5P6450 || CPU_S5P6440)
select ARM_AMBA
help
@ -351,6 +479,18 @@ config SAMSUNG_WAKEMASK
and above. This code allows a set of interrupt to wakeup-mask
mappings. See <plat/wakeup-mask.h>
config S5P_PM
bool
help
Common code for power management support on S5P and newer SoCs
Note: Do not select this for S5P6440 and S5P6450.
config S5P_SLEEP
bool
help
Internal config node to apply common S5P sleep management code.
Can be selected by S5P and newer SoCs with similar sleep procedure.
comment "Power Domain"
config SAMSUNG_PD

13
arch/arm/plat-samsung/Makefile
View File

@ -13,12 +13,18 @@ obj- :=
obj-y += init.o cpu.o
obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET) += time.o
obj-$(CONFIG_S5P_HRT) += s5p-time.o
obj-y += clock.o
obj-y += pwm-clock.o
obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o
obj-$(CONFIG_S5P_CLOCK) += s5p-clock.o
obj-$(CONFIG_SAMSUNG_IRQ_VIC_TIMER) += irq-vic-timer.o
obj-$(CONFIG_S5P_IRQ) += s5p-irq.o
obj-$(CONFIG_S5P_EXT_INT) += s5p-irq-eint.o
obj-$(CONFIG_S5P_GPIO_INT) += s5p-irq-gpioint.o
# ADC
@ -30,9 +36,13 @@ obj-y += platformdata.o
obj-y += devs.o
obj-y += dev-uart.o
obj-$(CONFIG_S5P_DEV_MFC) += s5p-dev-mfc.o
obj-$(CONFIG_S5P_DEV_UART) += s5p-dev-uart.o
obj-$(CONFIG_SAMSUNG_DEV_BACKLIGHT) += dev-backlight.o
obj-$(CONFIG_S5P_SETUP_MIPIPHY) += setup-mipiphy.o
# DMA support
obj-$(CONFIG_S3C_DMA) += dma.o s3c-dma-ops.o
@ -47,6 +57,9 @@ obj-$(CONFIG_SAMSUNG_PM_CHECK) += pm-check.o
obj-$(CONFIG_SAMSUNG_WAKEMASK) += wakeup-mask.o
obj-$(CONFIG_S5P_PM) += s5p-pm.o s5p-irq-pm.o
obj-$(CONFIG_S5P_SLEEP) += s5p-sleep.o
# PD support
obj-$(CONFIG_SAMSUNG_PD) += pd.o

2
arch/arm/plat-samsung/include/plat/cpu.h
View File

@ -202,7 +202,7 @@ extern struct bus_type s3c2443_subsys;
extern struct bus_type s3c6410_subsys;
extern struct bus_type s5p64x0_subsys;
extern struct bus_type s5pv210_subsys;
extern struct bus_type exynos4_subsys;
extern struct bus_type exynos_subsys;
extern void (*s5pc1xx_idle)(void);

3
arch/arm/plat-samsung/include/plat/devs.h
View File

@ -133,7 +133,8 @@ extern struct platform_device exynos4_device_pcm1;
extern struct platform_device exynos4_device_pcm2;
extern struct platform_device exynos4_device_pd[];
extern struct platform_device exynos4_device_spdif;
extern struct platform_device exynos4_device_sysmmu;
extern struct platform_device exynos_device_drm;
extern struct platform_device samsung_asoc_dma;
extern struct platform_device samsung_asoc_idma;

1
arch/arm/plat-samsung/include/plat/dma-pl330.h
View File

@ -90,6 +90,7 @@ enum dma_ch {
DMACH_MIPI_HSI5,
DMACH_MIPI_HSI6,
DMACH_MIPI_HSI7,
DMACH_DISP1,
DMACH_MTOM_0,
DMACH_MTOM_1,
DMACH_MTOM_2,

3
arch/arm/plat-samsung/include/plat/s3c2416.h
View File

@ -24,6 +24,9 @@ extern void s3c2416_init_clocks(int xtal);
extern int s3c2416_baseclk_add(void);
extern void s3c2416_restart(char mode, const char *cmd);
extern struct syscore_ops s3c2416_irq_syscore_ops;
#else
#define s3c2416_init_clocks NULL
#define s3c2416_init_uarts NULL

4
arch/arm/plat-samsung/include/plat/s5p-clock.h
View File

@ -32,8 +32,10 @@ extern struct clk clk_48m;
extern struct clk s5p_clk_27m;
extern struct clk clk_fout_apll;
extern struct clk clk_fout_bpll;
extern struct clk clk_fout_bpll_div2;
extern struct clk clk_fout_cpll;
extern struct clk clk_fout_mpll;
extern struct clk clk_fout_mpll_div2;
extern struct clk clk_fout_epll;
extern struct clk clk_fout_dpll;
extern struct clk clk_fout_vpll;
@ -42,8 +44,10 @@ extern struct clk clk_vpll;
extern struct clksrc_sources clk_src_apll;
extern struct clksrc_sources clk_src_bpll;
extern struct clksrc_sources clk_src_bpll_fout;
extern struct clksrc_sources clk_src_cpll;
extern struct clksrc_sources clk_src_mpll;
extern struct clksrc_sources clk_src_mpll_fout;
extern struct clksrc_sources clk_src_epll;
extern struct clksrc_sources clk_src_dpll;

95
arch/arm/plat-samsung/include/plat/sysmmu.h
View File

@ -1,95 +0,0 @@
/* linux/arch/arm/plat-samsung/include/plat/sysmmu.h
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Samsung System MMU driver for S5P platform
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __PLAT_SAMSUNG_SYSMMU_H
#define __PLAT_SAMSUNG_SYSMMU_H __FILE__
enum S5P_SYSMMU_INTERRUPT_TYPE {
SYSMMU_PAGEFAULT,
SYSMMU_AR_MULTIHIT,
SYSMMU_AW_MULTIHIT,
SYSMMU_BUSERROR,
SYSMMU_AR_SECURITY,
SYSMMU_AR_ACCESS,
SYSMMU_AW_SECURITY,
SYSMMU_AW_PROTECTION, /* 7 */
SYSMMU_FAULTS_NUM
};
#ifdef CONFIG_S5P_SYSTEM_MMU
#include <mach/sysmmu.h>
/**
* s5p_sysmmu_enable() - enable system mmu of ip
* @ips: The ip connected system mmu.
* #pgd: Base physical address of the 1st level page table
*
* This function enable system mmu to transfer address
* from virtual address to physical address
*/
void s5p_sysmmu_enable(sysmmu_ips ips, unsigned long pgd);
/**
* s5p_sysmmu_disable() - disable sysmmu mmu of ip
* @ips: The ip connected system mmu.
*
* This function disable system mmu to transfer address
* from virtual address to physical address
*/
void s5p_sysmmu_disable(sysmmu_ips ips);
/**
* s5p_sysmmu_set_tablebase_pgd() - set page table base address to refer page table
* @ips: The ip connected system mmu.
* @pgd: The page table base address.
*
* This function set page table base address
* When system mmu transfer address from virtaul address to physical address,
* system mmu refer address information from page table
*/
void s5p_sysmmu_set_tablebase_pgd(sysmmu_ips ips, unsigned long pgd);
/**
* s5p_sysmmu_tlb_invalidate() - flush all TLB entry in system mmu
* @ips: The ip connected system mmu.
*
* This function flush all TLB entry in system mmu
*/
void s5p_sysmmu_tlb_invalidate(sysmmu_ips ips);
/** s5p_sysmmu_set_fault_handler() - Fault handler for System MMUs
* @itype: type of fault.
* @pgtable_base: the physical address of page table base. This is 0 if @ips is
* SYSMMU_BUSERROR.
* @fault_addr: the device (virtual) address that the System MMU tried to
* translated. This is 0 if @ips is SYSMMU_BUSERROR.
* Called when interrupt occurred by the System MMUs
* The device drivers of peripheral devices that has a System MMU can implement
* a fault handler to resolve address translation fault by System MMU.
* The meanings of return value and parameters are described below.
* return value: non-zero if the fault is correctly resolved.
* zero if the fault is not handled.
*/
void s5p_sysmmu_set_fault_handler(sysmmu_ips ips,
int (*handler)(enum S5P_SYSMMU_INTERRUPT_TYPE itype,
unsigned long pgtable_base,
unsigned long fault_addr));
#else
#define s5p_sysmmu_enable(ips, pgd) do { } while (0)
#define s5p_sysmmu_disable(ips) do { } while (0)
#define s5p_sysmmu_set_tablebase_pgd(ips, pgd) do { } while (0)
#define s5p_sysmmu_tlb_invalidate(ips) do { } while (0)
#define s5p_sysmmu_set_fault_handler(ips, handler) do { } while (0)
#endif
#endif /* __ASM_PLAT_SYSMMU_H */

33
arch/arm/plat-s5p/clock.c → arch/arm/plat-samsung/s5p-clock.c
View File

@ -1,5 +1,4 @@
/* linux/arch/arm/plat-s5p/clock.c
*
/*
* Copyright 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
@ -68,6 +67,11 @@ struct clk clk_fout_bpll = {
.id = -1,
};
struct clk clk_fout_bpll_div2 = {
.name = "fout_bpll_div2",
.id = -1,
};
/* CPLL clock output */
struct clk clk_fout_cpll = {
@ -83,6 +87,11 @@ struct clk clk_fout_mpll = {
.id = -1,
};
struct clk clk_fout_mpll_div2 = {
.name = "fout_mpll_div2",
.id = -1,
};
/* EPLL clock output */
struct clk clk_fout_epll = {
.name = "fout_epll",
@ -126,6 +135,16 @@ struct clksrc_sources clk_src_bpll = {
.nr_sources = ARRAY_SIZE(clk_src_bpll_list),
};
static struct clk *clk_src_bpll_fout_list[] = {
[0] = &clk_fout_bpll_div2,
[1] = &clk_fout_bpll,
};
struct clksrc_sources clk_src_bpll_fout = {
.sources = clk_src_bpll_fout_list,
.nr_sources = ARRAY_SIZE(clk_src_bpll_fout_list),
};
/* Possible clock sources for CPLL Mux */
static struct clk *clk_src_cpll_list[] = {
[0] = &clk_fin_cpll,
@ -148,6 +167,16 @@ struct clksrc_sources clk_src_mpll = {
.nr_sources = ARRAY_SIZE(clk_src_mpll_list),
};
static struct clk *clk_src_mpll_fout_list[] = {
[0] = &clk_fout_mpll_div2,
[1] = &clk_fout_mpll,
};
struct clksrc_sources clk_src_mpll_fout = {
.sources = clk_src_mpll_fout_list,
.nr_sources = ARRAY_SIZE(clk_src_mpll_fout_list),
};
/* Possible clock sources for EPLL Mux */
static struct clk *clk_src_epll_list[] = {
[0] = &clk_fin_epll,

4
arch/arm/plat-s5p/dev-mfc.c → arch/arm/plat-samsung/s5p-dev-mfc.c
View File

@ -1,5 +1,4 @@
/* linux/arch/arm/plat-s5p/dev-mfc.c
*
/*
* Copyright (C) 2010-2011 Samsung Electronics Co.Ltd
*
* Base S5P MFC resource and device definitions
@ -9,7 +8,6 @@
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>

78
arch/arm/plat-s5p/dev-uart.c → arch/arm/plat-samsung/s5p-dev-uart.c
View File

@ -1,6 +1,5 @@
/* linux/arch/arm/plat-s5p/dev-uart.c
*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
/*
* Copyright (c) 2009,2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* Base S5P UART resource and device definitions
@ -14,6 +13,7 @@
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <asm/mach/arch.h>
@ -26,86 +26,38 @@
/* Serial port registrations */
static struct resource s5p_uart0_resource[] = {
[0] = {
.start = S5P_PA_UART0,
.end = S5P_PA_UART0 + S5P_SZ_UART - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_UART0,
.end = IRQ_UART0,
.flags = IORESOURCE_IRQ,
},
[0] = DEFINE_RES_MEM(S5P_PA_UART0, S5P_SZ_UART),
[1] = DEFINE_RES_IRQ(IRQ_UART0),
};
static struct resource s5p_uart1_resource[] = {
[0] = {
.start = S5P_PA_UART1,
.end = S5P_PA_UART1 + S5P_SZ_UART - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_UART1,
.end = IRQ_UART1,
.flags = IORESOURCE_IRQ,
},
[0] = DEFINE_RES_MEM(S5P_PA_UART1, S5P_SZ_UART),
[1] = DEFINE_RES_IRQ(IRQ_UART1),
};
static struct resource s5p_uart2_resource[] = {
[0] = {
.start = S5P_PA_UART2,
.end = S5P_PA_UART2 + S5P_SZ_UART - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_UART2,
.end = IRQ_UART2,
.flags = IORESOURCE_IRQ,
},
[0] = DEFINE_RES_MEM(S5P_PA_UART2, S5P_SZ_UART),
[1] = DEFINE_RES_IRQ(IRQ_UART2),
};
static struct resource s5p_uart3_resource[] = {
#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
[0] = {
.start = S5P_PA_UART3,
.end = S5P_PA_UART3 + S5P_SZ_UART - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_UART3,
.end = IRQ_UART3,
.flags = IORESOURCE_IRQ,
},
[0] = DEFINE_RES_MEM(S5P_PA_UART3, S5P_SZ_UART),
[1] = DEFINE_RES_IRQ(IRQ_UART3),
#endif
};
static struct resource s5p_uart4_resource[] = {
#if CONFIG_SERIAL_SAMSUNG_UARTS > 4
[0] = {
.start = S5P_PA_UART4,
.end = S5P_PA_UART4 + S5P_SZ_UART - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_UART4,
.end = IRQ_UART4,
.flags = IORESOURCE_IRQ,
},
[0] = DEFINE_RES_MEM(S5P_PA_UART4, S5P_SZ_UART),
[1] = DEFINE_RES_IRQ(IRQ_UART4),
#endif
};
static struct resource s5p_uart5_resource[] = {
#if CONFIG_SERIAL_SAMSUNG_UARTS > 5
[0] = {
.start = S5P_PA_UART5,
.end = S5P_PA_UART5 + S5P_SZ_UART - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_UART5,
.end = IRQ_UART5,
.flags = IORESOURCE_IRQ,
},
[0] = DEFINE_RES_MEM(S5P_PA_UART5, S5P_SZ_UART),
[1] = DEFINE_RES_IRQ(IRQ_UART5),
#endif
};

3
arch/arm/plat-s5p/irq-eint.c → arch/arm/plat-samsung/s5p-irq-eint.c
View File

@ -1,5 +1,4 @@
/* linux/arch/arm/plat-s5p/irq-eint.c
*
/*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*

3
arch/arm/plat-s5p/irq-gpioint.c → arch/arm/plat-samsung/s5p-irq-gpioint.c
View File

@ -1,5 +1,4 @@
/* linux/arch/arm/plat-s5p/irq-gpioint.c
*
/*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* Author: Kyungmin Park <kyungmin.park@samsung.com>
* Author: Joonyoung Shim <jy0922.shim@samsung.com>

3
arch/arm/plat-s5p/irq-pm.c → arch/arm/plat-samsung/s5p-irq-pm.c
View File

@ -1,5 +1,4 @@
/* linux/arch/arm/plat-s5p/irq-pm.c
*
/*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*

3
arch/arm/plat-s5p/irq.c → arch/arm/plat-samsung/s5p-irq.c
View File

@ -1,5 +1,4 @@
/* arch/arm/plat-s5p/irq.c
*
/*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*

3
arch/arm/plat-s5p/pm.c → arch/arm/plat-samsung/s5p-pm.c
View File

@ -1,5 +1,4 @@
/* linux/arch/arm/plat-s5p/pm.c
*
/*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*

3
arch/arm/plat-s5p/sleep.S → arch/arm/plat-samsung/s5p-sleep.S
View File

@ -1,5 +1,4 @@
/* linux/arch/arm/plat-s5p/sleep.S
*
/*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*

3
arch/arm/plat-s5p/s5p-time.c → arch/arm/plat-samsung/s5p-time.c
View File

@ -1,5 +1,4 @@
/* linux/arch/arm/plat-s5p/s5p-time.c
*
/*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*

0
arch/arm/plat-s5p/setup-mipiphy.c → arch/arm/plat-samsung/setup-mipiphy.c
View File

11
drivers/gpio/gpio-samsung.c
View File

@ -2452,6 +2452,12 @@ static struct samsung_gpio_chip exynos5_gpios_1[] = {
.ngpio = EXYNOS5_GPIO_C3_NR,
.label = "GPC3",
},
}, {
.chip = {
.base = EXYNOS5_GPC4(0),
.ngpio = EXYNOS5_GPIO_C4_NR,
.label = "GPC4",
},
}, {
.chip = {
.base = EXYNOS5_GPD0(0),
@ -2878,8 +2884,11 @@ static __init int samsung_gpiolib_init(void)
goto err_ioremap1;
}
/* need to set base address for gpc4 */
exynos5_gpios_1[11].base = gpio_base1 + 0x2E0;
/* need to set base address for gpx */
chip = &exynos5_gpios_1[20];
chip = &exynos5_gpios_1[21];
gpx_base = gpio_base1 + 0xC00;
for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
chip->base = gpx_base;

21
drivers/iommu/Kconfig
View File

@ -162,4 +162,25 @@ config TEGRA_IOMMU_SMMU
space through the SMMU (System Memory Management Unit)
hardware included on Tegra SoCs.
config EXYNOS_IOMMU
bool "Exynos IOMMU Support"
depends on ARCH_EXYNOS && EXYNOS_DEV_SYSMMU
select IOMMU_API
help
Support for the IOMMU(System MMU) of Samsung Exynos application
processor family. This enables H/W multimedia accellerators to see
non-linear physical memory chunks as a linear memory in their
address spaces
If unsure, say N here.
config EXYNOS_IOMMU_DEBUG
bool "Debugging log for Exynos IOMMU"
depends on EXYNOS_IOMMU
help
Select this to see the detailed log message that shows what
happens in the IOMMU driver
Say N unless you need kernel log message for IOMMU debugging
endif # IOMMU_SUPPORT

1
drivers/iommu/Makefile
View File

@ -10,3 +10,4 @@ obj-$(CONFIG_OMAP_IOVMM) += omap-iovmm.o
obj-$(CONFIG_OMAP_IOMMU_DEBUG) += omap-iommu-debug.o
obj-$(CONFIG_TEGRA_IOMMU_GART) += tegra-gart.o
obj-$(CONFIG_TEGRA_IOMMU_SMMU) += tegra-smmu.o
obj-$(CONFIG_EXYNOS_IOMMU) += exynos-iommu.o

1076
drivers/iommu/exynos-iommu.c Normal file
View File

File diff suppressed because it is too large Load Diff

2
drivers/spi/Kconfig
View File

@ -311,7 +311,7 @@ config SPI_S3C24XX_FIQ
config SPI_S3C64XX
tristate "Samsung S3C64XX series type SPI"
depends on (ARCH_S3C64XX || ARCH_S5P64X0 || ARCH_EXYNOS)
depends on (ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5P64X0 || ARCH_EXYNOS)
select S3C64XX_DMA if ARCH_S3C64XX
help
SPI driver for Samsung S3C64XX and newer SoCs.