mirror of https://gitee.com/openkylin/linux.git
misc: rtsx: Removed unused dev_aspm_mode
The struct rtsx_cr_option.dev_aspm_mode member is never set to anything other than DEV_ASPM_DYNAMIC (0). Remove it and code that tests it. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/20200521180545.1159896-3-helgaas@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
parent
8786eda9a9
commit
51876e22bf
|
@ -349,25 +349,15 @@ static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
|
|||
|
||||
static void rts5249_set_aspm(struct rtsx_pcr *pcr, bool enable)
|
||||
{
|
||||
struct rtsx_cr_option *option = &pcr->option;
|
||||
u8 val = 0;
|
||||
|
||||
if (pcr->aspm_enabled == enable)
|
||||
return;
|
||||
|
||||
if (option->dev_aspm_mode == DEV_ASPM_DYNAMIC) {
|
||||
if (enable)
|
||||
val = pcr->aspm_en;
|
||||
rtsx_pci_update_cfg_byte(pcr,
|
||||
pcr->pcie_cap + PCI_EXP_LNKCTL,
|
||||
ASPM_MASK_NEG, val);
|
||||
} else if (option->dev_aspm_mode == DEV_ASPM_BACKDOOR) {
|
||||
u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0;
|
||||
|
||||
if (!enable)
|
||||
val = FORCE_ASPM_CTL0;
|
||||
rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
|
||||
}
|
||||
if (enable)
|
||||
val = pcr->aspm_en;
|
||||
rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
|
||||
ASPM_MASK_NEG, val);
|
||||
|
||||
pcr->aspm_enabled = enable;
|
||||
}
|
||||
|
@ -471,7 +461,6 @@ void rts5249_init_params(struct rtsx_pcr *pcr)
|
|||
option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
|
||||
option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
|
||||
option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
|
||||
option->dev_aspm_mode = DEV_ASPM_DYNAMIC;
|
||||
option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
|
||||
option->ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5249_DEF;
|
||||
option->ltr_l1off_snooze_sspwrgate =
|
||||
|
|
|
@ -572,24 +572,15 @@ static int rts5260_extra_init_hw(struct rtsx_pcr *pcr)
|
|||
|
||||
static void rts5260_set_aspm(struct rtsx_pcr *pcr, bool enable)
|
||||
{
|
||||
struct rtsx_cr_option *option = &pcr->option;
|
||||
u8 val = 0;
|
||||
|
||||
if (pcr->aspm_enabled == enable)
|
||||
return;
|
||||
|
||||
if (option->dev_aspm_mode == DEV_ASPM_DYNAMIC) {
|
||||
if (enable)
|
||||
val = pcr->aspm_en;
|
||||
rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
|
||||
ASPM_MASK_NEG, val);
|
||||
} else if (option->dev_aspm_mode == DEV_ASPM_BACKDOOR) {
|
||||
u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0;
|
||||
|
||||
if (!enable)
|
||||
val = FORCE_ASPM_CTL0;
|
||||
rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
|
||||
}
|
||||
if (enable)
|
||||
val = pcr->aspm_en;
|
||||
rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
|
||||
ASPM_MASK_NEG, val);
|
||||
|
||||
pcr->aspm_enabled = enable;
|
||||
}
|
||||
|
@ -683,7 +674,6 @@ void rts5260_init_params(struct rtsx_pcr *pcr)
|
|||
option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
|
||||
option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
|
||||
option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
|
||||
option->dev_aspm_mode = DEV_ASPM_DYNAMIC;
|
||||
option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
|
||||
option->ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
|
||||
option->ltr_l1off_snooze_sspwrgate =
|
||||
|
|
|
@ -518,51 +518,28 @@ static int rts5261_extra_init_hw(struct rtsx_pcr *pcr)
|
|||
|
||||
static void rts5261_enable_aspm(struct rtsx_pcr *pcr, bool enable)
|
||||
{
|
||||
struct rtsx_cr_option *option = &pcr->option;
|
||||
u8 val = 0;
|
||||
|
||||
if (pcr->aspm_enabled == enable)
|
||||
return;
|
||||
|
||||
if (option->dev_aspm_mode == DEV_ASPM_DYNAMIC) {
|
||||
val = pcr->aspm_en;
|
||||
rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
|
||||
ASPM_MASK_NEG, val);
|
||||
} else if (option->dev_aspm_mode == DEV_ASPM_BACKDOOR) {
|
||||
u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0;
|
||||
|
||||
val = FORCE_ASPM_CTL0;
|
||||
val |= (pcr->aspm_en & 0x02);
|
||||
rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
|
||||
val = pcr->aspm_en;
|
||||
rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
|
||||
ASPM_MASK_NEG, val);
|
||||
}
|
||||
val = pcr->aspm_en;
|
||||
rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
|
||||
ASPM_MASK_NEG, val);
|
||||
pcr->aspm_enabled = enable;
|
||||
|
||||
}
|
||||
|
||||
static void rts5261_disable_aspm(struct rtsx_pcr *pcr, bool enable)
|
||||
{
|
||||
struct rtsx_cr_option *option = &pcr->option;
|
||||
u8 val = 0;
|
||||
|
||||
if (pcr->aspm_enabled == enable)
|
||||
return;
|
||||
|
||||
if (option->dev_aspm_mode == DEV_ASPM_DYNAMIC) {
|
||||
val = 0;
|
||||
rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
|
||||
ASPM_MASK_NEG, val);
|
||||
} else if (option->dev_aspm_mode == DEV_ASPM_BACKDOOR) {
|
||||
u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0;
|
||||
|
||||
val = 0;
|
||||
rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
|
||||
ASPM_MASK_NEG, val);
|
||||
val = FORCE_ASPM_CTL0;
|
||||
rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
|
||||
}
|
||||
val = 0;
|
||||
rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
|
||||
ASPM_MASK_NEG, val);
|
||||
rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
|
||||
udelay(10);
|
||||
pcr->aspm_enabled = enable;
|
||||
|
@ -789,7 +766,6 @@ void rts5261_init_params(struct rtsx_pcr *pcr)
|
|||
option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
|
||||
option->ltr_l1off_sspwrgate = 0x7F;
|
||||
option->ltr_l1off_snooze_sspwrgate = 0x78;
|
||||
option->dev_aspm_mode = DEV_ASPM_DYNAMIC;
|
||||
|
||||
option->ocp_en = 1;
|
||||
hw_param->interrupt_en |= SD_OC_INT_EN;
|
||||
|
|
|
@ -90,24 +90,13 @@ int rtsx_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency)
|
|||
|
||||
static void rtsx_comm_set_aspm(struct rtsx_pcr *pcr, bool enable)
|
||||
{
|
||||
struct rtsx_cr_option *option = &pcr->option;
|
||||
|
||||
if (pcr->aspm_enabled == enable)
|
||||
return;
|
||||
|
||||
if (option->dev_aspm_mode == DEV_ASPM_DYNAMIC) {
|
||||
if (enable)
|
||||
rtsx_pci_enable_aspm(pcr);
|
||||
else
|
||||
rtsx_pci_disable_aspm(pcr);
|
||||
} else if (option->dev_aspm_mode == DEV_ASPM_BACKDOOR) {
|
||||
u8 mask = FORCE_ASPM_VAL_MASK;
|
||||
u8 val = 0;
|
||||
|
||||
if (enable)
|
||||
val = pcr->aspm_en;
|
||||
rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
|
||||
}
|
||||
if (enable)
|
||||
rtsx_pci_enable_aspm(pcr);
|
||||
else
|
||||
rtsx_pci_disable_aspm(pcr);
|
||||
|
||||
pcr->aspm_enabled = enable;
|
||||
}
|
||||
|
|
|
@ -1104,13 +1104,6 @@ enum PDEV_STAT {PDEV_STAT_IDLE, PDEV_STAT_RUN};
|
|||
#define L1_SNOOZE_TEST_EN BIT(5)
|
||||
#define LTR_L1SS_PWR_GATE_CHECK_CARD_EN BIT(6)
|
||||
|
||||
enum dev_aspm_mode {
|
||||
DEV_ASPM_DYNAMIC,
|
||||
DEV_ASPM_BACKDOOR,
|
||||
DEV_ASPM_STATIC,
|
||||
DEV_ASPM_DISABLE,
|
||||
};
|
||||
|
||||
/*
|
||||
* struct rtsx_cr_option - card reader option
|
||||
* @dev_flags: device flags
|
||||
|
@ -1121,7 +1114,6 @@ enum dev_aspm_mode {
|
|||
* @ltr_active_latency: ltr mode active latency
|
||||
* @ltr_idle_latency: ltr mode idle latency
|
||||
* @ltr_l1off_latency: ltr mode l1off latency
|
||||
* @dev_aspm_mode: device aspm mode
|
||||
* @l1_snooze_delay: l1 snooze delay
|
||||
* @ltr_l1off_sspwrgate: ltr l1off sspwrgate
|
||||
* @ltr_l1off_snooze_sspwrgate: ltr l1off snooze sspwrgate
|
||||
|
@ -1138,7 +1130,6 @@ struct rtsx_cr_option {
|
|||
u32 ltr_active_latency;
|
||||
u32 ltr_idle_latency;
|
||||
u32 ltr_l1off_latency;
|
||||
enum dev_aspm_mode dev_aspm_mode;
|
||||
u32 l1_snooze_delay;
|
||||
u8 ltr_l1off_sspwrgate;
|
||||
u8 ltr_l1off_snooze_sspwrgate;
|
||||
|
|
Loading…
Reference in New Issue