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drm/i915: Push irq_shift from gen8_cs_irq_handler() to caller 

Originally we were inlining gen8_cs_irq_handler() and so expected the
compiler to constant-fold away the irq_shift (so we had hardcoded it as
opposed to use engine->irq_shift). However, we dropped the inline given
the proliferation of gen8_cs_irq_handler()s. If we pull the shifting
of the iir into the caller, we can shrink the code still further:

add/remove: 0/0 grow/shrink: 0/3 up/down: 0/-34 (-34)
Function                                     old     new   delta
gen8_cs_irq_handler                          123     118      -5
gen8_gt_irq_handler                          261     248     -13
gen11_irq_handler                            722     706     -16

v2: Drop gen11_cs_irq_handler now that it is a simple
stub around gen8_cs_irq_handler (Daniele)

References: 5d3d69d5c1 ("drm/i915: Stop inlining the execlists IRQ handler")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180309010808.11921-1-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson 2018-03-09 01:08:08 +00:00
parent d586b5f4cf
commit 51f6b0f99c
1 changed files with 16 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

38
drivers/gpu/drm/i915/i915_irq.c
View File

@ -1399,19 +1399,19 @@ static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
} }
static void static void
gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift) gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
{ {
struct intel_engine_execlists * const execlists = &engine->execlists; struct intel_engine_execlists * const execlists = &engine->execlists;
bool tasklet = false; bool tasklet = false;
if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift)) { if (iir & GT_CONTEXT_SWITCH_INTERRUPT) {
if (READ_ONCE(engine->execlists.active)) { if (READ_ONCE(engine->execlists.active)) {
__set_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); __set_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
tasklet = true; tasklet = true;
} }
} }
if (iir & (GT_RENDER_USER_INTERRUPT << test_shift)) { if (iir & GT_RENDER_USER_INTERRUPT) {
notify_ring(engine); notify_ring(engine);
tasklet |= USES_GUC_SUBMISSION(engine->i915); tasklet |= USES_GUC_SUBMISSION(engine->i915);
} }
@ -1466,21 +1466,21 @@ static void gen8_gt_irq_handler(struct drm_i915_private *i915,
{ {
if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
gen8_cs_irq_handler(i915->engine[RCS], gen8_cs_irq_handler(i915->engine[RCS],
gt_iir[0], GEN8_RCS_IRQ_SHIFT); gt_iir[0] >> GEN8_RCS_IRQ_SHIFT);
gen8_cs_irq_handler(i915->engine[BCS], gen8_cs_irq_handler(i915->engine[BCS],
gt_iir[0], GEN8_BCS_IRQ_SHIFT); gt_iir[0] >> GEN8_BCS_IRQ_SHIFT);
} }
if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) { if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
gen8_cs_irq_handler(i915->engine[VCS], gen8_cs_irq_handler(i915->engine[VCS],
gt_iir[1], GEN8_VCS1_IRQ_SHIFT); gt_iir[1] >> GEN8_VCS1_IRQ_SHIFT);
gen8_cs_irq_handler(i915->engine[VCS2], gen8_cs_irq_handler(i915->engine[VCS2],
gt_iir[1], GEN8_VCS2_IRQ_SHIFT); gt_iir[1] >> GEN8_VCS2_IRQ_SHIFT);
} }
if (master_ctl & GEN8_GT_VECS_IRQ) { if (master_ctl & GEN8_GT_VECS_IRQ) {
gen8_cs_irq_handler(i915->engine[VECS], gen8_cs_irq_handler(i915->engine[VECS],
gt_iir[3], GEN8_VECS_IRQ_SHIFT); gt_iir[3] >> GEN8_VECS_IRQ_SHIFT);
} }
if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) { if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
@ -2762,12 +2762,6 @@ static void __fini_wedge(struct wedge_me *w)
(W)->i915; \ (W)->i915; \
__fini_wedge((W))) __fini_wedge((W)))
static __always_inline void
gen11_cs_irq_handler(struct intel_engine_cs * const engine, const u32 iir)
{
gen8_cs_irq_handler(engine, iir, 0);
}
static void static void
gen11_gt_engine_irq_handler(struct drm_i915_private * const i915, gen11_gt_engine_irq_handler(struct drm_i915_private * const i915,
const unsigned int bank, const unsigned int bank,
@ -2781,27 +2775,27 @@ gen11_gt_engine_irq_handler(struct drm_i915_private * const i915,
switch (engine_n) { switch (engine_n) {
case GEN11_RCS0: case GEN11_RCS0:
return gen11_cs_irq_handler(engine[RCS], iir); return gen8_cs_irq_handler(engine[RCS], iir);
case GEN11_BCS: case GEN11_BCS:
return gen11_cs_irq_handler(engine[BCS], iir); return gen8_cs_irq_handler(engine[BCS], iir);
} }
case 1: case 1:
switch (engine_n) { switch (engine_n) {
case GEN11_VCS(0): case GEN11_VCS(0):
return gen11_cs_irq_handler(engine[_VCS(0)], iir); return gen8_cs_irq_handler(engine[_VCS(0)], iir);
case GEN11_VCS(1): case GEN11_VCS(1):
return gen11_cs_irq_handler(engine[_VCS(1)], iir); return gen8_cs_irq_handler(engine[_VCS(1)], iir);
case GEN11_VCS(2): case GEN11_VCS(2):
return gen11_cs_irq_handler(engine[_VCS(2)], iir); return gen8_cs_irq_handler(engine[_VCS(2)], iir);
case GEN11_VCS(3): case GEN11_VCS(3):
return gen11_cs_irq_handler(engine[_VCS(3)], iir); return gen8_cs_irq_handler(engine[_VCS(3)], iir);
case GEN11_VECS(0): case GEN11_VECS(0):
return gen11_cs_irq_handler(engine[_VECS(0)], iir); return gen8_cs_irq_handler(engine[_VECS(0)], iir);
case GEN11_VECS(1): case GEN11_VECS(1):
return gen11_cs_irq_handler(engine[_VECS(1)], iir); return gen8_cs_irq_handler(engine[_VECS(1)], iir);
} }
} }
} }