mirror of https://gitee.com/openkylin/linux.git
brcm80211: smac: remove enumeration rom parsing function
The core enumeration rom is already parsed by the bcma bus driver and there is no need to repeat the exercise. The ai_scan() function still exists but is targetted for removal as well. Reviewed-by: Pieter-Paul Giesberts <pieterpg@broadcom.com> Reviewed-by: Alwin Beukers <alwin@broadcom.com> Signed-off-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: Franky Lin <frankyl@broadcom.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Arend van Spriel
John W. Linville
parent
28a5344261
commit
5204563ab8
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@ -481,247 +481,27 @@ struct aidmp {
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u32 componentid3; /* 0xffc */
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};
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/* EROM parsing */
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static u32
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get_erom_ent(struct si_pub *sih, u32 __iomem **eromptr, u32 mask, u32 match)
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{
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u32 ent;
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uint inv = 0, nom = 0;
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while (true) {
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ent = R_REG(*eromptr);
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(*eromptr)++;
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if (mask == 0)
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break;
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if ((ent & ER_VALID) == 0) {
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inv++;
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continue;
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}
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if (ent == (ER_END | ER_VALID))
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break;
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if ((ent & mask) == match)
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break;
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nom++;
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}
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return ent;
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}
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static u32
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get_asd(struct si_pub *sih, u32 __iomem **eromptr, uint sp, uint ad, uint st,
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u32 *addrl, u32 *addrh, u32 *sizel, u32 *sizeh)
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{
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u32 asd, sz, szd;
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asd = get_erom_ent(sih, eromptr, ER_VALID, ER_VALID);
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if (((asd & ER_TAG1) != ER_ADD) ||
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(((asd & AD_SP_MASK) >> AD_SP_SHIFT) != sp) ||
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((asd & AD_ST_MASK) != st)) {
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/* This is not what we want, "push" it back */
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(*eromptr)--;
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return 0;
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}
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*addrl = asd & AD_ADDR_MASK;
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if (asd & AD_AG32)
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*addrh = get_erom_ent(sih, eromptr, 0, 0);
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else
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*addrh = 0;
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*sizeh = 0;
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sz = asd & AD_SZ_MASK;
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if (sz == AD_SZ_SZD) {
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szd = get_erom_ent(sih, eromptr, 0, 0);
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*sizel = szd & SD_SZ_MASK;
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if (szd & SD_SG32)
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*sizeh = get_erom_ent(sih, eromptr, 0, 0);
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} else
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*sizel = AD_SZ_BASE << (sz >> AD_SZ_SHIFT);
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return asd;
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}
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static void ai_hwfixup(struct si_info *sii)
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{
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}
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/* parse the enumeration rom to identify all cores */
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static void ai_scan(struct si_pub *sih, struct chipcregs __iomem *cc)
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static void ai_scan(struct si_pub *sih, struct bcma_bus *bus)
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{
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struct si_info *sii = (struct si_info *)sih;
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struct bcma_device *core;
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uint idx;
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u32 erombase;
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u32 __iomem *eromptr, *eromlim;
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void __iomem *regs = cc;
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erombase = R_REG(&cc->eromptr);
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/* Set wrappers address */
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sii->curwrap = (void *)((unsigned long)cc + SI_CORE_SIZE);
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/* Now point the window at the erom */
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pci_write_config_dword(sii->pcibus, PCI_BAR0_WIN, erombase);
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eromptr = regs;
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eromlim = eromptr + (ER_REMAPCONTROL / sizeof(u32));
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while (eromptr < eromlim) {
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u32 cia, cib, cid, mfg, crev, nmw, nsw, nmp, nsp;
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u32 mpd, asd, addrl, addrh, sizel, sizeh;
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u32 __iomem *base;
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uint i, j, idx;
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bool br;
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br = false;
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/* Grok a component */
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cia = get_erom_ent(sih, &eromptr, ER_TAG, ER_CI);
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if (cia == (ER_END | ER_VALID)) {
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/* Found END of erom */
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ai_hwfixup(sii);
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return;
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}
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base = eromptr - 1;
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cib = get_erom_ent(sih, &eromptr, 0, 0);
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if ((cib & ER_TAG) != ER_CI) {
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/* CIA not followed by CIB */
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goto error;
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}
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cid = (cia & CIA_CID_MASK) >> CIA_CID_SHIFT;
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mfg = (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
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crev = (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
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nmw = (cib & CIB_NMW_MASK) >> CIB_NMW_SHIFT;
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nsw = (cib & CIB_NSW_MASK) >> CIB_NSW_SHIFT;
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nmp = (cib & CIB_NMP_MASK) >> CIB_NMP_SHIFT;
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nsp = (cib & CIB_NSP_MASK) >> CIB_NSP_SHIFT;
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if (((mfg == MFGID_ARM) && (cid == DEF_AI_COMP)) || (nsp == 0))
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continue;
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if ((nmw + nsw == 0)) {
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/* A component which is not a core */
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if (cid == OOB_ROUTER_CORE_ID) {
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asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE,
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&addrl, &addrh, &sizel, &sizeh);
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if (asd != 0)
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sii->oob_router = addrl;
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}
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continue;
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}
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idx = sii->numcores;
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/* sii->eromptr[idx] = base; */
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sii->cia[idx] = cia;
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sii->cib[idx] = cib;
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sii->coreid[idx] = cid;
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for (i = 0; i < nmp; i++) {
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mpd = get_erom_ent(sih, &eromptr, ER_VALID, ER_VALID);
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if ((mpd & ER_TAG) != ER_MP) {
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/* Not enough MP entries for component */
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goto error;
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}
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}
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/* First Slave Address Descriptor should be port 0:
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* the main register space for the core
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*/
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asd =
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get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE, &addrl, &addrh,
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&sizel, &sizeh);
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if (asd == 0) {
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/* Try again to see if it is a bridge */
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asd =
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get_asd(sih, &eromptr, 0, 0, AD_ST_BRIDGE, &addrl,
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&addrh, &sizel, &sizeh);
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if (asd != 0)
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br = true;
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else if ((addrh != 0) || (sizeh != 0)
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|| (sizel != SI_CORE_SIZE)) {
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/* First Slave ASD for core malformed */
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goto error;
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}
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}
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sii->coresba[idx] = addrl;
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sii->coresba_size[idx] = sizel;
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/* Get any more ASDs in port 0 */
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j = 1;
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do {
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asd =
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get_asd(sih, &eromptr, 0, j, AD_ST_SLAVE, &addrl,
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&addrh, &sizel, &sizeh);
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if ((asd != 0) && (j == 1) && (sizel == SI_CORE_SIZE)) {
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sii->coresba2[idx] = addrl;
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sii->coresba2_size[idx] = sizel;
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}
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j++;
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} while (asd != 0);
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/* Go through the ASDs for other slave ports */
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for (i = 1; i < nsp; i++) {
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j = 0;
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do {
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asd =
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get_asd(sih, &eromptr, i, j++, AD_ST_SLAVE,
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&addrl, &addrh, &sizel, &sizeh);
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} while (asd != 0);
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if (j == 0) {
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/* SP has no address descriptors */
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goto error;
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}
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}
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/* Now get master wrappers */
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for (i = 0; i < nmw; i++) {
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asd =
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get_asd(sih, &eromptr, i, 0, AD_ST_MWRAP, &addrl,
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&addrh, &sizel, &sizeh);
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if (asd == 0) {
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/* Missing descriptor for MW */
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goto error;
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}
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if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
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/* Master wrapper %d is not 4KB */
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goto error;
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}
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if (i == 0)
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sii->wrapba[idx] = addrl;
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}
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/* And finally slave wrappers */
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for (i = 0; i < nsw; i++) {
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uint fwp = (nsp == 1) ? 0 : 1;
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asd =
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get_asd(sih, &eromptr, fwp + i, 0, AD_ST_SWRAP,
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&addrl, &addrh, &sizel, &sizeh);
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if (asd == 0) {
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/* Missing descriptor for SW */
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goto error;
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}
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if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
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/* Slave wrapper is not 4KB */
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goto error;
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}
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if ((nmw == 0) && (i == 0))
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sii->wrapba[idx] = addrl;
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}
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/* Don't record bridges */
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if (br)
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continue;
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/* Done with core */
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list_for_each_entry(core, &bus->cores, list) {
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idx = core->core_index;
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sii->cia[idx] = core->id.manuf << CIA_MFG_SHIFT;
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sii->cia[idx] |= core->id.id << CIA_CID_SHIFT;
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sii->cia[idx] |= core->id.class << CIA_CCL_SHIFT;
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sii->cib[idx] = core->id.rev << CIB_REV_SHIFT;
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sii->coreid[idx] = core->id.id;
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sii->coresba[idx] = core->addr;
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sii->coresba_size[idx] = 0x1000;
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sii->coresba2[idx] = 0;
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sii->coresba2_size[idx] = 0;
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sii->wrapba[idx] = core->wrap;
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sii->numcores++;
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}
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error:
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/* Reached end of erom without finding END */
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sii->numcores = 0;
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return;
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}
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/*
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@ -1039,8 +819,9 @@ static struct si_info *ai_doattach(struct si_info *sii,
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sii->icbus = pbus;
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sii->buscoreidx = BADIDX;
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sii->curmap = regs;
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sii->pcibus = pbus->host_pci;
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sii->curmap = regs;
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sii->curwrap = sii->curmap + SI_CORE_SIZE;
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/* find Chipcommon address */
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pci_read_config_dword(sii->pcibus, PCI_BAR0_WIN, &savewin);
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@ -1073,7 +854,7 @@ static struct si_info *ai_doattach(struct si_info *sii,
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if (socitype == SOCI_AI) {
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SI_MSG("Found chip type AI (0x%08x)\n", w);
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/* pass chipc address instead of original core base */
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ai_scan(&sii->pub, cc);
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ai_scan(&sii->pub, pbus);
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} else {
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/* Found chip of unknown type */
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return NULL;
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