drm/i915/icl: Wa_1604302699

Disable I2M Write for performance reasons.

v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
v4:
  - Rebased
  - C, not lisp (Chris)
  - GEN7 chicken bit in the wrong side of the fence (Mika)
  - Use two spaces to align bit macros

References: HSDES#1604302699
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1525814984-20039-12-git-send-email-oscar.mateo@intel.com
This commit is contained in:
Oscar Mateo 2018-05-08 14:29:33 -07:00 committed by Mika Kuoppala
parent 36204d80ba
commit 5215eef35f
2 changed files with 8 additions and 1 deletions

View File

@ -7227,7 +7227,9 @@ enum {
#define GEN7_L3CNTLREG3 _MMIO(0xB024)
#define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xB030)
#define GEN7_WA_L3_CHICKEN_MODE 0x20000000
#define GEN7_WA_L3_CHICKEN_MODE 0x20000000
#define GEN10_L3_CHICKEN_MODE_REGISTER _MMIO(0xB114)
#define GEN11_I2M_WRITE_DISABLE (1 << 28)
#define GEN7_L3SQCREG4 _MMIO(0xb034)
#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)

View File

@ -750,6 +750,11 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE,
I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE) |
GWUNIT_CLKGATE_DIS);
/* Wa_1604302699:icl */
I915_WRITE(GEN10_L3_CHICKEN_MODE_REGISTER,
I915_READ(GEN10_L3_CHICKEN_MODE_REGISTER) |
GEN11_I2M_WRITE_DISABLE);
}
void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)