mirror of https://gitee.com/openkylin/linux.git
dma-mapping updates for 4.14:
- removal of the old dma_alloc_noncoherent interface - remove unused flags to dma_declare_coherent_memory - restrict OF DMA configuration to specific physical busses - use the iommu mailing list for dma-mapping questions and patches -----BEGIN PGP SIGNATURE----- iQI/BAABCAApFiEEgdbnc3r/njty3Iq9D55TZVIEUYMFAlm38VMLHGhjaEBsc3Qu ZGUACgkQD55TZVIEUYNa+BAAjlTbZ2DhEmBDKHDYjQepnqdw7oY/5B/6A3GKArbR psXDmWR8HetbJC1+Yg2aaCvSWdza9cR36juI4WSsA2+4FVLU0nj5elkX9QEN/eP4 kiUuwUXCKi3MNd55ESIiVQos0RKvQ8us7rLDfug2h/8dVP5EdLNI//axHY4Y/R7k 6j6ymal9QdHxLj8wdkAQ332womV2jQH44ISIy/Eu/eF1DmWJ1HZvgO/PNeSyVpwB bP8CRfMAnQDFqB0XiwCXyukNKntvBe7ZpazMdQKH6bObiLOa8DT2Ex/UeG6VBtb3 TXeLW9aSJDG9FfzlqwDlySZWqQlvcEEK7DWm7kNka9tiHx+AKZW+utlrS7Pvofut ufqD9NRrmutBzgXsZiri/x9b5+UsREKsdHNyLHVfjYo9PlEsZwMjaXxExAlEdgvl L0pU4EpLP8kK5pRV5K8IXCEVMyoejI2ZIrtu5DHlc3mblUApXkKx1TG81gJsncHh fDLARilSgCN6g8wQjSiBiXwS6ynBRcmvpeIxrh3x7xQ7OqmqDMS5JcgJCNvBQEKm yEMCKd8vf30Jpva3VRmQXyUiDMwebguUqSJUDJW0JeDFFGQ7O39JeOwB72LzVHjZ N9VMh3gCvtkF2ZPV+HIPNbTFnfydzyjNW/BpGt4r5cyvfd2TjEDSPFeIOWZ+chVQ j68= =qHNs -----END PGP SIGNATURE----- Merge tag 'dma-mapping-4.14' of git://git.infradead.org/users/hch/dma-mapping Pull dma-mapping updates from Christoph Hellwig: - removal of the old dma_alloc_noncoherent interface - remove unused flags to dma_declare_coherent_memory - restrict OF DMA configuration to specific physical busses - use the iommu mailing list for dma-mapping questions and patches * tag 'dma-mapping-4.14' of git://git.infradead.org/users/hch/dma-mapping: dma-coherent: fix dma_declare_coherent_memory() logic error ARM: imx: mx31moboard: Remove unused 'dma' variable dma-coherent: remove an unused variable MAINTAINERS: use the iommu list for the dma-mapping subsystem dma-coherent: remove the DMA_MEMORY_MAP and DMA_MEMORY_IO flags dma-coherent: remove the DMA_MEMORY_INCLUDES_CHILDREN flag of: restrict DMA configuration dma-mapping: remove dma_alloc_noncoherent and dma_free_noncoherent i825xx: switch to switch to dma_alloc_attrs au1000_eth: switch to dma_alloc_attrs sgiseeq: switch to dma_alloc_attrs dma-mapping: reduce dma_mapping_error inline bloat
This commit is contained in:
commit
52269718dc
|
@ -515,14 +515,15 @@ API at all.
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::
|
::
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||||||
|
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void *
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void *
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dma_alloc_noncoherent(struct device *dev, size_t size,
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dma_alloc_attrs(struct device *dev, size_t size, dma_addr_t *dma_handle,
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dma_addr_t *dma_handle, gfp_t flag)
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gfp_t flag, unsigned long attrs)
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|
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Identical to dma_alloc_coherent() except that the platform will
|
Identical to dma_alloc_coherent() except that when the
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choose to return either consistent or non-consistent memory as it sees
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DMA_ATTR_NON_CONSISTENT flags is passed in the attrs argument, the
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fit. By using this API, you are guaranteeing to the platform that you
|
platform will choose to return either consistent or non-consistent memory
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have all the correct and necessary sync points for this memory in the
|
as it sees fit. By using this API, you are guaranteeing to the platform
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driver should it choose to return non-consistent memory.
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that you have all the correct and necessary sync points for this memory
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|
in the driver should it choose to return non-consistent memory.
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|
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Note: where the platform can return consistent memory, it will
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Note: where the platform can return consistent memory, it will
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guarantee that the sync points become nops.
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guarantee that the sync points become nops.
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@ -535,12 +536,13 @@ that simply cannot make consistent memory.
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::
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::
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|
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void
|
void
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dma_free_noncoherent(struct device *dev, size_t size, void *cpu_addr,
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dma_free_attrs(struct device *dev, size_t size, void *cpu_addr,
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dma_addr_t dma_handle)
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dma_addr_t dma_handle, unsigned long attrs)
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|
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Free memory allocated by the nonconsistent API. All parameters must
|
Free memory allocated by the dma_alloc_attrs(). All parameters common
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be identical to those passed in (and returned by
|
parameters must identical to those otherwise passed to dma_fre_coherent,
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dma_alloc_noncoherent()).
|
and the attrs argument must be identical to the attrs passed to
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|
dma_alloc_attrs().
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|
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::
|
::
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|
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|
@ -564,8 +566,8 @@ memory or doing partial flushes.
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dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction direction)
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enum dma_data_direction direction)
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|
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Do a partial sync of memory that was allocated by
|
Do a partial sync of memory that was allocated by dma_alloc_attrs() with
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dma_alloc_noncoherent(), starting at virtual address vaddr and
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the DMA_ATTR_NON_CONSISTENT flag starting at virtual address vaddr and
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continuing on for size. Again, you *must* observe the cache line
|
continuing on for size. Again, you *must* observe the cache line
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boundaries when doing this.
|
boundaries when doing this.
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|
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|
@ -590,34 +592,11 @@ size is the size of the area (must be multiples of PAGE_SIZE).
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|
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flags can be ORed together and are:
|
flags can be ORed together and are:
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|
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- DMA_MEMORY_MAP - request that the memory returned from
|
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dma_alloc_coherent() be directly writable.
|
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|
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- DMA_MEMORY_IO - request that the memory returned from
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dma_alloc_coherent() be addressable using read()/write()/memcpy_toio() etc.
|
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|
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One or both of these flags must be present.
|
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|
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- DMA_MEMORY_INCLUDES_CHILDREN - make the declared memory be allocated by
|
|
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dma_alloc_coherent of any child devices of this one (for memory residing
|
|
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on a bridge).
|
|
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|
|
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- DMA_MEMORY_EXCLUSIVE - only allocate memory from the declared regions.
|
- DMA_MEMORY_EXCLUSIVE - only allocate memory from the declared regions.
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Do not allow dma_alloc_coherent() to fall back to system memory when
|
Do not allow dma_alloc_coherent() to fall back to system memory when
|
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it's out of memory in the declared region.
|
it's out of memory in the declared region.
|
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|
|
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The return value will be either DMA_MEMORY_MAP or DMA_MEMORY_IO and
|
As a simplification for the platforms, only *one* such region of
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must correspond to a passed in flag (i.e. no returning DMA_MEMORY_IO
|
|
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if only DMA_MEMORY_MAP were passed in) for success or zero for
|
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failure.
|
|
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|
|
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Note, for DMA_MEMORY_IO returns, all subsequent memory returned by
|
|
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dma_alloc_coherent() may no longer be accessed directly, but instead
|
|
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must be accessed using the correct bus functions. If your driver
|
|
||||||
isn't prepared to handle this contingency, it should not specify
|
|
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DMA_MEMORY_IO in the input flags.
|
|
||||||
|
|
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As a simplification for the platforms, only **one** such region of
|
|
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memory may be declared per device.
|
memory may be declared per device.
|
||||||
|
|
||||||
For reasons of efficiency, most platforms choose to track the declared
|
For reasons of efficiency, most platforms choose to track the declared
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|
|
|
@ -4219,7 +4219,7 @@ DMA MAPPING HELPERS
|
||||||
M: Christoph Hellwig <hch@lst.de>
|
M: Christoph Hellwig <hch@lst.de>
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M: Marek Szyprowski <m.szyprowski@samsung.com>
|
M: Marek Szyprowski <m.szyprowski@samsung.com>
|
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R: Robin Murphy <robin.murphy@arm.com>
|
R: Robin Murphy <robin.murphy@arm.com>
|
||||||
L: linux-kernel@vger.kernel.org
|
L: iommu@lists.linux-foundation.org
|
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T: git git://git.infradead.org/users/hch/dma-mapping.git
|
T: git git://git.infradead.org/users/hch/dma-mapping.git
|
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W: http://git.infradead.org/users/hch/dma-mapping.git
|
W: http://git.infradead.org/users/hch/dma-mapping.git
|
||||||
S: Supported
|
S: Supported
|
||||||
|
|
|
@ -245,7 +245,6 @@ static phys_addr_t mx2_camera_base __initdata;
|
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static void __init visstrim_analog_camera_init(void)
|
static void __init visstrim_analog_camera_init(void)
|
||||||
{
|
{
|
||||||
struct platform_device *pdev;
|
struct platform_device *pdev;
|
||||||
int dma;
|
|
||||||
|
|
||||||
gpio_set_value(TVP5150_PWDN, 1);
|
gpio_set_value(TVP5150_PWDN, 1);
|
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ndelay(1);
|
ndelay(1);
|
||||||
|
@ -258,12 +257,9 @@ static void __init visstrim_analog_camera_init(void)
|
||||||
if (IS_ERR(pdev))
|
if (IS_ERR(pdev))
|
||||||
return;
|
return;
|
||||||
|
|
||||||
dma = dma_declare_coherent_memory(&pdev->dev,
|
dma_declare_coherent_memory(&pdev->dev, mx2_camera_base,
|
||||||
mx2_camera_base, mx2_camera_base,
|
mx2_camera_base, MX2_CAMERA_BUF_SIZE,
|
||||||
MX2_CAMERA_BUF_SIZE,
|
DMA_MEMORY_EXCLUSIVE);
|
||||||
DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
|
|
||||||
if (!(dma & DMA_MEMORY_MAP))
|
|
||||||
return;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static void __init visstrim_reserve(void)
|
static void __init visstrim_reserve(void)
|
||||||
|
@ -444,16 +440,13 @@ static const struct imx_ssi_platform_data visstrim_m10_ssi_pdata __initconst = {
|
||||||
static void __init visstrim_coda_init(void)
|
static void __init visstrim_coda_init(void)
|
||||||
{
|
{
|
||||||
struct platform_device *pdev;
|
struct platform_device *pdev;
|
||||||
int dma;
|
|
||||||
|
|
||||||
pdev = imx27_add_coda();
|
pdev = imx27_add_coda();
|
||||||
dma = dma_declare_coherent_memory(&pdev->dev,
|
dma_declare_coherent_memory(&pdev->dev,
|
||||||
mx2_camera_base + MX2_CAMERA_BUF_SIZE,
|
mx2_camera_base + MX2_CAMERA_BUF_SIZE,
|
||||||
mx2_camera_base + MX2_CAMERA_BUF_SIZE,
|
mx2_camera_base + MX2_CAMERA_BUF_SIZE,
|
||||||
MX2_CAMERA_BUF_SIZE,
|
MX2_CAMERA_BUF_SIZE,
|
||||||
DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
|
DMA_MEMORY_EXCLUSIVE);
|
||||||
if (!(dma & DMA_MEMORY_MAP))
|
|
||||||
return;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/* DMA deinterlace */
|
/* DMA deinterlace */
|
||||||
|
@ -466,24 +459,21 @@ static void __init visstrim_deinterlace_init(void)
|
||||||
{
|
{
|
||||||
int ret = -ENOMEM;
|
int ret = -ENOMEM;
|
||||||
struct platform_device *pdev = &visstrim_deinterlace;
|
struct platform_device *pdev = &visstrim_deinterlace;
|
||||||
int dma;
|
|
||||||
|
|
||||||
ret = platform_device_register(pdev);
|
ret = platform_device_register(pdev);
|
||||||
|
|
||||||
dma = dma_declare_coherent_memory(&pdev->dev,
|
dma_declare_coherent_memory(&pdev->dev,
|
||||||
mx2_camera_base + 2 * MX2_CAMERA_BUF_SIZE,
|
mx2_camera_base + 2 * MX2_CAMERA_BUF_SIZE,
|
||||||
mx2_camera_base + 2 * MX2_CAMERA_BUF_SIZE,
|
mx2_camera_base + 2 * MX2_CAMERA_BUF_SIZE,
|
||||||
MX2_CAMERA_BUF_SIZE,
|
MX2_CAMERA_BUF_SIZE,
|
||||||
DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
|
DMA_MEMORY_EXCLUSIVE);
|
||||||
if (!(dma & DMA_MEMORY_MAP))
|
|
||||||
return;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Emma-PrP for format conversion */
|
/* Emma-PrP for format conversion */
|
||||||
static void __init visstrim_emmaprp_init(void)
|
static void __init visstrim_emmaprp_init(void)
|
||||||
{
|
{
|
||||||
struct platform_device *pdev;
|
struct platform_device *pdev;
|
||||||
int dma;
|
int ret;
|
||||||
|
|
||||||
pdev = imx27_add_mx2_emmaprp();
|
pdev = imx27_add_mx2_emmaprp();
|
||||||
if (IS_ERR(pdev))
|
if (IS_ERR(pdev))
|
||||||
|
@ -493,11 +483,11 @@ static void __init visstrim_emmaprp_init(void)
|
||||||
* Use the same memory area as the analog camera since both
|
* Use the same memory area as the analog camera since both
|
||||||
* devices are, by nature, exclusive.
|
* devices are, by nature, exclusive.
|
||||||
*/
|
*/
|
||||||
dma = dma_declare_coherent_memory(&pdev->dev,
|
ret = dma_declare_coherent_memory(&pdev->dev,
|
||||||
mx2_camera_base, mx2_camera_base,
|
mx2_camera_base, mx2_camera_base,
|
||||||
MX2_CAMERA_BUF_SIZE,
|
MX2_CAMERA_BUF_SIZE,
|
||||||
DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
|
DMA_MEMORY_EXCLUSIVE);
|
||||||
if (!(dma & DMA_MEMORY_MAP))
|
if (ret)
|
||||||
pr_err("Failed to declare memory for emmaprp\n");
|
pr_err("Failed to declare memory for emmaprp\n");
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -475,7 +475,7 @@ static phys_addr_t mx3_camera_base __initdata;
|
||||||
|
|
||||||
static int __init mx31moboard_init_cam(void)
|
static int __init mx31moboard_init_cam(void)
|
||||||
{
|
{
|
||||||
int dma, ret = -ENOMEM;
|
int ret;
|
||||||
struct platform_device *pdev;
|
struct platform_device *pdev;
|
||||||
|
|
||||||
imx31_add_ipu_core();
|
imx31_add_ipu_core();
|
||||||
|
@ -484,11 +484,11 @@ static int __init mx31moboard_init_cam(void)
|
||||||
if (IS_ERR(pdev))
|
if (IS_ERR(pdev))
|
||||||
return PTR_ERR(pdev);
|
return PTR_ERR(pdev);
|
||||||
|
|
||||||
dma = dma_declare_coherent_memory(&pdev->dev,
|
ret = dma_declare_coherent_memory(&pdev->dev,
|
||||||
mx3_camera_base, mx3_camera_base,
|
mx3_camera_base, mx3_camera_base,
|
||||||
MX3_CAMERA_BUF_SIZE,
|
MX3_CAMERA_BUF_SIZE,
|
||||||
DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
|
DMA_MEMORY_EXCLUSIVE);
|
||||||
if (!(dma & DMA_MEMORY_MAP))
|
if (ret)
|
||||||
goto err;
|
goto err;
|
||||||
|
|
||||||
ret = platform_device_add(pdev);
|
ret = platform_device_add(pdev);
|
||||||
|
|
|
@ -9,7 +9,7 @@ static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* dma_alloc_noncoherent() returns non-cacheable memory, so there's no need to
|
* dma_alloc_attrs() always returns non-cacheable memory, so there's no need to
|
||||||
* do any flushing here.
|
* do any flushing here.
|
||||||
*/
|
*/
|
||||||
static inline void
|
static inline void
|
||||||
|
|
|
@ -18,7 +18,7 @@ static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* dma_alloc_noncoherent() returns non-cacheable memory, so there's no need to
|
* dma_alloc_attrs() always returns non-cacheable memory, so there's no need to
|
||||||
* do any flushing here.
|
* do any flushing here.
|
||||||
*/
|
*/
|
||||||
static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
|
static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
|
||||||
|
|
|
@ -63,11 +63,10 @@ static void gapspci_fixup_resources(struct pci_dev *dev)
|
||||||
res.end = GAPSPCI_DMA_BASE + GAPSPCI_DMA_SIZE - 1;
|
res.end = GAPSPCI_DMA_BASE + GAPSPCI_DMA_SIZE - 1;
|
||||||
res.flags = IORESOURCE_MEM;
|
res.flags = IORESOURCE_MEM;
|
||||||
pcibios_resource_to_bus(dev->bus, ®ion, &res);
|
pcibios_resource_to_bus(dev->bus, ®ion, &res);
|
||||||
BUG_ON(!dma_declare_coherent_memory(&dev->dev,
|
BUG_ON(dma_declare_coherent_memory(&dev->dev,
|
||||||
res.start,
|
res.start,
|
||||||
region.start,
|
region.start,
|
||||||
resource_size(&res),
|
resource_size(&res),
|
||||||
DMA_MEMORY_MAP |
|
|
||||||
DMA_MEMORY_EXCLUSIVE));
|
DMA_MEMORY_EXCLUSIVE));
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
|
|
|
@ -68,8 +68,8 @@ static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
|
||||||
int dma_set_mask(struct device *dev, u64 mask);
|
int dma_set_mask(struct device *dev, u64 mask);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* dma_alloc_noncoherent() is #defined to return coherent memory,
|
* dma_alloc_attrs() always returns non-cacheable memory, so there's no need to
|
||||||
* so there's no need to do any flushing here.
|
* do any flushing here.
|
||||||
*/
|
*/
|
||||||
static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
|
static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
|
||||||
enum dma_data_direction direction)
|
enum dma_data_direction direction)
|
||||||
|
|
|
@ -37,7 +37,7 @@ static inline dma_addr_t dma_get_device_base(struct device *dev,
|
||||||
return mem->device_base;
|
return mem->device_base;
|
||||||
}
|
}
|
||||||
|
|
||||||
static bool dma_init_coherent_memory(
|
static int dma_init_coherent_memory(
|
||||||
phys_addr_t phys_addr, dma_addr_t device_addr, size_t size, int flags,
|
phys_addr_t phys_addr, dma_addr_t device_addr, size_t size, int flags,
|
||||||
struct dma_coherent_mem **mem)
|
struct dma_coherent_mem **mem)
|
||||||
{
|
{
|
||||||
|
@ -45,25 +45,28 @@ static bool dma_init_coherent_memory(
|
||||||
void __iomem *mem_base = NULL;
|
void __iomem *mem_base = NULL;
|
||||||
int pages = size >> PAGE_SHIFT;
|
int pages = size >> PAGE_SHIFT;
|
||||||
int bitmap_size = BITS_TO_LONGS(pages) * sizeof(long);
|
int bitmap_size = BITS_TO_LONGS(pages) * sizeof(long);
|
||||||
|
int ret;
|
||||||
|
|
||||||
if ((flags & (DMA_MEMORY_MAP | DMA_MEMORY_IO)) == 0)
|
if (!size) {
|
||||||
goto out;
|
ret = -EINVAL;
|
||||||
if (!size)
|
|
||||||
goto out;
|
goto out;
|
||||||
|
}
|
||||||
|
|
||||||
if (flags & DMA_MEMORY_MAP)
|
mem_base = memremap(phys_addr, size, MEMREMAP_WC);
|
||||||
mem_base = memremap(phys_addr, size, MEMREMAP_WC);
|
if (!mem_base) {
|
||||||
else
|
ret = -EINVAL;
|
||||||
mem_base = ioremap(phys_addr, size);
|
|
||||||
if (!mem_base)
|
|
||||||
goto out;
|
goto out;
|
||||||
|
}
|
||||||
dma_mem = kzalloc(sizeof(struct dma_coherent_mem), GFP_KERNEL);
|
dma_mem = kzalloc(sizeof(struct dma_coherent_mem), GFP_KERNEL);
|
||||||
if (!dma_mem)
|
if (!dma_mem) {
|
||||||
|
ret = -ENOMEM;
|
||||||
goto out;
|
goto out;
|
||||||
|
}
|
||||||
dma_mem->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
|
dma_mem->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
|
||||||
if (!dma_mem->bitmap)
|
if (!dma_mem->bitmap) {
|
||||||
|
ret = -ENOMEM;
|
||||||
goto out;
|
goto out;
|
||||||
|
}
|
||||||
|
|
||||||
dma_mem->virt_base = mem_base;
|
dma_mem->virt_base = mem_base;
|
||||||
dma_mem->device_base = device_addr;
|
dma_mem->device_base = device_addr;
|
||||||
|
@ -73,17 +76,13 @@ static bool dma_init_coherent_memory(
|
||||||
spin_lock_init(&dma_mem->spinlock);
|
spin_lock_init(&dma_mem->spinlock);
|
||||||
|
|
||||||
*mem = dma_mem;
|
*mem = dma_mem;
|
||||||
return true;
|
return 0;
|
||||||
|
|
||||||
out:
|
out:
|
||||||
kfree(dma_mem);
|
kfree(dma_mem);
|
||||||
if (mem_base) {
|
if (mem_base)
|
||||||
if (flags & DMA_MEMORY_MAP)
|
memunmap(mem_base);
|
||||||
memunmap(mem_base);
|
return ret;
|
||||||
else
|
|
||||||
iounmap(mem_base);
|
|
||||||
}
|
|
||||||
return false;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static void dma_release_coherent_memory(struct dma_coherent_mem *mem)
|
static void dma_release_coherent_memory(struct dma_coherent_mem *mem)
|
||||||
|
@ -91,10 +90,7 @@ static void dma_release_coherent_memory(struct dma_coherent_mem *mem)
|
||||||
if (!mem)
|
if (!mem)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
if (mem->flags & DMA_MEMORY_MAP)
|
memunmap(mem->virt_base);
|
||||||
memunmap(mem->virt_base);
|
|
||||||
else
|
|
||||||
iounmap(mem->virt_base);
|
|
||||||
kfree(mem->bitmap);
|
kfree(mem->bitmap);
|
||||||
kfree(mem);
|
kfree(mem);
|
||||||
}
|
}
|
||||||
|
@ -109,8 +105,6 @@ static int dma_assign_coherent_memory(struct device *dev,
|
||||||
return -EBUSY;
|
return -EBUSY;
|
||||||
|
|
||||||
dev->dma_mem = mem;
|
dev->dma_mem = mem;
|
||||||
/* FIXME: this routine just ignores DMA_MEMORY_INCLUDES_CHILDREN */
|
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -118,16 +112,16 @@ int dma_declare_coherent_memory(struct device *dev, phys_addr_t phys_addr,
|
||||||
dma_addr_t device_addr, size_t size, int flags)
|
dma_addr_t device_addr, size_t size, int flags)
|
||||||
{
|
{
|
||||||
struct dma_coherent_mem *mem;
|
struct dma_coherent_mem *mem;
|
||||||
|
int ret;
|
||||||
|
|
||||||
if (!dma_init_coherent_memory(phys_addr, device_addr, size, flags,
|
ret = dma_init_coherent_memory(phys_addr, device_addr, size, flags, &mem);
|
||||||
&mem))
|
if (ret)
|
||||||
return 0;
|
return ret;
|
||||||
|
|
||||||
if (dma_assign_coherent_memory(dev, mem) == 0)
|
ret = dma_assign_coherent_memory(dev, mem);
|
||||||
return flags & DMA_MEMORY_MAP ? DMA_MEMORY_MAP : DMA_MEMORY_IO;
|
if (ret)
|
||||||
|
dma_release_coherent_memory(mem);
|
||||||
dma_release_coherent_memory(mem);
|
return ret;
|
||||||
return 0;
|
|
||||||
}
|
}
|
||||||
EXPORT_SYMBOL(dma_declare_coherent_memory);
|
EXPORT_SYMBOL(dma_declare_coherent_memory);
|
||||||
|
|
||||||
|
@ -171,7 +165,6 @@ static void *__dma_alloc_from_coherent(struct dma_coherent_mem *mem,
|
||||||
int order = get_order(size);
|
int order = get_order(size);
|
||||||
unsigned long flags;
|
unsigned long flags;
|
||||||
int pageno;
|
int pageno;
|
||||||
int dma_memory_map;
|
|
||||||
void *ret;
|
void *ret;
|
||||||
|
|
||||||
spin_lock_irqsave(&mem->spinlock, flags);
|
spin_lock_irqsave(&mem->spinlock, flags);
|
||||||
|
@ -188,15 +181,9 @@ static void *__dma_alloc_from_coherent(struct dma_coherent_mem *mem,
|
||||||
*/
|
*/
|
||||||
*dma_handle = mem->device_base + (pageno << PAGE_SHIFT);
|
*dma_handle = mem->device_base + (pageno << PAGE_SHIFT);
|
||||||
ret = mem->virt_base + (pageno << PAGE_SHIFT);
|
ret = mem->virt_base + (pageno << PAGE_SHIFT);
|
||||||
dma_memory_map = (mem->flags & DMA_MEMORY_MAP);
|
|
||||||
spin_unlock_irqrestore(&mem->spinlock, flags);
|
spin_unlock_irqrestore(&mem->spinlock, flags);
|
||||||
if (dma_memory_map)
|
memset(ret, 0, size);
|
||||||
memset(ret, 0, size);
|
|
||||||
else
|
|
||||||
memset_io(ret, 0, size);
|
|
||||||
|
|
||||||
return ret;
|
return ret;
|
||||||
|
|
||||||
err:
|
err:
|
||||||
spin_unlock_irqrestore(&mem->spinlock, flags);
|
spin_unlock_irqrestore(&mem->spinlock, flags);
|
||||||
return NULL;
|
return NULL;
|
||||||
|
@ -359,14 +346,18 @@ static struct reserved_mem *dma_reserved_default_memory __initdata;
|
||||||
static int rmem_dma_device_init(struct reserved_mem *rmem, struct device *dev)
|
static int rmem_dma_device_init(struct reserved_mem *rmem, struct device *dev)
|
||||||
{
|
{
|
||||||
struct dma_coherent_mem *mem = rmem->priv;
|
struct dma_coherent_mem *mem = rmem->priv;
|
||||||
|
int ret;
|
||||||
|
|
||||||
if (!mem &&
|
if (!mem)
|
||||||
!dma_init_coherent_memory(rmem->base, rmem->base, rmem->size,
|
return -ENODEV;
|
||||||
DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE,
|
|
||||||
&mem)) {
|
ret = dma_init_coherent_memory(rmem->base, rmem->base, rmem->size,
|
||||||
|
DMA_MEMORY_EXCLUSIVE, &mem);
|
||||||
|
|
||||||
|
if (ret) {
|
||||||
pr_err("Reserved memory: failed to init DMA memory pool at %pa, size %ld MiB\n",
|
pr_err("Reserved memory: failed to init DMA memory pool at %pa, size %ld MiB\n",
|
||||||
&rmem->base, (unsigned long)rmem->size / SZ_1M);
|
&rmem->base, (unsigned long)rmem->size / SZ_1M);
|
||||||
return -ENODEV;
|
return ret;
|
||||||
}
|
}
|
||||||
mem->use_dev_dma_pfn_offset = true;
|
mem->use_dev_dma_pfn_offset = true;
|
||||||
rmem->priv = mem;
|
rmem->priv = mem;
|
||||||
|
|
|
@ -176,13 +176,10 @@ int dmam_declare_coherent_memory(struct device *dev, phys_addr_t phys_addr,
|
||||||
|
|
||||||
rc = dma_declare_coherent_memory(dev, phys_addr, device_addr, size,
|
rc = dma_declare_coherent_memory(dev, phys_addr, device_addr, size,
|
||||||
flags);
|
flags);
|
||||||
if (rc) {
|
if (!rc)
|
||||||
devres_add(dev, res);
|
devres_add(dev, res);
|
||||||
rc = 0;
|
else
|
||||||
} else {
|
|
||||||
devres_free(res);
|
devres_free(res);
|
||||||
rc = -ENOMEM;
|
|
||||||
}
|
|
||||||
|
|
||||||
return rc;
|
return rc;
|
||||||
}
|
}
|
||||||
|
|
|
@ -451,9 +451,6 @@ static struct port_buffer *alloc_buf(struct virtqueue *vq, size_t buf_size,
|
||||||
* device is created by remoteproc, the DMA memory is
|
* device is created by remoteproc, the DMA memory is
|
||||||
* associated with the grandparent device:
|
* associated with the grandparent device:
|
||||||
* vdev => rproc => platform-dev.
|
* vdev => rproc => platform-dev.
|
||||||
* The code here would have been less quirky if
|
|
||||||
* DMA_MEMORY_INCLUDES_CHILDREN had been supported
|
|
||||||
* in dma-coherent.c
|
|
||||||
*/
|
*/
|
||||||
if (!vq->vdev->dev.parent || !vq->vdev->dev.parent->parent)
|
if (!vq->vdev->dev.parent || !vq->vdev->dev.parent->parent)
|
||||||
goto free_buf;
|
goto free_buf;
|
||||||
|
|
|
@ -1708,11 +1708,10 @@ static int sh_mobile_ceu_probe(struct platform_device *pdev)
|
||||||
err = dma_declare_coherent_memory(&pdev->dev, res->start,
|
err = dma_declare_coherent_memory(&pdev->dev, res->start,
|
||||||
res->start,
|
res->start,
|
||||||
resource_size(res),
|
resource_size(res),
|
||||||
DMA_MEMORY_MAP |
|
|
||||||
DMA_MEMORY_EXCLUSIVE);
|
DMA_MEMORY_EXCLUSIVE);
|
||||||
if (!err) {
|
if (err) {
|
||||||
dev_err(&pdev->dev, "Unable to declare CEU memory.\n");
|
dev_err(&pdev->dev, "Unable to declare CEU memory.\n");
|
||||||
return -ENXIO;
|
return err;
|
||||||
}
|
}
|
||||||
|
|
||||||
pcdev->video_limit = resource_size(res);
|
pcdev->video_limit = resource_size(res);
|
||||||
|
|
|
@ -1180,9 +1180,10 @@ static int au1000_probe(struct platform_device *pdev)
|
||||||
/* Allocate the data buffers
|
/* Allocate the data buffers
|
||||||
* Snooping works fine with eth on all au1xxx
|
* Snooping works fine with eth on all au1xxx
|
||||||
*/
|
*/
|
||||||
aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE *
|
aup->vaddr = (u32)dma_alloc_attrs(NULL, MAX_BUF_SIZE *
|
||||||
(NUM_TX_BUFFS + NUM_RX_BUFFS),
|
(NUM_TX_BUFFS + NUM_RX_BUFFS),
|
||||||
&aup->dma_addr, 0);
|
&aup->dma_addr, 0,
|
||||||
|
DMA_ATTR_NON_CONSISTENT);
|
||||||
if (!aup->vaddr) {
|
if (!aup->vaddr) {
|
||||||
dev_err(&pdev->dev, "failed to allocate data buffers\n");
|
dev_err(&pdev->dev, "failed to allocate data buffers\n");
|
||||||
err = -ENOMEM;
|
err = -ENOMEM;
|
||||||
|
@ -1361,8 +1362,9 @@ static int au1000_probe(struct platform_device *pdev)
|
||||||
err_remap2:
|
err_remap2:
|
||||||
iounmap(aup->mac);
|
iounmap(aup->mac);
|
||||||
err_remap1:
|
err_remap1:
|
||||||
dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS),
|
dma_free_attrs(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS),
|
||||||
(void *)aup->vaddr, aup->dma_addr);
|
(void *)aup->vaddr, aup->dma_addr,
|
||||||
|
DMA_ATTR_NON_CONSISTENT);
|
||||||
err_vaddr:
|
err_vaddr:
|
||||||
free_netdev(dev);
|
free_netdev(dev);
|
||||||
err_alloc:
|
err_alloc:
|
||||||
|
@ -1394,9 +1396,9 @@ static int au1000_remove(struct platform_device *pdev)
|
||||||
if (aup->tx_db_inuse[i])
|
if (aup->tx_db_inuse[i])
|
||||||
au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
|
au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
|
||||||
|
|
||||||
dma_free_noncoherent(NULL, MAX_BUF_SIZE *
|
dma_free_attrs(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS),
|
||||||
(NUM_TX_BUFFS + NUM_RX_BUFFS),
|
(void *)aup->vaddr, aup->dma_addr,
|
||||||
(void *)aup->vaddr, aup->dma_addr);
|
DMA_ATTR_NON_CONSISTENT);
|
||||||
|
|
||||||
iounmap(aup->macdma);
|
iounmap(aup->macdma);
|
||||||
iounmap(aup->mac);
|
iounmap(aup->mac);
|
||||||
|
|
|
@ -96,8 +96,6 @@
|
||||||
|
|
||||||
#define OPT_SWAP_PORT 0x0001 /* Need to wordswp on the MPU port */
|
#define OPT_SWAP_PORT 0x0001 /* Need to wordswp on the MPU port */
|
||||||
|
|
||||||
#define DMA_ALLOC dma_alloc_noncoherent
|
|
||||||
#define DMA_FREE dma_free_noncoherent
|
|
||||||
#define DMA_WBACK(ndev, addr, len) \
|
#define DMA_WBACK(ndev, addr, len) \
|
||||||
do { dma_cache_sync((ndev)->dev.parent, (void *)addr, len, DMA_TO_DEVICE); } while (0)
|
do { dma_cache_sync((ndev)->dev.parent, (void *)addr, len, DMA_TO_DEVICE); } while (0)
|
||||||
|
|
||||||
|
@ -200,8 +198,8 @@ static int __exit lan_remove_chip(struct parisc_device *pdev)
|
||||||
struct i596_private *lp = netdev_priv(dev);
|
struct i596_private *lp = netdev_priv(dev);
|
||||||
|
|
||||||
unregister_netdev (dev);
|
unregister_netdev (dev);
|
||||||
DMA_FREE(&pdev->dev, sizeof(struct i596_private),
|
dma_free_attrs(&pdev->dev, sizeof(struct i596_private), lp->dma,
|
||||||
(void *)lp->dma, lp->dma_addr);
|
lp->dma_addr, DMA_ATTR_NON_CONSISTENT);
|
||||||
free_netdev (dev);
|
free_netdev (dev);
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
|
@ -1063,8 +1063,9 @@ static int i82596_probe(struct net_device *dev)
|
||||||
if (!dev->base_addr || !dev->irq)
|
if (!dev->base_addr || !dev->irq)
|
||||||
return -ENODEV;
|
return -ENODEV;
|
||||||
|
|
||||||
dma = (struct i596_dma *) DMA_ALLOC(dev->dev.parent,
|
dma = dma_alloc_attrs(dev->dev.parent, sizeof(struct i596_dma),
|
||||||
sizeof(struct i596_dma), &lp->dma_addr, GFP_KERNEL);
|
&lp->dma_addr, GFP_KERNEL,
|
||||||
|
DMA_ATTR_NON_CONSISTENT);
|
||||||
if (!dma) {
|
if (!dma) {
|
||||||
printk(KERN_ERR "%s: Couldn't get shared memory\n", __FILE__);
|
printk(KERN_ERR "%s: Couldn't get shared memory\n", __FILE__);
|
||||||
return -ENOMEM;
|
return -ENOMEM;
|
||||||
|
@ -1085,8 +1086,8 @@ static int i82596_probe(struct net_device *dev)
|
||||||
|
|
||||||
i = register_netdev(dev);
|
i = register_netdev(dev);
|
||||||
if (i) {
|
if (i) {
|
||||||
DMA_FREE(dev->dev.parent, sizeof(struct i596_dma),
|
dma_free_attrs(dev->dev.parent, sizeof(struct i596_dma),
|
||||||
(void *)dma, lp->dma_addr);
|
dma, lp->dma_addr, DMA_ATTR_NON_CONSISTENT);
|
||||||
return i;
|
return i;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -23,8 +23,6 @@
|
||||||
|
|
||||||
static const char sni_82596_string[] = "snirm_82596";
|
static const char sni_82596_string[] = "snirm_82596";
|
||||||
|
|
||||||
#define DMA_ALLOC dma_alloc_coherent
|
|
||||||
#define DMA_FREE dma_free_coherent
|
|
||||||
#define DMA_WBACK(priv, addr, len) do { } while (0)
|
#define DMA_WBACK(priv, addr, len) do { } while (0)
|
||||||
#define DMA_INV(priv, addr, len) do { } while (0)
|
#define DMA_INV(priv, addr, len) do { } while (0)
|
||||||
#define DMA_WBACK_INV(priv, addr, len) do { } while (0)
|
#define DMA_WBACK_INV(priv, addr, len) do { } while (0)
|
||||||
|
@ -152,8 +150,8 @@ static int sni_82596_driver_remove(struct platform_device *pdev)
|
||||||
struct i596_private *lp = netdev_priv(dev);
|
struct i596_private *lp = netdev_priv(dev);
|
||||||
|
|
||||||
unregister_netdev(dev);
|
unregister_netdev(dev);
|
||||||
DMA_FREE(dev->dev.parent, sizeof(struct i596_private),
|
dma_free_attrs(dev->dev.parent, sizeof(struct i596_private), lp->dma,
|
||||||
lp->dma, lp->dma_addr);
|
lp->dma_addr, DMA_ATTR_NON_CONSISTENT);
|
||||||
iounmap(lp->ca);
|
iounmap(lp->ca);
|
||||||
iounmap(lp->mpu_port);
|
iounmap(lp->mpu_port);
|
||||||
free_netdev (dev);
|
free_netdev (dev);
|
||||||
|
|
|
@ -737,8 +737,8 @@ static int sgiseeq_probe(struct platform_device *pdev)
|
||||||
sp = netdev_priv(dev);
|
sp = netdev_priv(dev);
|
||||||
|
|
||||||
/* Make private data page aligned */
|
/* Make private data page aligned */
|
||||||
sr = dma_alloc_noncoherent(&pdev->dev, sizeof(*sp->srings),
|
sr = dma_alloc_attrs(&pdev->dev, sizeof(*sp->srings), &sp->srings_dma,
|
||||||
&sp->srings_dma, GFP_KERNEL);
|
GFP_KERNEL, DMA_ATTR_NON_CONSISTENT);
|
||||||
if (!sr) {
|
if (!sr) {
|
||||||
printk(KERN_ERR "Sgiseeq: Page alloc failed, aborting.\n");
|
printk(KERN_ERR "Sgiseeq: Page alloc failed, aborting.\n");
|
||||||
err = -ENOMEM;
|
err = -ENOMEM;
|
||||||
|
@ -813,8 +813,8 @@ static int sgiseeq_remove(struct platform_device *pdev)
|
||||||
struct sgiseeq_private *sp = netdev_priv(dev);
|
struct sgiseeq_private *sp = netdev_priv(dev);
|
||||||
|
|
||||||
unregister_netdev(dev);
|
unregister_netdev(dev);
|
||||||
dma_free_noncoherent(&pdev->dev, sizeof(*sp->srings), sp->srings,
|
dma_free_attrs(&pdev->dev, sizeof(*sp->srings), sp->srings,
|
||||||
sp->srings_dma);
|
sp->srings_dma, DMA_ATTR_NON_CONSISTENT);
|
||||||
free_netdev(dev);
|
free_netdev(dev);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
|
|
|
@ -9,6 +9,9 @@
|
||||||
#include <linux/module.h>
|
#include <linux/module.h>
|
||||||
#include <linux/mod_devicetable.h>
|
#include <linux/mod_devicetable.h>
|
||||||
#include <linux/slab.h>
|
#include <linux/slab.h>
|
||||||
|
#include <linux/pci.h>
|
||||||
|
#include <linux/platform_device.h>
|
||||||
|
#include <linux/amba/bus.h>
|
||||||
|
|
||||||
#include <asm/errno.h>
|
#include <asm/errno.h>
|
||||||
#include "of_private.h"
|
#include "of_private.h"
|
||||||
|
@ -84,31 +87,28 @@ int of_device_add(struct platform_device *ofdev)
|
||||||
*/
|
*/
|
||||||
int of_dma_configure(struct device *dev, struct device_node *np)
|
int of_dma_configure(struct device *dev, struct device_node *np)
|
||||||
{
|
{
|
||||||
u64 dma_addr, paddr, size;
|
u64 dma_addr, paddr, size = 0;
|
||||||
int ret;
|
int ret;
|
||||||
bool coherent;
|
bool coherent;
|
||||||
unsigned long offset;
|
unsigned long offset;
|
||||||
const struct iommu_ops *iommu;
|
const struct iommu_ops *iommu;
|
||||||
u64 mask;
|
u64 mask;
|
||||||
|
|
||||||
/*
|
|
||||||
* Set default coherent_dma_mask to 32 bit. Drivers are expected to
|
|
||||||
* setup the correct supported mask.
|
|
||||||
*/
|
|
||||||
if (!dev->coherent_dma_mask)
|
|
||||||
dev->coherent_dma_mask = DMA_BIT_MASK(32);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Set it to coherent_dma_mask by default if the architecture
|
|
||||||
* code has not set it.
|
|
||||||
*/
|
|
||||||
if (!dev->dma_mask)
|
|
||||||
dev->dma_mask = &dev->coherent_dma_mask;
|
|
||||||
|
|
||||||
ret = of_dma_get_range(np, &dma_addr, &paddr, &size);
|
ret = of_dma_get_range(np, &dma_addr, &paddr, &size);
|
||||||
if (ret < 0) {
|
if (ret < 0) {
|
||||||
|
/*
|
||||||
|
* For legacy reasons, we have to assume some devices need
|
||||||
|
* DMA configuration regardless of whether "dma-ranges" is
|
||||||
|
* correctly specified or not.
|
||||||
|
*/
|
||||||
|
if (!dev_is_pci(dev) &&
|
||||||
|
#ifdef CONFIG_ARM_AMBA
|
||||||
|
dev->bus != &amba_bustype &&
|
||||||
|
#endif
|
||||||
|
dev->bus != &platform_bus_type)
|
||||||
|
return ret == -ENODEV ? 0 : ret;
|
||||||
|
|
||||||
dma_addr = offset = 0;
|
dma_addr = offset = 0;
|
||||||
size = max(dev->coherent_dma_mask, dev->coherent_dma_mask + 1);
|
|
||||||
} else {
|
} else {
|
||||||
offset = PFN_DOWN(paddr - dma_addr);
|
offset = PFN_DOWN(paddr - dma_addr);
|
||||||
|
|
||||||
|
@ -129,6 +129,22 @@ int of_dma_configure(struct device *dev, struct device_node *np)
|
||||||
dev_dbg(dev, "dma_pfn_offset(%#08lx)\n", offset);
|
dev_dbg(dev, "dma_pfn_offset(%#08lx)\n", offset);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Set default coherent_dma_mask to 32 bit. Drivers are expected to
|
||||||
|
* setup the correct supported mask.
|
||||||
|
*/
|
||||||
|
if (!dev->coherent_dma_mask)
|
||||||
|
dev->coherent_dma_mask = DMA_BIT_MASK(32);
|
||||||
|
/*
|
||||||
|
* Set it to coherent_dma_mask by default if the architecture
|
||||||
|
* code has not set it.
|
||||||
|
*/
|
||||||
|
if (!dev->dma_mask)
|
||||||
|
dev->dma_mask = &dev->coherent_dma_mask;
|
||||||
|
|
||||||
|
if (!size)
|
||||||
|
size = max(dev->coherent_dma_mask, dev->coherent_dma_mask + 1);
|
||||||
|
|
||||||
dev->dma_pfn_offset = offset;
|
dev->dma_pfn_offset = offset;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -217,8 +217,7 @@ NCR_Q720_probe(struct device *dev)
|
||||||
}
|
}
|
||||||
|
|
||||||
if (dma_declare_coherent_memory(dev, base_addr, base_addr,
|
if (dma_declare_coherent_memory(dev, base_addr, base_addr,
|
||||||
mem_size, DMA_MEMORY_MAP)
|
mem_size, 0)) {
|
||||||
!= DMA_MEMORY_MAP) {
|
|
||||||
printk(KERN_ERR "NCR_Q720: DMA declare memory failed\n");
|
printk(KERN_ERR "NCR_Q720: DMA declare memory failed\n");
|
||||||
goto out_release_region;
|
goto out_release_region;
|
||||||
}
|
}
|
||||||
|
|
|
@ -123,13 +123,12 @@ static int ohci_hcd_sm501_drv_probe(struct platform_device *pdev)
|
||||||
* regular memory. The HCD_LOCAL_MEM flag does just that.
|
* regular memory. The HCD_LOCAL_MEM flag does just that.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
if (!dma_declare_coherent_memory(dev, mem->start,
|
retval = dma_declare_coherent_memory(dev, mem->start,
|
||||||
mem->start - mem->parent->start,
|
mem->start - mem->parent->start,
|
||||||
resource_size(mem),
|
resource_size(mem),
|
||||||
DMA_MEMORY_MAP |
|
DMA_MEMORY_EXCLUSIVE);
|
||||||
DMA_MEMORY_EXCLUSIVE)) {
|
if (retval) {
|
||||||
dev_err(dev, "cannot declare coherent memory\n");
|
dev_err(dev, "cannot declare coherent memory\n");
|
||||||
retval = -ENXIO;
|
|
||||||
goto err1;
|
goto err1;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -227,13 +227,10 @@ static int ohci_hcd_tmio_drv_probe(struct platform_device *dev)
|
||||||
goto err_ioremap_regs;
|
goto err_ioremap_regs;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (!dma_declare_coherent_memory(&dev->dev, sram->start,
|
ret = dma_declare_coherent_memory(&dev->dev, sram->start, sram->start,
|
||||||
sram->start,
|
resource_size(sram), DMA_MEMORY_EXCLUSIVE);
|
||||||
resource_size(sram),
|
if (ret)
|
||||||
DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE)) {
|
|
||||||
ret = -EBUSY;
|
|
||||||
goto err_dma_declare;
|
goto err_dma_declare;
|
||||||
}
|
|
||||||
|
|
||||||
if (cell->enable) {
|
if (cell->enable) {
|
||||||
ret = cell->enable(dev);
|
ret = cell->enable(dev);
|
||||||
|
|
|
@ -550,26 +550,13 @@ static inline void dma_free_coherent(struct device *dev, size_t size,
|
||||||
return dma_free_attrs(dev, size, cpu_addr, dma_handle, 0);
|
return dma_free_attrs(dev, size, cpu_addr, dma_handle, 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void *dma_alloc_noncoherent(struct device *dev, size_t size,
|
|
||||||
dma_addr_t *dma_handle, gfp_t gfp)
|
|
||||||
{
|
|
||||||
return dma_alloc_attrs(dev, size, dma_handle, gfp,
|
|
||||||
DMA_ATTR_NON_CONSISTENT);
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline void dma_free_noncoherent(struct device *dev, size_t size,
|
|
||||||
void *cpu_addr, dma_addr_t dma_handle)
|
|
||||||
{
|
|
||||||
dma_free_attrs(dev, size, cpu_addr, dma_handle,
|
|
||||||
DMA_ATTR_NON_CONSISTENT);
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
|
static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
|
||||||
{
|
{
|
||||||
debug_dma_mapping_error(dev, dma_addr);
|
const struct dma_map_ops *ops = get_dma_ops(dev);
|
||||||
|
|
||||||
if (get_dma_ops(dev)->mapping_error)
|
debug_dma_mapping_error(dev, dma_addr);
|
||||||
return get_dma_ops(dev)->mapping_error(dev, dma_addr);
|
if (ops->mapping_error)
|
||||||
|
return ops->mapping_error(dev, dma_addr);
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -720,10 +707,7 @@ static inline int dma_get_cache_alignment(void)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* flags for the coherent memory api */
|
/* flags for the coherent memory api */
|
||||||
#define DMA_MEMORY_MAP 0x01
|
#define DMA_MEMORY_EXCLUSIVE 0x01
|
||||||
#define DMA_MEMORY_IO 0x02
|
|
||||||
#define DMA_MEMORY_INCLUDES_CHILDREN 0x04
|
|
||||||
#define DMA_MEMORY_EXCLUSIVE 0x08
|
|
||||||
|
|
||||||
#ifdef CONFIG_HAVE_GENERIC_DMA_COHERENT
|
#ifdef CONFIG_HAVE_GENERIC_DMA_COHERENT
|
||||||
int dma_declare_coherent_memory(struct device *dev, phys_addr_t phys_addr,
|
int dma_declare_coherent_memory(struct device *dev, phys_addr_t phys_addr,
|
||||||
|
@ -736,7 +720,7 @@ static inline int
|
||||||
dma_declare_coherent_memory(struct device *dev, phys_addr_t phys_addr,
|
dma_declare_coherent_memory(struct device *dev, phys_addr_t phys_addr,
|
||||||
dma_addr_t device_addr, size_t size, int flags)
|
dma_addr_t device_addr, size_t size, int flags)
|
||||||
{
|
{
|
||||||
return 0;
|
return -ENOSYS;
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void
|
static inline void
|
||||||
|
|
Loading…
Reference in New Issue