mirror of https://gitee.com/openkylin/linux.git
drm/tegra: hdmi: Implement runtime PM
Use runtime PM to clock-(un)gate and (de)assert reset to the HDMI controller. This ties in nicely with atomic DPMS in that a runtime PM reference is taken before a pipe is enabled and dropped after it has been shut down. Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Thierry Reding
parent
ef8187d752
commit
5234549b93
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@ -11,6 +11,7 @@
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#include <linux/debugfs.h>
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#include <linux/gpio.h>
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#include <linux/hdmi.h>
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#include <linux/pm_runtime.h>
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#include <linux/regulator/consumer.h>
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#include <linux/reset.h>
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@ -641,6 +642,29 @@ static void tegra_hdmi_enable_audio(struct tegra_hdmi *hdmi)
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tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
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}
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static void tegra_hdmi_write_eld(struct tegra_hdmi *hdmi)
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{
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size_t length = drm_eld_size(hdmi->output.connector.eld), i;
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u32 value;
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for (i = 0; i < length; i++)
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tegra_hdmi_writel(hdmi, i << 8 | hdmi->output.connector.eld[i],
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HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
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/*
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* The HDA codec will always report an ELD buffer size of 96 bytes and
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* the HDA codec driver will check that each byte read from the buffer
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* is valid. Therefore every byte must be written, even if no 96 bytes
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* were parsed from EDID.
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*/
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for (i = length; i < HDMI_ELD_BUFFER_SIZE; i++)
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tegra_hdmi_writel(hdmi, i << 8 | 0,
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HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
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value = SOR_AUDIO_HDA_PRESENSE_VALID | SOR_AUDIO_HDA_PRESENSE_PRESENT;
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tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
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}
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static inline u32 tegra_hdmi_subpack(const u8 *ptr, size_t size)
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{
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u32 value = 0;
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@ -945,29 +969,11 @@ static void tegra_hdmi_encoder_disable(struct drm_encoder *encoder)
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tegra_hdmi_disable_avi_infoframe(hdmi);
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tegra_hdmi_disable_audio(hdmi);
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}
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}
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static void tegra_hdmi_write_eld(struct tegra_hdmi *hdmi)
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{
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size_t length = drm_eld_size(hdmi->output.connector.eld), i;
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u32 value;
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tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_ENABLE);
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tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_MASK);
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for (i = 0; i < length; i++)
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tegra_hdmi_writel(hdmi, i << 8 | hdmi->output.connector.eld[i],
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HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
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/*
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* The HDA codec will always report an ELD buffer size of 96 bytes and
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* the HDA codec driver will check that each byte read from the buffer
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* is valid. Therefore every byte must be written, even if no 96 bytes
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* were parsed from EDID.
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*/
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for (i = length; i < HDMI_ELD_BUFFER_SIZE; i++)
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tegra_hdmi_writel(hdmi, i << 8 | 0,
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HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
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value = SOR_AUDIO_HDA_PRESENSE_VALID | SOR_AUDIO_HDA_PRESENSE_PRESENT;
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tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
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pm_runtime_put(hdmi->dev);
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}
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static void tegra_hdmi_encoder_enable(struct drm_encoder *encoder)
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@ -982,6 +988,16 @@ static void tegra_hdmi_encoder_enable(struct drm_encoder *encoder)
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u32 value;
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int err;
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pm_runtime_get_sync(hdmi->dev);
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/*
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* Enable and unmask the HDA codec SCRATCH0 register interrupt. This
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* is used for interoperability between the HDA codec driver and the
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* HDMI driver.
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*/
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tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_ENABLE);
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tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_MASK);
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hdmi->pixel_clock = mode->clock * 1000;
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h_sync_width = mode->hsync_end - mode->hsync_start;
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h_back_porch = mode->htotal - mode->hsync_end;
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@ -1507,22 +1523,6 @@ static int tegra_hdmi_init(struct host1x_client *client)
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return err;
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}
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err = clk_prepare_enable(hdmi->clk);
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if (err < 0) {
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dev_err(hdmi->dev, "failed to enable clock: %d\n", err);
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return err;
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}
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reset_control_deassert(hdmi->rst);
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/*
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* Enable and unmask the HDA codec SCRATCH0 register interrupt. This
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* is used for interoperability between the HDA codec driver and the
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* HDMI driver.
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*/
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tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_ENABLE);
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tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_MASK);
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return 0;
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}
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@ -1530,14 +1530,8 @@ static int tegra_hdmi_exit(struct host1x_client *client)
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{
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struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
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tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_MASK);
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tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_ENABLE);
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tegra_output_exit(&hdmi->output);
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reset_control_assert(hdmi->rst);
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clk_disable_unprepare(hdmi->clk);
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regulator_disable(hdmi->vdd);
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regulator_disable(hdmi->pll);
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regulator_disable(hdmi->hdmi);
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@ -1752,6 +1746,9 @@ static int tegra_hdmi_probe(struct platform_device *pdev)
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return err;
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}
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platform_set_drvdata(pdev, hdmi);
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pm_runtime_enable(&pdev->dev);
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INIT_LIST_HEAD(&hdmi->client.list);
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hdmi->client.ops = &hdmi_client_ops;
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hdmi->client.dev = &pdev->dev;
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@ -1763,8 +1760,6 @@ static int tegra_hdmi_probe(struct platform_device *pdev)
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return err;
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}
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platform_set_drvdata(pdev, hdmi);
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return 0;
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}
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@ -1773,6 +1768,8 @@ static int tegra_hdmi_remove(struct platform_device *pdev)
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struct tegra_hdmi *hdmi = platform_get_drvdata(pdev);
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int err;
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pm_runtime_disable(&pdev->dev);
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err = host1x_client_unregister(&hdmi->client);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
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@ -1782,17 +1779,61 @@ static int tegra_hdmi_remove(struct platform_device *pdev)
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tegra_output_remove(&hdmi->output);
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clk_disable_unprepare(hdmi->clk_parent);
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return 0;
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}
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#ifdef CONFIG_PM
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static int tegra_hdmi_suspend(struct device *dev)
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{
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struct tegra_hdmi *hdmi = dev_get_drvdata(dev);
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int err;
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err = reset_control_assert(hdmi->rst);
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if (err < 0) {
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dev_err(dev, "failed to assert reset: %d\n", err);
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return err;
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}
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usleep_range(1000, 2000);
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clk_disable_unprepare(hdmi->clk);
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return 0;
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}
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static int tegra_hdmi_resume(struct device *dev)
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{
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struct tegra_hdmi *hdmi = dev_get_drvdata(dev);
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int err;
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err = clk_prepare_enable(hdmi->clk);
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if (err < 0) {
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dev_err(dev, "failed to enable clock: %d\n", err);
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return err;
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}
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usleep_range(1000, 2000);
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err = reset_control_deassert(hdmi->rst);
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if (err < 0) {
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dev_err(dev, "failed to deassert reset: %d\n", err);
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clk_disable_unprepare(hdmi->clk);
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return err;
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}
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return 0;
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}
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#endif
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static const struct dev_pm_ops tegra_hdmi_pm_ops = {
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SET_RUNTIME_PM_OPS(tegra_hdmi_suspend, tegra_hdmi_resume, NULL)
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};
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struct platform_driver tegra_hdmi_driver = {
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.driver = {
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.name = "tegra-hdmi",
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.owner = THIS_MODULE,
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.of_match_table = tegra_hdmi_of_match,
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.pm = &tegra_hdmi_pm_ops,
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},
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.probe = tegra_hdmi_probe,
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.remove = tegra_hdmi_remove,
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