mirror of https://gitee.com/openkylin/linux.git
Renesas fixes for v5.7
- Fix IOMMU support on R-Car V3H, - Minor fixes that are fast-tracked to avoid introducing regressions during conversion of DT bindings to json-schema. -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCXqqEEQAKCRCKwlD9ZEnx cK6VAQDEYT5s4bzgLANPkTuvz3n5NgmS1nSC9tGrUX9co4OEUgD+OkwEnFJgLF1+ LbwisW1fNfCz1looPeyyZTl9Q8o5Yg0= =cIRT -----END PGP SIGNATURE----- Merge tag 'renesas-fixes-for-v5.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/fixes Renesas fixes for v5.7 - Fix IOMMU support on R-Car V3H, - Minor fixes that are fast-tracked to avoid introducing regressions during conversion of DT bindings to json-schema. * tag 'renesas-fixes-for-v5.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: ARM: dts: r7s9210: Remove bogus clock-names from OSTM nodes arm64: dts: renesas: r8a77980: Fix IPMMU VIP[01] nodes ARM: dts: r8a73a4: Add missing CMT1 interrupts Link: https://lore.kernel.org/r/20200430084834.1384-1-geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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commit
5258bba832
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@ -304,7 +304,6 @@ ostm0: timer@e803b000 {
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reg = <0xe803b000 0x30>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>;
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clocks = <&cpg CPG_MOD 36>;
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clock-names = "ostm0";
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power-domains = <&cpg>;
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status = "disabled";
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};
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@ -314,7 +313,6 @@ ostm1: timer@e803c000 {
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reg = <0xe803c000 0x30>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
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clocks = <&cpg CPG_MOD 35>;
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clock-names = "ostm1";
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power-domains = <&cpg>;
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status = "disabled";
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};
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@ -324,7 +322,6 @@ ostm2: timer@e803d000 {
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reg = <0xe803d000 0x30>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>;
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clocks = <&cpg CPG_MOD 34>;
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clock-names = "ostm2";
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power-domains = <&cpg>;
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status = "disabled";
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};
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@ -131,7 +131,14 @@ i2c5: i2c@e60b0000 {
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cmt1: timer@e6130000 {
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compatible = "renesas,r8a73a4-cmt1", "renesas,rcar-gen2-cmt1";
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reg = <0 0xe6130000 0 0x1004>;
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interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
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clock-names = "fck";
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power-domains = <&pd_c5>;
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@ -1318,6 +1318,7 @@ ipmmu_vi0: mmu@febd0000 {
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ipmmu_vip0: mmu@e7b00000 {
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compatible = "renesas,ipmmu-r8a77980";
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reg = <0 0xe7b00000 0 0x1000>;
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renesas,ipmmu-main = <&ipmmu_mm 4>;
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power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
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#iommu-cells = <1>;
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};
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@ -1325,6 +1326,7 @@ ipmmu_vip0: mmu@e7b00000 {
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ipmmu_vip1: mmu@e7960000 {
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compatible = "renesas,ipmmu-r8a77980";
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reg = <0 0xe7960000 0 0x1000>;
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renesas,ipmmu-main = <&ipmmu_mm 11>;
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power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
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#iommu-cells = <1>;
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};
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