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Renesas fixes for v5.7 

- Fix IOMMU support on R-Car V3H,
   - Minor fixes that are fast-tracked to avoid introducing regressions
     during conversion of DT bindings to json-schema.
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Merge tag 'renesas-fixes-for-v5.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/fixes

Renesas fixes for v5.7

  - Fix IOMMU support on R-Car V3H,
  - Minor fixes that are fast-tracked to avoid introducing regressions
    during conversion of DT bindings to json-schema.

* tag 'renesas-fixes-for-v5.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  ARM: dts: r7s9210: Remove bogus clock-names from OSTM nodes
  arm64: dts: renesas: r8a77980: Fix IPMMU VIP[01] nodes
  ARM: dts: r8a73a4: Add missing CMT1 interrupts

Link: https://lore.kernel.org/r/20200430084834.1384-1-geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2020-05-14 00:01:06 +02:00
parent 896e18f4dc b704fc1da9
commit 5258bba832
3 changed files with 10 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/boot/dts/r7s9210.dtsi
View File

@ -304,7 +304,6 @@ ostm0: timer@e803b000 {
reg = <0xe803b000 0x30>; reg = <0xe803b000 0x30>;
interrupts = <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>; interrupts = <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>;
clocks = <&cpg CPG_MOD 36>; clocks = <&cpg CPG_MOD 36>;
clock-names = "ostm0";
power-domains = <&cpg>; power-domains = <&cpg>;
status = "disabled"; status = "disabled";
}; };
@ -314,7 +313,6 @@ ostm1: timer@e803c000 {
reg = <0xe803c000 0x30>; reg = <0xe803c000 0x30>;
interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
clocks = <&cpg CPG_MOD 35>; clocks = <&cpg CPG_MOD 35>;
clock-names = "ostm1";
power-domains = <&cpg>; power-domains = <&cpg>;
status = "disabled"; status = "disabled";
}; };
@ -324,7 +322,6 @@ ostm2: timer@e803d000 {
reg = <0xe803d000 0x30>; reg = <0xe803d000 0x30>;
interrupts = <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>; interrupts = <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>;
clocks = <&cpg CPG_MOD 34>; clocks = <&cpg CPG_MOD 34>;
clock-names = "ostm2";
power-domains = <&cpg>; power-domains = <&cpg>;
status = "disabled"; status = "disabled";
}; };

9
arch/arm/boot/dts/r8a73a4.dtsi
View File

@ -131,7 +131,14 @@ i2c5: i2c@e60b0000 {
cmt1: timer@e6130000 { cmt1: timer@e6130000 {
compatible = "renesas,r8a73a4-cmt1", "renesas,rcar-gen2-cmt1"; compatible = "renesas,r8a73a4-cmt1", "renesas,rcar-gen2-cmt1";
reg = <0 0xe6130000 0 0x1004>; reg = <0 0xe6130000 0 0x1004>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A73A4_CLK_CMT1>; clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
clock-names = "fck"; clock-names = "fck";
power-domains = <&pd_c5>; power-domains = <&pd_c5>;

2
arch/arm64/boot/dts/renesas/r8a77980.dtsi
View File

@ -1318,6 +1318,7 @@ ipmmu_vi0: mmu@febd0000 {
ipmmu_vip0: mmu@e7b00000 { ipmmu_vip0: mmu@e7b00000 {
compatible = "renesas,ipmmu-r8a77980"; compatible = "renesas,ipmmu-r8a77980";
reg = <0 0xe7b00000 0 0x1000>; reg = <0 0xe7b00000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 4>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
#iommu-cells = <1>; #iommu-cells = <1>;
}; };
@ -1325,6 +1326,7 @@ ipmmu_vip0: mmu@e7b00000 {
ipmmu_vip1: mmu@e7960000 { ipmmu_vip1: mmu@e7960000 {
compatible = "renesas,ipmmu-r8a77980"; compatible = "renesas,ipmmu-r8a77980";
reg = <0 0xe7960000 0 0x1000>; reg = <0 0xe7960000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 11>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
#iommu-cells = <1>; #iommu-cells = <1>;
}; };