Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin: (88 commits) Blackfin: Convert BUG() to use unreachable() Blackfin: define __NR_recvmmsg Blackfin: drop duplicate sched_clock Blackfin: NOMPU: skip DMA ICPLB hole when it is redundant Blackfin: MPU: add missing __init markings Blackfin: add support for TIF_NOTIFY_RESUME Blackfin: kgdb_test: clean up code a bit Blackfin: convert kgdbtest to proc_fops Blackfin: convert cyc2ns() to clocksource_cyc2ns() Blackfin: ip0x: pull in asm/portmux.h for P_xxx defines Blackfin: drop unused ax88180 resources Blackfin: bf537-stamp: add ADF702x network driver resources Blackfin: bf537-stamp: add CAN resources Blackfin: bf537-stamp: add AD5258 i2c address Blackfin: bf537-stamp: add adau1761 i2c address Blackfin: bf537-stamp: add adau1371 i2c address Blackfin: bf537-stamp: add ADP8870 resources Blackfin: bf537-stamp: kill AD714x board-specific Kconfigs Blackfin: bf537-stamp: update ADP5520 resources Blackfin: bf537-stamp: add ADXL346 orientation sensing support ...
2009-12-16 10:52:35 -08:00 · 2009-12-16 10:52:35 -08:00 · 525995d77c
parent e4bdda1bc3 64a2b16802
commit 525995d77c
137 changed files with 6846 additions and 13624 deletions
--- a/Documentation/blackfin/00-INDEX
+++ b/Documentation/blackfin/00-INDEX
@ -1,9 +1,6 @@
 00-INDEX
 	- This file
 cache-lock.txt
 	- HOWTO for blackfin cache locking.
 cachefeatures.txt
 	- Supported cache features.
--- a/Documentation/blackfin/Makefile
+++ b/Documentation/blackfin/Makefile
@ -0,0 +1,6 @@
 obj-m := gptimers-example.o
 all: modules
 modules clean:
 	$(MAKE) -C ../.. SUBDIRS=$(PWD) $@
--- a/Documentation/blackfin/cache-lock.txt
+++ b/Documentation/blackfin/cache-lock.txt
@ -1,48 +0,0 @@
 /*
 * File:         Documentation/blackfin/cache-lock.txt
 * Based on:
 * Author:
 *
 * Created:
 * Description:  This file contains the simple DMA Implementation for Blackfin
 *
 * Rev:          $Id: cache-lock.txt 2384 2006-11-01 04:12:43Z magicyang $
 *
 * Modified:
 *               Copyright 2004-2006 Analog Devices Inc.
 *
 * Bugs:         Enter bugs at http://blackfin.uclinux.org/
 *
 */
 How to lock your code in cache in uClinux/blackfin
 --------------------------------------------------
 There are only a few steps required to lock your code into the cache.
 Currently you can lock the code by Way.
 Below are the interface provided for locking the cache.
 1. cache_grab_lock(int Ways);
 This function grab the lock for locking your code into the cache specified
 by Ways.
 2. cache_lock(int Ways);
 This function should be called after your critical code has been executed.
 Once the critical code exits, the code is now loaded into the cache. This
 function locks the code into the cache.
 So, the example sequence will be:
 	cache_grab_lock(WAY0_L);	/* Grab the lock */
 	critical_code();		/* Execute the code of interest */
 	cache_lock(WAY0_L);		/* Lock the cache */
 Where WAY0_L signifies WAY0 locking.
--- a/Documentation/blackfin/cachefeatures.txt
+++ b/Documentation/blackfin/cachefeatures.txt
@ -41,16 +41,6 @@
 		icplb_flush();
 		dcplb_flush();
 	- Locking the cache.
 		cache_grab_lock();
 		cache_lock();
 	Please refer linux-2.6.x/Documentation/blackfin/cache-lock.txt for how to
 	lock the cache.
 	Locking the cache is optional feature.
 	- Miscellaneous cache functions.
 		flush_cache_all();
--- a/Documentation/blackfin/gptimers-example.c
+++ b/Documentation/blackfin/gptimers-example.c
@ -0,0 +1,83 @@
 /*
 * Simple gptimers example
 *	http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:gptimers
 *
 * Copyright 2007-2009 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
 */
 #include <linux/interrupt.h>
 #include <linux/module.h>
 #include <asm/gptimers.h>
 #include <asm/portmux.h>
 /* ... random driver includes ... */
 #define DRIVER_NAME "gptimer_example"
 struct gptimer_data {
 	uint32_t period, width;
 };
 static struct gptimer_data data;
 /* ... random driver state ... */
 static irqreturn_t gptimer_example_irq(int irq, void *dev_id)
 {
 	struct gptimer_data *data = dev_id;
 	/* make sure it was our timer which caused the interrupt */
 	if (!get_gptimer_intr(TIMER5_id))
 		return IRQ_NONE;
 	/* read the width/period values that were captured for the waveform */
 	data->width = get_gptimer_pwidth(TIMER5_id);
 	data->period = get_gptimer_period(TIMER5_id);
 	/* acknowledge the interrupt */
 	clear_gptimer_intr(TIMER5_id);
 	/* tell the upper layers we took care of things */
 	return IRQ_HANDLED;
 }
 /* ... random driver code ... */
 static int __init gptimer_example_init(void)
 {
 	int ret;
 	/* grab the peripheral pins */
 	ret = peripheral_request(P_TMR5, DRIVER_NAME);
 	if (ret) {
 		printk(KERN_NOTICE DRIVER_NAME ": peripheral request failed\n");
 		return ret;
 	}
 	/* grab the IRQ for the timer */
 	ret = request_irq(IRQ_TIMER5, gptimer_example_irq, IRQF_SHARED, DRIVER_NAME, &data);
 	if (ret) {
 		printk(KERN_NOTICE DRIVER_NAME ": IRQ request failed\n");
 		peripheral_free(P_TMR5);
 		return ret;
 	}
 	/* setup the timer and enable it */
 	set_gptimer_config(TIMER5_id, WDTH_CAP | PULSE_HI | PERIOD_CNT | IRQ_ENA);
 	enable_gptimers(TIMER5bit);
 	return 0;
 }
 module_init(gptimer_example_init);
 static void __exit gptimer_example_exit(void)
 {
 	disable_gptimers(TIMER5bit);
 	free_irq(IRQ_TIMER5, &data);
 	peripheral_free(P_TMR5);
 }
 module_exit(gptimer_example_exit);
 MODULE_LICENSE("BSD");
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@ -32,6 +32,9 @@ config BLACKFIN
 	select HAVE_OPROFILE
 	select ARCH_WANT_OPTIONAL_GPIOLIB
 config GENERIC_CSUM
 	def_bool y
 config GENERIC_BUG
 	def_bool y
 	depends on BUG
@ -177,7 +180,7 @@ config BF539
 	help
 	  BF539 Processor Support.
-config BF542
+config BF542_std
 	bool "BF542"
 	help
 	  BF542 Processor Support.
@ -187,7 +190,7 @@ config BF542M
 	help
 	  BF542 Processor Support.
-config BF544
+config BF544_std
 	bool "BF544"
 	help
 	  BF544 Processor Support.
@ -197,7 +200,7 @@ config BF544M
 	help
 	  BF544 Processor Support.
-config BF547
+config BF547_std
 	bool "BF547"
 	help
 	  BF547 Processor Support.
@ -207,7 +210,7 @@ config BF547M
 	help
 	  BF547 Processor Support.
-config BF548
+config BF548_std
 	bool "BF548"
 	help
 	  BF548 Processor Support.
@ -217,7 +220,7 @@ config BF548M
 	help
 	  BF548 Processor Support.
-config BF549
+config BF549_std
 	bool "BF549"
 	help
 	  BF549 Processor Support.
@ -311,31 +314,11 @@ config BF_REV_NONE
 endchoice
 config BF51x
 	bool
 	depends on (BF512 || BF514 || BF516 || BF518)
 	default y
 config BF52x
 	bool
 	depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
 	default y
 config BF53x
 	bool
 	depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
 	default y
 config BF54xM
 	bool
 	depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
 	default y
 config BF54x
 	bool
 	depends on (BF542 || BF544 || BF547 || BF548 || BF549 || BF54xM)
 	default y
 config MEM_GENERIC_BOARD
 	bool
 	depends on GENERIC_BOARD
@ -917,6 +900,12 @@ config DMA_UNCACHED_2M
 	bool "Enable 2M DMA region"
 config DMA_UNCACHED_1M
 	bool "Enable 1M DMA region"
 config DMA_UNCACHED_512K
 	bool "Enable 512K DMA region"
 config DMA_UNCACHED_256K
 	bool "Enable 256K DMA region"
 config DMA_UNCACHED_128K
 	bool "Enable 128K DMA region"
 config DMA_UNCACHED_NONE
 	bool "Disable DMA region"
 endchoice
@ -1278,6 +1267,8 @@ source "net/Kconfig"
 source "drivers/Kconfig"
 source "drivers/firmware/Kconfig"
 source "fs/Kconfig"
 source "arch/blackfin/Kconfig.debug"
--- a/arch/blackfin/Makefile
+++ b/arch/blackfin/Makefile
@ -16,6 +16,7 @@ GZFLAGS          := -9
 KBUILD_CFLAGS           += $(call cc-option,-mno-fdpic)
 KBUILD_AFLAGS           += $(call cc-option,-mno-fdpic)
 CFLAGS_MODULE    += -mlong-calls
 LDFLAGS_MODULE   += -m elf32bfin
 KALLSYMS         += --symbol-prefix=_
 KBUILD_DEFCONFIG := BF537-STAMP_defconfig
@ -137,7 +138,7 @@ archclean:
 INSTALL_PATH ?= /tftpboot
 boot := arch/$(ARCH)/boot
-BOOT_TARGETS = vmImage vmImage.bz2 vmImage.gz vmImage.lzma
+BOOT_TARGETS = vmImage vmImage.bin vmImage.bz2 vmImage.gz vmImage.lzma
 PHONY += $(BOOT_TARGETS) install
 KBUILD_IMAGE := $(boot)/vmImage
@ -151,6 +152,7 @@ install:
 define archhelp
  echo  '* vmImage         - Alias to selected kernel format (vmImage.gz by default)'
  echo  '  vmImage.bin     - Uncompressed Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.bin)'
  echo  '  vmImage.bz2     - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.bz2)'
  echo  '* vmImage.gz      - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.gz)'
  echo  '  vmImage.lzma    - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.lzma)'
--- a/arch/blackfin/boot/Makefile
+++ b/arch/blackfin/boot/Makefile
@ -8,7 +8,7 @@
 MKIMAGE := $(srctree)/scripts/mkuboot.sh
-targets := vmImage vmImage.bz2 vmImage.gz vmImage.lzma
+targets := vmImage vmImage.bin vmImage.bz2 vmImage.gz vmImage.lzma
 extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma
 quiet_cmd_uimage = UIMAGE  $@
@ -29,6 +29,9 @@ $(obj)/vmlinux.bin.bz2: $(obj)/vmlinux.bin FORCE
 $(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin FORCE
 	$(call if_changed,lzma)
 $(obj)/vmImage.bin: $(obj)/vmlinux.bin
 	$(call if_changed,uimage,none)
 $(obj)/vmImage.bz2: $(obj)/vmlinux.bin.bz2
 	$(call if_changed,uimage,bzip2)
@ -38,6 +41,7 @@ $(obj)/vmImage.gz: $(obj)/vmlinux.bin.gz
 $(obj)/vmImage.lzma: $(obj)/vmlinux.bin.lzma
 	$(call if_changed,uimage,lzma)
 suffix-y                      := bin
 suffix-$(CONFIG_KERNEL_GZIP)  := gz
 suffix-$(CONFIG_KERNEL_BZIP2) := bz2
 suffix-$(CONFIG_KERNEL_LZMA)  := lzma
--- a/arch/blackfin/configs/BF518F-EZBRD_defconfig
+++ b/arch/blackfin/configs/BF518F-EZBRD_defconfig
@ -67,6 +67,7 @@ CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
 CONFIG_MMAP_ALLOW_UNINITIALIZED=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
@ -316,6 +317,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
 CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 CONFIG_BFIN_GPTIMERS=m
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
@ -438,17 +440,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
-CONFIG_NET_DSA=y
+# CONFIG_NET_DSA is not set
 # CONFIG_NET_DSA_TAG_DSA is not set
 # CONFIG_NET_DSA_TAG_EDSA is not set
 # CONFIG_NET_DSA_TAG_TRAILER is not set
 CONFIG_NET_DSA_TAG_STPID=y
 # CONFIG_NET_DSA_MV88E6XXX is not set
 # CONFIG_NET_DSA_MV88E6060 is not set
 # CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set
 # CONFIG_NET_DSA_MV88E6131 is not set
 # CONFIG_NET_DSA_MV88E6123_61_65 is not set
 CONFIG_NET_DSA_KSZ8893M=y
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 # CONFIG_LLC2 is not set
--- a/arch/blackfin/configs/BF526-EZBRD_defconfig
+++ b/arch/blackfin/configs/BF526-EZBRD_defconfig
@ -67,6 +67,7 @@ CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
 CONFIG_MMAP_ALLOW_UNINITIALIZED=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
@ -321,6 +322,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
 CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 CONFIG_BFIN_GPTIMERS=m
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
--- a/arch/blackfin/configs/BF527-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF527-EZKIT_defconfig
@ -67,6 +67,7 @@ CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
 CONFIG_MMAP_ALLOW_UNINITIALIZED=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
@ -321,6 +322,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
 CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 CONFIG_BFIN_GPTIMERS=y
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
--- a/arch/blackfin/configs/BF533-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF533-EZKIT_defconfig
@ -67,6 +67,7 @@ CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
 CONFIG_MMAP_ALLOW_UNINITIALIZED=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
@ -283,6 +284,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
 CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 CONFIG_BFIN_GPTIMERS=m
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
--- a/arch/blackfin/configs/BF533-STAMP_defconfig
+++ b/arch/blackfin/configs/BF533-STAMP_defconfig
@ -67,6 +67,7 @@ CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
 CONFIG_MMAP_ALLOW_UNINITIALIZED=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
@ -283,6 +284,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
 CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 CONFIG_BFIN_GPTIMERS=m
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
--- a/arch/blackfin/configs/BF537-STAMP_defconfig
+++ b/arch/blackfin/configs/BF537-STAMP_defconfig
@ -67,6 +67,7 @@ CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
 CONFIG_MMAP_ALLOW_UNINITIALIZED=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
@ -290,6 +291,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
 CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 CONFIG_BFIN_GPTIMERS=m
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
@ -704,10 +706,7 @@ CONFIG_CONFIG_INPUT_PCF8574=m
 #
 # Hardware I/O ports
 #
-CONFIG_SERIO=y
+# CONFIG_SERIO is not set
 CONFIG_SERIO_SERPORT=y
 CONFIG_SERIO_LIBPS2=y
 # CONFIG_SERIO_RAW is not set
 # CONFIG_GAMEPORT is not set
 #
--- a/arch/blackfin/configs/BF538-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF538-EZKIT_defconfig
@ -67,6 +67,7 @@ CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
 CONFIG_MMAP_ALLOW_UNINITIALIZED=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
@ -301,6 +302,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
 CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 CONFIG_BFIN_GPTIMERS=m
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
--- a/arch/blackfin/configs/BF548-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF548-EZKIT_defconfig
@ -1,22 +1,29 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.28.10
+# Linux kernel version: 2.6.31.5
-# Thu May 21 05:50:01 2009
+# Mon Nov  2 22:02:56 2009
 #
 # CONFIG_MMU is not set
 # CONFIG_FPU is not set
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
 CONFIG_BLACKFIN=y
 CONFIG_GENERIC_CSUM=y
 CONFIG_GENERIC_BUG=y
 CONFIG_ZONE_DMA=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_GENERIC_GPIO=y
 CONFIG_FORCE_MAX_ZONEORDER=14
 CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 CONFIG_CONSTRUCTORS=y
 #
 # General setup
@ -26,22 +33,40 @@ CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
 CONFIG_HAVE_KERNEL_GZIP=y
 CONFIG_HAVE_KERNEL_BZIP2=y
 CONFIG_HAVE_KERNEL_LZMA=y
 CONFIG_KERNEL_GZIP=y
 # CONFIG_KERNEL_BZIP2 is not set
 # CONFIG_KERNEL_LZMA is not set
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
 #
 # RCU Subsystem
 #
 CONFIG_CLASSIC_RCU=y
 # CONFIG_TREE_RCU is not set
 # CONFIG_PREEMPT_RCU is not set
 # CONFIG_TREE_RCU_TRACE is not set
 # CONFIG_PREEMPT_RCU_TRACE is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_CGROUPS is not set
 # CONFIG_GROUP_SCHED is not set
 # CONFIG_CGROUPS is not set
 # CONFIG_SYSFS_DEPRECATED_V2 is not set
 # CONFIG_RELAY is not set
 # CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 CONFIG_RD_GZIP=y
 # CONFIG_RD_BZIP2 is not set
 # CONFIG_RD_LZMA is not set
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SYSCTL=y
 CONFIG_ANON_INODES=y
@ -62,17 +87,28 @@ CONFIG_EPOLL=y
 # CONFIG_TIMERFD is not set
 # CONFIG_EVENTFD is not set
 # CONFIG_AIO is not set
 #
 # Performance Counters
 #
 CONFIG_VM_EVENT_COUNTERS=y
 # CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
 CONFIG_MMAP_ALLOW_UNINITIALIZED=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
 #
 # GCOV-based kernel profiling
 #
 # CONFIG_GCOV_KERNEL is not set
 # CONFIG_SLOW_WORK is not set
 # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
 # CONFIG_MODULE_FORCE_LOAD is not set
@ -80,11 +116,8 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
 CONFIG_BLOCK=y
-# CONFIG_LBD is not set
+# CONFIG_LBDAF is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
@ -94,13 +127,12 @@ CONFIG_BLOCK=y
 CONFIG_IOSCHED_NOOP=y
 CONFIG_IOSCHED_AS=y
 # CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_IOSCHED_CFQ=y
+# CONFIG_IOSCHED_CFQ is not set
 CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_DEADLINE is not set
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
 CONFIG_CLASSIC_RCU=y
 # CONFIG_PREEMPT_NONE is not set
 CONFIG_PREEMPT_VOLUNTARY=y
 # CONFIG_PREEMPT is not set
@ -137,7 +169,7 @@ CONFIG_PREEMPT_VOLUNTARY=y
 # CONFIG_BF544M is not set
 # CONFIG_BF547 is not set
 # CONFIG_BF547M is not set
-CONFIG_BF548=y
+CONFIG_BF548_std=y
 # CONFIG_BF548M is not set
 # CONFIG_BF549 is not set
 # CONFIG_BF549M is not set
@ -195,7 +227,7 @@ CONFIG_BFIN548_EZKIT=y
 #
 # BF548 Specific Configuration
 #
-# CONFIG_DEB_DMA_URGENT is not set
+CONFIG_DEB_DMA_URGENT=y
 # CONFIG_BF548_ATAPI_ALTERNATIVE_PORT is not set
 #
@ -352,10 +384,11 @@ CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
 CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 CONFIG_BFIN_GPTIMERS=m
 # CONFIG_DMA_UNCACHED_4M is not set
 CONFIG_DMA_UNCACHED_2M=y
@ -366,14 +399,13 @@ CONFIG_DMA_UNCACHED_2M=y
 # Cache Support
 #
 CONFIG_BFIN_ICACHE=y
-# CONFIG_BFIN_ICACHE_LOCK is not set
+CONFIG_BFIN_EXTMEM_ICACHEABLE=y
 # CONFIG_BFIN_L2_ICACHEABLE is not set
 CONFIG_BFIN_DCACHE=y
 # CONFIG_BFIN_DCACHE_BANKA is not set
 CONFIG_BFIN_EXTMEM_ICACHEABLE=y
 CONFIG_BFIN_EXTMEM_DCACHEABLE=y
-CONFIG_BFIN_EXTMEM_WRITEBACK=y
+# CONFIG_BFIN_EXTMEM_WRITEBACK is not set
-# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
+CONFIG_BFIN_EXTMEM_WRITETHROUGH=y
 # CONFIG_BFIN_L2_ICACHEABLE is not set
 # CONFIG_BFIN_L2_DCACHEABLE is not set
 #
@ -382,7 +414,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y
 # CONFIG_MPU is not set
 #
-# Asynchonous Memory Configuration
+# Asynchronous Memory Configuration
 #
 #
@ -441,11 +473,6 @@ CONFIG_NET=y
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
 CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
 # CONFIG_XFRM_SUB_POLICY is not set
 # CONFIG_XFRM_MIGRATE is not set
 # CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
@ -469,13 +496,11 @@ CONFIG_IP_PNP=y
 # CONFIG_INET_XFRM_MODE_BEET is not set
 # CONFIG_INET_LRO is not set
 # CONFIG_INET_DIAG is not set
 CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
 # CONFIG_NETLABEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
 # CONFIG_IP_DCCP is not set
@ -493,7 +518,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
 # CONFIG_PHONET is not set
 # CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
 # CONFIG_DCB is not set
 #
 # Network testing
@ -548,14 +576,10 @@ CONFIG_SIR_BFIN_DMA=y
 # CONFIG_MCS_FIR is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
-# CONFIG_PHONET is not set
+# CONFIG_WIRELESS is not set
 CONFIG_WIRELESS=y
 # CONFIG_CFG80211 is not set
 CONFIG_WIRELESS_OLD_REGULATORY=y
 CONFIG_WIRELESS_EXT=y
-CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_LIB80211=m
-# CONFIG_MAC80211 is not set
+# CONFIG_WIMAX is not set
 # CONFIG_IEEE80211 is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
@ -578,6 +602,7 @@ CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 # CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
@ -653,7 +678,6 @@ CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_VERIFY_WRITE is not set
 # CONFIG_MTD_NAND_ECC_SMC is not set
 # CONFIG_MTD_NAND_MUSEUM_IDS is not set
 # CONFIG_MTD_NAND_BFIN is not set
 CONFIG_MTD_NAND_IDS=y
 CONFIG_MTD_NAND_BF5XX=y
 CONFIG_MTD_NAND_BF5XX_HWECC=y
@ -664,6 +688,11 @@ CONFIG_MTD_NAND_BF5XX_HWECC=y
 # CONFIG_MTD_ALAUDA is not set
 # CONFIG_MTD_ONENAND is not set
 #
 # LPDDR flash memory drivers
 #
 # CONFIG_MTD_LPDDR is not set
 #
 # UBI - Unsorted block images
 #
@ -682,10 +711,20 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
 # CONFIG_ATA_OVER_ETH is not set
 # CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_93CX6 is not set
 # CONFIG_ICS932S401 is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
 # CONFIG_ISL29003 is not set
 # CONFIG_AD525X_DPOT is not set
 # CONFIG_C2PORT is not set
 #
 # EEPROM support
 #
 # CONFIG_EEPROM_AT24 is not set
 # CONFIG_EEPROM_AT25 is not set
 # CONFIG_EEPROM_LEGACY is not set
 # CONFIG_EEPROM_MAX6875 is not set
 # CONFIG_EEPROM_93CX6 is not set
 CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
@ -709,10 +748,6 @@ CONFIG_BLK_DEV_SR=m
 # CONFIG_BLK_DEV_SR_VENDOR is not set
 # CONFIG_CHR_DEV_SG is not set
 # CONFIG_CHR_DEV_SCH is not set
 #
 # Some SCSI devices (e.g. CD jukebox) support multiple LUNs
 #
 # CONFIG_SCSI_MULTI_LUN is not set
 # CONFIG_SCSI_CONSTANTS is not set
 # CONFIG_SCSI_LOGGING is not set
@ -729,6 +764,7 @@ CONFIG_SCSI_WAIT_SCAN=m
 # CONFIG_SCSI_SRP_ATTRS is not set
 # CONFIG_SCSI_LOWLEVEL is not set
 # CONFIG_SCSI_DH is not set
 # CONFIG_SCSI_OSD_INITIATOR is not set
 CONFIG_ATA=y
 # CONFIG_ATA_NONSTANDARD is not set
 CONFIG_SATA_PMP=y
@ -744,13 +780,34 @@ CONFIG_NETDEVICES=y
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
 # CONFIG_VETH is not set
-# CONFIG_PHYLIB is not set
+CONFIG_PHYLIB=y
 #
 # MII PHY device drivers
 #
 # CONFIG_MARVELL_PHY is not set
 # CONFIG_DAVICOM_PHY is not set
 # CONFIG_QSEMI_PHY is not set
 # CONFIG_LXT_PHY is not set
 # CONFIG_CICADA_PHY is not set
 # CONFIG_VITESSE_PHY is not set
 # CONFIG_SMSC_PHY is not set
 # CONFIG_BROADCOM_PHY is not set
 # CONFIG_ICPLUS_PHY is not set
 # CONFIG_REALTEK_PHY is not set
 # CONFIG_NATIONAL_PHY is not set
 # CONFIG_STE10XP is not set
 # CONFIG_LSI_ET1011C_PHY is not set
 # CONFIG_FIXED_PHY is not set
 # CONFIG_MDIO_BITBANG is not set
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
 # CONFIG_SMC91X is not set
 CONFIG_SMSC911X=y
 # CONFIG_DM9000 is not set
 # CONFIG_ENC28J60 is not set
 # CONFIG_ETHOC is not set
 CONFIG_SMSC911X=y
 # CONFIG_DNET is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
 # CONFIG_IBM_NEW_EMAC_TAH is not set
@ -759,6 +816,8 @@ CONFIG_SMSC911X=y
 # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
 # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 # CONFIG_B44 is not set
 # CONFIG_KS8842 is not set
 # CONFIG_KS8851 is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
@ -771,12 +830,15 @@ CONFIG_LIBERTAS=m
 # CONFIG_LIBERTAS_USB is not set
 CONFIG_LIBERTAS_SDIO=m
 CONFIG_POWEROF2_BLOCKSIZE_ONLY=y
 # CONFIG_LIBERTAS_SPI is not set
 # CONFIG_LIBERTAS_DEBUG is not set
 # CONFIG_USB_ZD1201 is not set
 # CONFIG_USB_NET_RNDIS_WLAN is not set
 # CONFIG_IWLWIFI_LEDS is not set
 # CONFIG_HOSTAP is not set
 #
 # Enable WiMAX (Networking options) to see the WiMAX drivers
 #
 #
 # USB Network Adapters
 #
@ -813,28 +875,31 @@ CONFIG_INPUT_EVBUG=m
 # Input Device Drivers
 #
 CONFIG_INPUT_KEYBOARD=y
 # CONFIG_KEYBOARD_ATKBD is not set
 # CONFIG_KEYBOARD_SUNKBD is not set
 # CONFIG_KEYBOARD_LKKBD is not set
 # CONFIG_KEYBOARD_XTKBD is not set
 # CONFIG_KEYBOARD_NEWTON is not set
 # CONFIG_KEYBOARD_STOWAWAY is not set
 # CONFIG_KEYBOARD_GPIO is not set
 CONFIG_KEYBOARD_BFIN=y
 # CONFIG_KEYBOARD_OPENCORES is not set
 # CONFIG_KEYBOARD_ADP5588 is not set
 # CONFIG_KEYBOARD_ATKBD is not set
 CONFIG_KEYBOARD_BFIN=y
 # CONFIG_KEYBOARD_LKKBD is not set
 # CONFIG_KEYBOARD_GPIO is not set
 # CONFIG_KEYBOARD_MATRIX is not set
 # CONFIG_KEYBOARD_NEWTON is not set
 # CONFIG_KEYBOARD_OPENCORES is not set
 # CONFIG_KEYBOARD_STOWAWAY is not set
 # CONFIG_KEYBOARD_SUNKBD is not set
 # CONFIG_KEYBOARD_XTKBD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
 # CONFIG_INPUT_TABLET is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 # CONFIG_TOUCHSCREEN_ADS7846 is not set
 CONFIG_TOUCHSCREEN_AD7877=m
 # CONFIG_TOUCHSCREEN_AD7879_I2C is not set
 # CONFIG_TOUCHSCREEN_AD7879_SPI is not set
 # CONFIG_TOUCHSCREEN_AD7879 is not set
-# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
 # CONFIG_TOUCHSCREEN_FUJITSU is not set
 # CONFIG_TOUCHSCREEN_GUNZE is not set
 # CONFIG_TOUCHSCREEN_ELO is not set
 # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
 # CONFIG_TOUCHSCREEN_MTOUCH is not set
 # CONFIG_TOUCHSCREEN_INEXIO is not set
 # CONFIG_TOUCHSCREEN_MK712 is not set
@ -844,6 +909,8 @@ CONFIG_TOUCHSCREEN_AD7877=m
 # CONFIG_TOUCHSCREEN_WM97XX is not set
 # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
 # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
 # CONFIG_TOUCHSCREEN_TSC2007 is not set
 # CONFIG_TOUCHSCREEN_W90X900 is not set
 CONFIG_INPUT_MISC=y
 # CONFIG_INPUT_ATI_REMOTE is not set
 # CONFIG_INPUT_ATI_REMOTE2 is not set
@ -852,7 +919,11 @@ CONFIG_INPUT_MISC=y
 # CONFIG_INPUT_YEALINK is not set
 # CONFIG_INPUT_CM109 is not set
 # CONFIG_INPUT_UINPUT is not set
-# CONFIG_CONFIG_INPUT_PCF8574 is not set
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
 # CONFIG_INPUT_BFIN_ROTARY is not set
 # CONFIG_INPUT_AD714X is not set
 # CONFIG_INPUT_ADXL34X is not set
 # CONFIG_INPUT_PCF8574 is not set
 #
 # Hardware I/O ports
@ -863,16 +934,13 @@ CONFIG_INPUT_MISC=y
 #
 # Character devices
 #
 # CONFIG_AD9960 is not set
 CONFIG_BFIN_DMA_INTERFACE=m
 # CONFIG_BFIN_PPI is not set
 # CONFIG_BFIN_PPIFCD is not set
 # CONFIG_BFIN_SIMPLE_TIMER is not set
 # CONFIG_BFIN_SPI_ADC is not set
 CONFIG_BFIN_SPORT=m
 # CONFIG_BFIN_TIMER_LATENCY is not set
 # CONFIG_BFIN_TWI_LCD is not set
 CONFIG_SIMPLE_GPIO=m
 CONFIG_VT=y
 CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
@ -890,6 +958,7 @@ CONFIG_BFIN_JTAG_COMM=m
 #
 # Non-8250 serial port support
 #
 # CONFIG_SERIAL_MAX3100 is not set
 CONFIG_SERIAL_BFIN=y
 CONFIG_SERIAL_BFIN_CONSOLE=y
 CONFIG_SERIAL_BFIN_DMA=y
@ -903,6 +972,7 @@ CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_SERIAL_BFIN_SPORT is not set
 CONFIG_UNIX98_PTYS=y
 # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 # CONFIG_LEGACY_PTYS is not set
 CONFIG_BFIN_OTP=y
 # CONFIG_BFIN_OTP_WRITE_ENABLE is not set
@ -951,14 +1021,9 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
 # Miscellaneous I2C Chip support
 #
 # CONFIG_DS1682 is not set
 # CONFIG_EEPROM_AT24 is not set
 # CONFIG_SENSORS_AD5252 is not set
 # CONFIG_EEPROM_LEGACY is not set
 # CONFIG_SENSORS_PCF8574 is not set
 # CONFIG_PCF8575 is not set
 # CONFIG_SENSORS_PCA9539 is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
@ -975,13 +1040,18 @@ CONFIG_SPI_BFIN=y
 # CONFIG_SPI_BFIN_LOCK is not set
 # CONFIG_SPI_BFIN_SPORT is not set
 # CONFIG_SPI_BITBANG is not set
 # CONFIG_SPI_GPIO is not set
 #
 # SPI Protocol Masters
 #
 # CONFIG_EEPROM_AT25 is not set
 # CONFIG_SPI_SPIDEV is not set
 # CONFIG_SPI_TLE62X0 is not set
 #
 # PPS support
 #
 # CONFIG_PPS is not set
 CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
 CONFIG_GPIOLIB=y
 # CONFIG_DEBUG_GPIO is not set
@ -997,6 +1067,7 @@ CONFIG_GPIO_SYSFS=y
 # CONFIG_GPIO_MAX732X is not set
 # CONFIG_GPIO_PCA953X is not set
 # CONFIG_GPIO_PCF857X is not set
 # CONFIG_GPIO_ADP5588 is not set
 #
 # PCI GPIO expanders:
@ -1038,28 +1109,19 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
 # CONFIG_UCB1400_CORE is not set
 # CONFIG_TPS65010 is not set
 # CONFIG_TWL4030_CORE is not set
 # CONFIG_MFD_TMIO is not set
 # CONFIG_PMIC_DA903X is not set
 # CONFIG_PMIC_ADP5520 is not set
 # CONFIG_MFD_WM8400 is not set
 # CONFIG_MFD_WM8350_I2C is not set
 # CONFIG_MFD_PCF50633 is not set
 # CONFIG_AB3100_CORE is not set
 # CONFIG_EZX_PCAP is not set
 # CONFIG_REGULATOR is not set
-
+# CONFIG_MEDIA_SUPPORT is not set
 #
 # Multimedia devices
 #
 #
 # Multimedia core support
 #
 # CONFIG_VIDEO_DEV is not set
 # CONFIG_DVB_CORE is not set
 # CONFIG_VIDEO_MEDIA is not set
 #
 # Multimedia drivers
 #
 # CONFIG_DAB is not set
 #
 # Graphics support
@ -1096,6 +1158,7 @@ CONFIG_FB_BF54X_LQ043=y
 # CONFIG_FB_VIRTUAL is not set
 # CONFIG_FB_METRONOME is not set
 # CONFIG_FB_MB862XX is not set
 # CONFIG_FB_BROADSHEET is not set
 # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 #
@ -1132,6 +1195,7 @@ CONFIG_SOUND_OSS_CORE=y
 CONFIG_SND=y
 CONFIG_SND_TIMER=y
 CONFIG_SND_PCM=y
 CONFIG_SND_JACK=y
 # CONFIG_SND_SEQUENCER is not set
 CONFIG_SND_OSSEMUL=y
 CONFIG_SND_MIXER_OSS=y
@ -1142,6 +1206,11 @@ CONFIG_SND_SUPPORT_OLD_API=y
 CONFIG_SND_VERBOSE_PROCFS=y
 # CONFIG_SND_VERBOSE_PRINTK is not set
 # CONFIG_SND_DEBUG is not set
 # CONFIG_SND_RAWMIDI_SEQ is not set
 # CONFIG_SND_OPL3_LIB_SEQ is not set
 # CONFIG_SND_OPL4_LIB_SEQ is not set
 # CONFIG_SND_SBAWE_SEQ is not set
 # CONFIG_SND_EMU10K1_SEQ is not set
 CONFIG_SND_DRIVERS=y
 # CONFIG_SND_DUMMY is not set
 # CONFIG_SND_MTPAV is not set
@ -1152,7 +1221,6 @@ CONFIG_SND_SPI=y
 #
 # ALSA Blackfin devices
 #
 # CONFIG_SND_BLACKFIN_AD1836 is not set
 # CONFIG_SND_BFIN_AD73322 is not set
 CONFIG_SND_USB=y
 # CONFIG_SND_USB_AUDIO is not set
@ -1160,15 +1228,17 @@ CONFIG_SND_USB=y
 CONFIG_SND_SOC=y
 CONFIG_SND_SOC_AC97_BUS=y
 # CONFIG_SND_BF5XX_I2S is not set
 # CONFIG_SND_BF5XX_TDM is not set
 CONFIG_SND_BF5XX_AC97=y
 CONFIG_SND_BF5XX_MMAP_SUPPORT=y
 # CONFIG_SND_BF5XX_MULTICHAN_SUPPORT is not set
 CONFIG_SND_BF5XX_SOC_SPORT=y
 CONFIG_SND_BF5XX_SOC_AC97=y
 CONFIG_SND_BF5XX_SOC_AD1980=y
 CONFIG_SND_BF5XX_SPORT_NUM=0
 CONFIG_SND_BF5XX_HAVE_COLD_RESET=y
 CONFIG_SND_BF5XX_RESET_GPIO_NUM=19
 CONFIG_SND_BF5XX_SOC_AD1980=y
 CONFIG_SND_BF5XX_SOC_SPORT=y
 CONFIG_SND_BF5XX_SOC_AC97=y
 CONFIG_SND_BF5XX_SPORT_NUM=0
 CONFIG_SND_SOC_I2C_AND_SPI=y
 # CONFIG_SND_SOC_ALL_CODECS is not set
 CONFIG_SND_SOC_AD1980=y
 # CONFIG_SOUND_PRIME is not set
@ -1188,30 +1258,34 @@ CONFIG_USB_HID=y
 #
 # Special HID drivers
 #
 CONFIG_HID_COMPAT=y
 CONFIG_HID_A4TECH=y
 CONFIG_HID_APPLE=y
 CONFIG_HID_BELKIN=y
 CONFIG_HID_BRIGHT=y
 CONFIG_HID_CHERRY=y
 CONFIG_HID_CHICONY=y
 CONFIG_HID_CYPRESS=y
-CONFIG_HID_DELL=y
+# CONFIG_HID_DRAGONRISE is not set
 CONFIG_HID_EZKEY=y
 # CONFIG_HID_KYE is not set
 CONFIG_HID_GYRATION=y
 # CONFIG_HID_KENSINGTON is not set
 CONFIG_HID_LOGITECH=y
 # CONFIG_LOGITECH_FF is not set
 # CONFIG_LOGIRUMBLEPAD2_FF is not set
 CONFIG_HID_MICROSOFT=y
 CONFIG_HID_MONTEREY=y
 # CONFIG_HID_NTRIG is not set
 CONFIG_HID_PANTHERLORD=y
 # CONFIG_PANTHERLORD_FF is not set
 CONFIG_HID_PETALYNX=y
 CONFIG_HID_SAMSUNG=y
 CONFIG_HID_SONY=y
 CONFIG_HID_SUNPLUS=y
-CONFIG_THRUSTMASTER_FF=m
+# CONFIG_HID_GREENASIA is not set
-CONFIG_ZEROPLUS_FF=m
+# CONFIG_HID_SMARTJOYPLUS is not set
 # CONFIG_HID_TOPSEED is not set
 # CONFIG_HID_THRUSTMASTER is not set
 # CONFIG_HID_ZEROPLUS is not set
 CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 # CONFIG_USB_ARCH_HAS_OHCI is not set
@ -1237,6 +1311,7 @@ CONFIG_USB_MON=y
 # USB Host Controller Drivers
 #
 # CONFIG_USB_C67X00_HCD is not set
 # CONFIG_USB_OXU210HP_HCD is not set
 # CONFIG_USB_ISP116X_HCD is not set
 # CONFIG_USB_ISP1760_HCD is not set
 # CONFIG_USB_ISP1362_HCD is not set
@ -1267,18 +1342,17 @@ CONFIG_USB_INVENTRA_DMA=y
 # CONFIG_USB_TMC is not set
 #
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
 #
 #
-# see USB_STORAGE Help for more information
+# also be needed; see USB_STORAGE Help for more info
 #
 CONFIG_USB_STORAGE=y
 # CONFIG_USB_STORAGE_DEBUG is not set
 # CONFIG_USB_STORAGE_DATAFAB is not set
 # CONFIG_USB_STORAGE_FREECOM is not set
 # CONFIG_USB_STORAGE_ISD200 is not set
 # CONFIG_USB_STORAGE_DPCM is not set
 # CONFIG_USB_STORAGE_USBAT is not set
 # CONFIG_USB_STORAGE_SDDR09 is not set
 # CONFIG_USB_STORAGE_SDDR55 is not set
@ -1314,7 +1388,6 @@ CONFIG_USB_STORAGE=y
 # CONFIG_USB_LED is not set
 # CONFIG_USB_CYPRESS_CY7C63 is not set
 # CONFIG_USB_CYTHERM is not set
 # CONFIG_USB_PHIDGET is not set
 # CONFIG_USB_IDMOUSE is not set
 # CONFIG_USB_FTDI_ELAN is not set
 # CONFIG_USB_APPLEDISPLAY is not set
@ -1326,6 +1399,13 @@ CONFIG_USB_STORAGE=y
 # CONFIG_USB_ISIGHTFW is not set
 # CONFIG_USB_VST is not set
 # CONFIG_USB_GADGET is not set
 #
 # OTG and related infrastructure
 #
 CONFIG_USB_OTG_UTILS=y
 # CONFIG_USB_GPIO_VBUS is not set
 CONFIG_NOP_USB_XCEIV=y
 CONFIG_MMC=y
 # CONFIG_MMC_DEBUG is not set
 # CONFIG_MMC_UNSAFE_RESUME is not set
@ -1380,6 +1460,7 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_S35390A is not set
 # CONFIG_RTC_DRV_FM3130 is not set
 # CONFIG_RTC_DRV_RX8581 is not set
 # CONFIG_RTC_DRV_RX8025 is not set
 #
 # SPI RTC drivers
@ -1411,9 +1492,20 @@ CONFIG_RTC_INTF_DEV=y
 #
 CONFIG_RTC_DRV_BFIN=y
 # CONFIG_DMADEVICES is not set
 # CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
 #
 # TI VLYNQ
 #
 # CONFIG_STAGING is not set
 #
 # Firmware Drivers
 #
 # CONFIG_FIRMWARE_MEMMAP is not set
 # CONFIG_SIGMA is not set
 #
 # File systems
 #
@ -1427,9 +1519,11 @@ CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
 # CONFIG_OCFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
 CONFIG_FILE_LOCKING=y
 CONFIG_FSNOTIFY=y
 # CONFIG_DNOTIFY is not set
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@ -1438,6 +1532,11 @@ CONFIG_INOTIFY_USER=y
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
 #
 # Caches
 #
 # CONFIG_FSCACHE is not set
 #
 # CD-ROM/DVD Filesystems
 #
@ -1467,10 +1566,7 @@ CONFIG_SYSFS=y
 # CONFIG_TMPFS is not set
 # CONFIG_HUGETLB_PAGE is not set
 # CONFIG_CONFIGFS_FS is not set
-
+CONFIG_MISC_FILESYSTEMS=y
 #
 # Miscellaneous filesystems
 #
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
@ -1489,17 +1585,8 @@ CONFIG_JFFS2_ZLIB=y
 # CONFIG_JFFS2_LZO is not set
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
 CONFIG_YAFFS_FS=m
 CONFIG_YAFFS_YAFFS1=y
 # CONFIG_YAFFS_9BYTE_TAGS is not set
 # CONFIG_YAFFS_DOES_ECC is not set
 CONFIG_YAFFS_YAFFS2=y
 CONFIG_YAFFS_AUTO_YAFFS2=y
 # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
 # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
 # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
 CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
 # CONFIG_CRAMFS is not set
 # CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_OMFS_FS is not set
@ -1508,6 +1595,7 @@ CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
 # CONFIG_NILFS2_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
@ -1522,7 +1610,6 @@ CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=m
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=m
 # CONFIG_SUNRPC_REGISTER_V4 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@ -1596,11 +1683,15 @@ CONFIG_FRAME_WARN=1024
 # CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_SECTION_MISMATCH=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SHIRQ=y
 CONFIG_DETECT_SOFTLOCKUP=y
 # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
 CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
 CONFIG_DETECT_HUNG_TASK=y
 # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
 CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
 CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
@ -1608,16 +1699,21 @@ CONFIG_SCHED_DEBUG=y
 # CONFIG_DEBUG_SLAB is not set
 # CONFIG_DEBUG_SPINLOCK is not set
 # CONFIG_DEBUG_MUTEXES is not set
 # CONFIG_DEBUG_LOCK_ALLOC is not set
 # CONFIG_PROVE_LOCKING is not set
 # CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
 CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_DEBUG_INFO=y
 # CONFIG_DEBUG_VM is not set
 # CONFIG_DEBUG_NOMMU_REGIONS is not set
 # CONFIG_DEBUG_WRITECOUNT is not set
 # CONFIG_DEBUG_MEMORY_INIT is not set
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
 # CONFIG_DEBUG_NOTIFIERS is not set
 # CONFIG_FRAME_POINTER is not set
 # CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
@ -1625,17 +1721,16 @@ CONFIG_DEBUG_INFO=y
 # CONFIG_BACKTRACE_SELF_TEST is not set
 # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
 # CONFIG_FAULT_INJECTION is not set
-
+# CONFIG_PAGE_POISONING is not set
-#
+CONFIG_HAVE_FUNCTION_TRACER=y
-# Tracers
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-#
+CONFIG_TRACING_SUPPORT=y
-# CONFIG_SCHED_TRACER is not set
+# CONFIG_FTRACE is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_BOOT_TRACER is not set
 # CONFIG_DYNAMIC_PRINTK_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_KGDB is not set
 # CONFIG_KMEMCHECK is not set
 # CONFIG_DEBUG_STACKOVERFLOW is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
 CONFIG_DEBUG_VERBOSE=y
@ -1657,17 +1752,15 @@ CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE=y
 CONFIG_EARLY_PRINTK=y
 CONFIG_CPLB_INFO=y
 CONFIG_ACCESS_CHECK=y
 # CONFIG_BFIN_ISRAM_SELF_TEST is not set
 #
 # Security options
 #
 # CONFIG_KEYS is not set
-CONFIG_SECURITY=y
+# CONFIG_SECURITY is not set
 # CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_NETWORK is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
 # CONFIG_SECURITY_ROOTPLUG is not set
 CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
 CONFIG_CRYPTO=y
 #
@ -1746,6 +1839,7 @@ CONFIG_CRYPTO=y
 # Compression
 #
 # CONFIG_CRYPTO_DEFLATE is not set
 # CONFIG_CRYPTO_ZLIB is not set
 # CONFIG_CRYPTO_LZO is not set
 #
@ -1753,11 +1847,13 @@ CONFIG_CRYPTO=y
 #
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRYPTO_HW=y
 # CONFIG_BINARY_PRINTF is not set
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
 CONFIG_GENERIC_FIND_LAST_BIT=y
 CONFIG_CRC_CCITT=m
 # CONFIG_CRC16 is not set
 # CONFIG_CRC_T10DIF is not set
@ -1767,6 +1863,8 @@ CONFIG_CRC32=y
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=m
 CONFIG_DECOMPRESS_GZIP=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
 CONFIG_NLATTR=y
--- a/arch/blackfin/configs/BF561-ACVILON_defconfig
+++ b/arch/blackfin/configs/BF561-ACVILON_defconfig
--- a/arch/blackfin/configs/BF561-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF561-EZKIT_defconfig
@ -1,22 +1,29 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.28.10
+# Linux kernel version: 2.6.31.5
-# Thu May 21 05:50:01 2009
+# Mon Nov  2 21:59:31 2009
 #
 # CONFIG_MMU is not set
 # CONFIG_FPU is not set
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
 CONFIG_BLACKFIN=y
 CONFIG_GENERIC_CSUM=y
 CONFIG_GENERIC_BUG=y
 CONFIG_ZONE_DMA=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_GENERIC_GPIO=y
 CONFIG_FORCE_MAX_ZONEORDER=14
 CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 CONFIG_CONSTRUCTORS=y
 #
 # General setup
@ -26,22 +33,40 @@ CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
 CONFIG_HAVE_KERNEL_GZIP=y
 CONFIG_HAVE_KERNEL_BZIP2=y
 CONFIG_HAVE_KERNEL_LZMA=y
 CONFIG_KERNEL_GZIP=y
 # CONFIG_KERNEL_BZIP2 is not set
 # CONFIG_KERNEL_LZMA is not set
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
 #
 # RCU Subsystem
 #
 CONFIG_CLASSIC_RCU=y
 # CONFIG_TREE_RCU is not set
 # CONFIG_PREEMPT_RCU is not set
 # CONFIG_TREE_RCU_TRACE is not set
 # CONFIG_PREEMPT_RCU_TRACE is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_CGROUPS is not set
 # CONFIG_GROUP_SCHED is not set
 # CONFIG_CGROUPS is not set
 # CONFIG_SYSFS_DEPRECATED_V2 is not set
 # CONFIG_RELAY is not set
 # CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 CONFIG_RD_GZIP=y
 # CONFIG_RD_BZIP2 is not set
 # CONFIG_RD_LZMA is not set
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SYSCTL=y
 CONFIG_ANON_INODES=y
@ -62,17 +87,28 @@ CONFIG_EPOLL=y
 # CONFIG_TIMERFD is not set
 # CONFIG_EVENTFD is not set
 # CONFIG_AIO is not set
 #
 # Performance Counters
 #
 CONFIG_VM_EVENT_COUNTERS=y
 # CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
 CONFIG_MMAP_ALLOW_UNINITIALIZED=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
 #
 # GCOV-based kernel profiling
 #
 # CONFIG_GCOV_KERNEL is not set
 # CONFIG_SLOW_WORK is not set
 # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
 # CONFIG_MODULE_FORCE_LOAD is not set
@ -80,11 +116,8 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
 CONFIG_BLOCK=y
-# CONFIG_LBD is not set
+# CONFIG_LBDAF is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
@ -94,13 +127,12 @@ CONFIG_BLOCK=y
 CONFIG_IOSCHED_NOOP=y
 CONFIG_IOSCHED_AS=y
 # CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_IOSCHED_CFQ=y
+# CONFIG_IOSCHED_CFQ is not set
 CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_DEADLINE is not set
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
 CONFIG_CLASSIC_RCU=y
 # CONFIG_PREEMPT_NONE is not set
 CONFIG_PREEMPT_VOLUNTARY=y
 # CONFIG_PREEMPT is not set
@ -170,6 +202,7 @@ CONFIG_IRQ_SPI_ERROR=7
 CONFIG_BFIN561_EZKIT=y
 # CONFIG_BFIN561_TEPLA is not set
 # CONFIG_BFIN561_BLUETECHNIX_CM is not set
 # CONFIG_BFIN561_ACVILON is not set
 #
 # BF561 Specific Configuration
@ -317,10 +350,11 @@ CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
 CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 CONFIG_BFIN_GPTIMERS=m
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
@ -331,14 +365,13 @@ CONFIG_DMA_UNCACHED_1M=y
 # Cache Support
 #
 CONFIG_BFIN_ICACHE=y
-# CONFIG_BFIN_ICACHE_LOCK is not set
+CONFIG_BFIN_EXTMEM_ICACHEABLE=y
 # CONFIG_BFIN_L2_ICACHEABLE is not set
 CONFIG_BFIN_DCACHE=y
 # CONFIG_BFIN_DCACHE_BANKA is not set
 CONFIG_BFIN_EXTMEM_ICACHEABLE=y
 CONFIG_BFIN_EXTMEM_DCACHEABLE=y
 CONFIG_BFIN_EXTMEM_WRITEBACK=y
 # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
 # CONFIG_BFIN_L2_ICACHEABLE is not set
 # CONFIG_BFIN_L2_DCACHEABLE is not set
 #
@ -347,7 +380,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y
 # CONFIG_MPU is not set
 #
-# Asynchonous Memory Configuration
+# Asynchronous Memory Configuration
 #
 #
@ -407,11 +440,6 @@ CONFIG_NET=y
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
 CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
 # CONFIG_XFRM_SUB_POLICY is not set
 # CONFIG_XFRM_MIGRATE is not set
 # CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
@ -435,13 +463,11 @@ CONFIG_IP_PNP=y
 # CONFIG_INET_XFRM_MODE_BEET is not set
 # CONFIG_INET_LRO is not set
 # CONFIG_INET_DIAG is not set
 CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
 # CONFIG_NETLABEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
 # CONFIG_IP_DCCP is not set
@ -459,7 +485,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
 # CONFIG_PHONET is not set
 # CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
 # CONFIG_DCB is not set
 #
 # Network testing
@ -503,13 +532,8 @@ CONFIG_IRTTY_SIR=m
 #
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
-# CONFIG_PHONET is not set
+# CONFIG_WIRELESS is not set
-CONFIG_WIRELESS=y
+# CONFIG_WIMAX is not set
 # CONFIG_CFG80211 is not set
 CONFIG_WIRELESS_OLD_REGULATORY=y
 # CONFIG_WIRELESS_EXT is not set
 # CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
@ -530,6 +554,7 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 # CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
@ -602,6 +627,11 @@ CONFIG_MTD_PHYSMAP=m
 # CONFIG_MTD_NAND is not set
 # CONFIG_MTD_ONENAND is not set
 #
 # LPDDR flash memory drivers
 #
 # CONFIG_MTD_LPDDR is not set
 #
 # UBI - Unsorted block images
 #
@ -619,9 +649,14 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
 # CONFIG_ATA_OVER_ETH is not set
 # CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_93CX6 is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
 # CONFIG_C2PORT is not set
 #
 # EEPROM support
 #
 # CONFIG_EEPROM_AT25 is not set
 # CONFIG_EEPROM_93CX6 is not set
 CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
@ -645,9 +680,11 @@ CONFIG_NETDEVICES=y
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
 CONFIG_SMC91X=y
 # CONFIG_SMSC911X is not set
 # CONFIG_DM9000 is not set
 # CONFIG_ENC28J60 is not set
 # CONFIG_ETHOC is not set
 # CONFIG_SMSC911X is not set
 # CONFIG_DNET is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
 # CONFIG_IBM_NEW_EMAC_TAH is not set
@ -656,6 +693,8 @@ CONFIG_SMC91X=y
 # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
 # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 # CONFIG_B44 is not set
 # CONFIG_KS8842 is not set
 # CONFIG_KS8851 is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
@ -664,7 +703,10 @@ CONFIG_SMC91X=y
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
-# CONFIG_IWLWIFI_LEDS is not set
+
 #
 # Enable WiMAX (Networking options) to see the WiMAX drivers
 #
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
@ -708,15 +750,12 @@ CONFIG_INPUT_EVDEV=m
 #
 # Character devices
 #
 # CONFIG_AD9960 is not set
 CONFIG_BFIN_DMA_INTERFACE=m
 # CONFIG_BFIN_PPI is not set
 # CONFIG_BFIN_PPIFCD is not set
 # CONFIG_BFIN_SIMPLE_TIMER is not set
 # CONFIG_BFIN_SPI_ADC is not set
 # CONFIG_BFIN_SPORT is not set
 # CONFIG_BFIN_TIMER_LATENCY is not set
 CONFIG_SIMPLE_GPIO=m
 # CONFIG_VT is not set
 # CONFIG_DEVKMEM is not set
 CONFIG_BFIN_JTAG_COMM=m
@ -730,6 +769,7 @@ CONFIG_BFIN_JTAG_COMM=m
 #
 # Non-8250 serial port support
 #
 # CONFIG_SERIAL_MAX3100 is not set
 CONFIG_SERIAL_BFIN=y
 CONFIG_SERIAL_BFIN_CONSOLE=y
 CONFIG_SERIAL_BFIN_DMA=y
@ -740,6 +780,7 @@ CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_SERIAL_BFIN_SPORT is not set
 CONFIG_UNIX98_PTYS=y
 # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 # CONFIG_LEGACY_PTYS is not set
 #
@ -763,13 +804,18 @@ CONFIG_SPI_BFIN=y
 # CONFIG_SPI_BFIN_LOCK is not set
 # CONFIG_SPI_BFIN_SPORT is not set
 # CONFIG_SPI_BITBANG is not set
 # CONFIG_SPI_GPIO is not set
 #
 # SPI Protocol Masters
 #
 # CONFIG_EEPROM_AT25 is not set
 # CONFIG_SPI_SPIDEV is not set
 # CONFIG_SPI_TLE62X0 is not set
 #
 # PPS support
 #
 # CONFIG_PPS is not set
 CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
 CONFIG_GPIOLIB=y
 # CONFIG_DEBUG_GPIO is not set
@ -782,9 +828,6 @@ CONFIG_GPIO_SYSFS=y
 #
 # I2C GPIO expanders:
 #
 # CONFIG_GPIO_MAX732X is not set
 # CONFIG_GPIO_PCA953X is not set
 # CONFIG_GPIO_PCF857X is not set
 #
 # PCI GPIO expanders:
@ -822,23 +865,9 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
 # CONFIG_MFD_TMIO is not set
 # CONFIG_EZX_PCAP is not set
 # CONFIG_REGULATOR is not set
-
+# CONFIG_MEDIA_SUPPORT is not set
 #
 # Multimedia devices
 #
 #
 # Multimedia core support
 #
 # CONFIG_VIDEO_DEV is not set
 # CONFIG_DVB_CORE is not set
 # CONFIG_VIDEO_MEDIA is not set
 #
 # Multimedia drivers
 #
 # CONFIG_DAB is not set
 #
 # Graphics support
@ -862,7 +891,6 @@ CONFIG_HID=m
 #
 # Special HID drivers
 #
 CONFIG_HID_COMPAT=y
 # CONFIG_USB_SUPPORT is not set
 # CONFIG_MMC is not set
 # CONFIG_MEMSTICK is not set
@ -870,9 +898,19 @@ CONFIG_HID_COMPAT=y
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_RTC_CLASS is not set
 # CONFIG_DMADEVICES is not set
 # CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
 #
 # TI VLYNQ
 #
 # CONFIG_STAGING is not set
 #
 # Firmware Drivers
 #
 # CONFIG_FIRMWARE_MEMMAP is not set
 #
 # File systems
 #
@ -882,9 +920,11 @@ CONFIG_HID_COMPAT=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
 # CONFIG_OCFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
 CONFIG_FILE_LOCKING=y
 CONFIG_FSNOTIFY=y
 # CONFIG_DNOTIFY is not set
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@ -893,6 +933,11 @@ CONFIG_INOTIFY_USER=y
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
 #
 # Caches
 #
 # CONFIG_FSCACHE is not set
 #
 # CD-ROM/DVD Filesystems
 #
@ -915,10 +960,7 @@ CONFIG_SYSFS=y
 # CONFIG_TMPFS is not set
 # CONFIG_HUGETLB_PAGE is not set
 # CONFIG_CONFIGFS_FS is not set
-
+CONFIG_MISC_FILESYSTEMS=y
 #
 # Miscellaneous filesystems
 #
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
@ -937,17 +979,8 @@ CONFIG_JFFS2_ZLIB=y
 # CONFIG_JFFS2_LZO is not set
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
 CONFIG_YAFFS_FS=m
 CONFIG_YAFFS_YAFFS1=y
 # CONFIG_YAFFS_9BYTE_TAGS is not set
 # CONFIG_YAFFS_DOES_ECC is not set
 CONFIG_YAFFS_YAFFS2=y
 CONFIG_YAFFS_AUTO_YAFFS2=y
 # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
 # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
 # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
 CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
 # CONFIG_CRAMFS is not set
 # CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_OMFS_FS is not set
@ -956,6 +989,7 @@ CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
 # CONFIG_NILFS2_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
@ -966,7 +1000,6 @@ CONFIG_LOCKD=m
 CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=m
 # CONFIG_SUNRPC_REGISTER_V4 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@ -1034,11 +1067,15 @@ CONFIG_FRAME_WARN=1024
 # CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_SECTION_MISMATCH=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SHIRQ=y
 CONFIG_DETECT_SOFTLOCKUP=y
 # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
 CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
 CONFIG_DETECT_HUNG_TASK=y
 # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
 CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
 CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
@ -1046,16 +1083,21 @@ CONFIG_SCHED_DEBUG=y
 # CONFIG_DEBUG_SLAB is not set
 # CONFIG_DEBUG_SPINLOCK is not set
 # CONFIG_DEBUG_MUTEXES is not set
 # CONFIG_DEBUG_LOCK_ALLOC is not set
 # CONFIG_PROVE_LOCKING is not set
 # CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
 CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_DEBUG_INFO=y
 # CONFIG_DEBUG_VM is not set
 # CONFIG_DEBUG_NOMMU_REGIONS is not set
 # CONFIG_DEBUG_WRITECOUNT is not set
 # CONFIG_DEBUG_MEMORY_INIT is not set
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
 # CONFIG_DEBUG_NOTIFIERS is not set
 # CONFIG_FRAME_POINTER is not set
 # CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
@ -1063,17 +1105,19 @@ CONFIG_DEBUG_INFO=y
 # CONFIG_BACKTRACE_SELF_TEST is not set
 # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
 # CONFIG_FAULT_INJECTION is not set
-
+# CONFIG_PAGE_POISONING is not set
-#
+CONFIG_HAVE_FUNCTION_TRACER=y
-# Tracers
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-#
+CONFIG_TRACING_SUPPORT=y
-# CONFIG_SCHED_TRACER is not set
+# CONFIG_FTRACE is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_BRANCH_PROFILE_NONE is not set
-# CONFIG_BOOT_TRACER is not set
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
 # CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_KGDB is not set
 # CONFIG_KMEMCHECK is not set
 # CONFIG_DEBUG_STACKOVERFLOW is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
 CONFIG_DEBUG_VERBOSE=y
@ -1095,16 +1139,15 @@ CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE=y
 CONFIG_EARLY_PRINTK=y
 CONFIG_CPLB_INFO=y
 CONFIG_ACCESS_CHECK=y
 # CONFIG_BFIN_ISRAM_SELF_TEST is not set
 #
 # Security options
 #
 # CONFIG_KEYS is not set
-CONFIG_SECURITY=y
+# CONFIG_SECURITY is not set
 # CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_NETWORK is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
 CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
 CONFIG_CRYPTO=y
 #
@ -1183,6 +1226,7 @@ CONFIG_CRYPTO=y
 # Compression
 #
 # CONFIG_CRYPTO_DEFLATE is not set
 # CONFIG_CRYPTO_ZLIB is not set
 # CONFIG_CRYPTO_LZO is not set
 #
@ -1190,11 +1234,13 @@ CONFIG_CRYPTO=y
 #
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRYPTO_HW=y
 # CONFIG_BINARY_PRINTF is not set
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
 CONFIG_GENERIC_FIND_LAST_BIT=y
 CONFIG_CRC_CCITT=m
 # CONFIG_CRC16 is not set
 # CONFIG_CRC_T10DIF is not set
@ -1204,6 +1250,8 @@ CONFIG_CRC32=y
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=m
 CONFIG_DECOMPRESS_GZIP=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
 CONFIG_NLATTR=y
--- a/arch/blackfin/configs/BlackStamp_defconfig
+++ b/arch/blackfin/configs/BlackStamp_defconfig
@ -66,6 +66,7 @@ CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
 CONFIG_MMAP_ALLOW_UNINITIALIZED=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
@ -275,6 +276,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
 CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 CONFIG_BFIN_GPTIMERS=y
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
--- a/arch/blackfin/configs/CM-BF527_defconfig
+++ b/arch/blackfin/configs/CM-BF527_defconfig
@ -1,12 +1,13 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.28
+# Linux kernel version: 2.6.30.5
 #
 # CONFIG_MMU is not set
 # CONFIG_FPU is not set
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
 CONFIG_BLACKFIN=y
 CONFIG_GENERIC_BUG=y
 CONFIG_ZONE_DMA=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
@ -15,6 +16,9 @@ CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_GENERIC_GPIO=y
 CONFIG_FORCE_MAX_ZONEORDER=14
 CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 #
@ -25,55 +29,72 @@ CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
 CONFIG_HAVE_KERNEL_GZIP=y
 CONFIG_HAVE_KERNEL_BZIP2=y
 CONFIG_HAVE_KERNEL_LZMA=y
 # CONFIG_KERNEL_GZIP is not set
 # CONFIG_KERNEL_BZIP2 is not set
 CONFIG_KERNEL_LZMA=y
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
 #
 # RCU Subsystem
 #
 CONFIG_CLASSIC_RCU=y
 # CONFIG_TREE_RCU is not set
 # CONFIG_PREEMPT_RCU is not set
 # CONFIG_TREE_RCU_TRACE is not set
 # CONFIG_PREEMPT_RCU_TRACE is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_CGROUPS is not set
 # CONFIG_GROUP_SCHED is not set
-CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_CGROUPS is not set
-CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
 # CONFIG_RELAY is not set
 # CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 # CONFIG_RD_GZIP is not set
 # CONFIG_RD_BZIP2 is not set
 CONFIG_RD_LZMA=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-# CONFIG_SYSCTL is not set
+CONFIG_SYSCTL=y
 CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
 CONFIG_UID16=y
 # CONFIG_SYSCTL_SYSCALL is not set
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
 # CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 # CONFIG_ELF_CORE is not set
 CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 # CONFIG_FUTEX is not set
 CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 # CONFIG_AIO is not set
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
 CONFIG_MMAP_ALLOW_UNINITIALIZED=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
 # CONFIG_SLOW_WORK is not set
 # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
 # CONFIG_MODULE_FORCE_LOAD is not set
@ -81,11 +102,8 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
@ -101,7 +119,6 @@ CONFIG_IOSCHED_CFQ=y
 CONFIG_DEFAULT_CFQ=y
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="cfq"
 CONFIG_CLASSIC_RCU=y
 # CONFIG_PREEMPT_NONE is not set
 CONFIG_PREEMPT_VOLUNTARY=y
 # CONFIG_PREEMPT is not set
@ -265,7 +282,10 @@ CONFIG_HZ=250
 # CONFIG_SCHED_HRTICK is not set
 CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 # CONFIG_TICKSOURCE_GPTMR0 is not set
 CONFIG_TICKSOURCE_CORETMR=y
 # CONFIG_CYCLES_CLOCKSOURCE is not set
 # CONFIG_GPTMR0_CLOCKSOURCE is not set
 # CONFIG_NO_HZ is not set
 # CONFIG_HIGH_RES_TIMERS is not set
 CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
@ -315,10 +335,12 @@ CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
 CONFIG_UNEVICTABLE_LRU=y
 CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 CONFIG_BFIN_GPTIMERS=y
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
@ -329,10 +351,9 @@ CONFIG_DMA_UNCACHED_1M=y
 # Cache Support
 #
 CONFIG_BFIN_ICACHE=y
-# CONFIG_BFIN_ICACHE_LOCK is not set
+CONFIG_BFIN_EXTMEM_ICACHEABLE=y
 CONFIG_BFIN_DCACHE=y
 # CONFIG_BFIN_DCACHE_BANKA is not set
 CONFIG_BFIN_EXTMEM_ICACHEABLE=y
 CONFIG_BFIN_EXTMEM_DCACHEABLE=y
 CONFIG_BFIN_EXTMEM_WRITEBACK=y
 # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
@ -343,7 +364,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y
 # CONFIG_MPU is not set
 #
-# Asynchonous Memory Configuration
+# Asynchronous Memory Configuration
 #
 #
@ -361,7 +382,7 @@ CONFIG_C_AMBEN_ALL=y
 # EBIU_AMBCTL Control
 #
 CONFIG_BANK_0=0x7BB0
-CONFIG_BANK_1=0x5554
+CONFIG_BANK_1=0x7BB0
 CONFIG_BANK_2=0x7BB0
 CONFIG_BANK_3=0xFFC0
@ -386,7 +407,6 @@ CONFIG_BINFMT_ZFLAT=y
 #
 # CONFIG_PM is not set
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
 # CONFIG_PM_WAKEUP_BY_GPIO is not set
 #
 # CPU Frequency scaling
@ -400,11 +420,6 @@ CONFIG_NET=y
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
 CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
 # CONFIG_XFRM_SUB_POLICY is not set
 # CONFIG_XFRM_MIGRATE is not set
 # CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
@ -428,7 +443,6 @@ CONFIG_IP_PNP=y
 # CONFIG_INET_XFRM_MODE_BEET is not set
 # CONFIG_INET_LRO is not set
 # CONFIG_INET_DIAG is not set
 CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
@ -452,7 +466,9 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
 # CONFIG_PHONET is not set
 # CONFIG_NET_SCHED is not set
 # CONFIG_DCB is not set
 #
 # Network testing
@ -463,13 +479,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
-# CONFIG_PHONET is not set
+# CONFIG_WIRELESS is not set
-CONFIG_WIRELESS=y
+# CONFIG_WIMAX is not set
 # CONFIG_CFG80211 is not set
 CONFIG_WIRELESS_OLD_REGULATORY=y
 # CONFIG_WIRELESS_EXT is not set
 # CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
@ -484,22 +495,21 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 # CONFIG_FW_LOADER is not set
 # CONFIG_DEBUG_DRIVER is not set
 # CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 # CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
 # CONFIG_MTD_AR7_PARTS is not set
 #
 # User Modules And Translation Layers
 #
-CONFIG_MTD_CHAR=m
+CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLKDEVS=y
 CONFIG_MTD_BLOCK=y
 # CONFIG_FTL is not set
@ -512,9 +522,9 @@ CONFIG_MTD_BLOCK=y
 #
 # RAM/ROM/Flash chip drivers
 #
-# CONFIG_MTD_CFI is not set
+CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=m
+# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_GEN_PROBE=m
+CONFIG_MTD_GEN_PROBE=y
 # CONFIG_MTD_CFI_ADV_OPTIONS is not set
 CONFIG_MTD_MAP_BANK_WIDTH_1=y
 CONFIG_MTD_MAP_BANK_WIDTH_2=y
@ -526,9 +536,11 @@ CONFIG_MTD_CFI_I1=y
 CONFIG_MTD_CFI_I2=y
 # CONFIG_MTD_CFI_I4 is not set
 # CONFIG_MTD_CFI_I8 is not set
-# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_INTELEXT=y
 # CONFIG_MTD_CFI_AMDSTD is not set
 # CONFIG_MTD_CFI_STAA is not set
 # CONFIG_MTD_PSD4256G is not set
 CONFIG_MTD_CFI_UTIL=y
 CONFIG_MTD_RAM=y
 CONFIG_MTD_ROM=m
 # CONFIG_MTD_ABSENT is not set
@ -538,7 +550,7 @@ CONFIG_MTD_ROM=m
 #
 CONFIG_MTD_COMPLEX_MAPPINGS=y
 # CONFIG_MTD_PHYSMAP is not set
-# CONFIG_MTD_GPIO_ADDR is not set
+CONFIG_MTD_GPIO_ADDR=y
 # CONFIG_MTD_UCLINUX is not set
 # CONFIG_MTD_PLATRAM is not set
@ -561,6 +573,11 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y
 # CONFIG_MTD_NAND is not set
 # CONFIG_MTD_ONENAND is not set
 #
 # LPDDR flash memory drivers
 #
 # CONFIG_MTD_LPDDR is not set
 #
 # UBI - Unsorted block images
 #
@ -586,12 +603,46 @@ CONFIG_HAVE_IDE=y
 # SCSI device support
 #
 # CONFIG_RAID_ATTRS is not set
-# CONFIG_SCSI is not set
+CONFIG_SCSI=y
-# CONFIG_SCSI_DMA is not set
+CONFIG_SCSI_DMA=y
 # CONFIG_SCSI_TGT is not set
 # CONFIG_SCSI_NETLINK is not set
 CONFIG_SCSI_PROC_FS=y
 #
 # SCSI support type (disk, tape, CD-ROM)
 #
 CONFIG_BLK_DEV_SD=y
 # CONFIG_CHR_DEV_ST is not set
 # CONFIG_CHR_DEV_OSST is not set
 # CONFIG_BLK_DEV_SR is not set
 # CONFIG_CHR_DEV_SG is not set
 # CONFIG_CHR_DEV_SCH is not set
 #
 # Some SCSI devices (e.g. CD jukebox) support multiple LUNs
 #
 # CONFIG_SCSI_MULTI_LUN is not set
 # CONFIG_SCSI_CONSTANTS is not set
 # CONFIG_SCSI_LOGGING is not set
 # CONFIG_SCSI_SCAN_ASYNC is not set
 CONFIG_SCSI_WAIT_SCAN=m
 #
 # SCSI Transports
 #
 # CONFIG_SCSI_SPI_ATTRS is not set
 # CONFIG_SCSI_FC_ATTRS is not set
 # CONFIG_SCSI_ISCSI_ATTRS is not set
 # CONFIG_SCSI_SAS_LIBSAS is not set
 # CONFIG_SCSI_SRP_ATTRS is not set
 # CONFIG_SCSI_LOWLEVEL is not set
 # CONFIG_SCSI_DH is not set
 # CONFIG_SCSI_OSD_INITIATOR is not set
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
 CONFIG_COMPAT_NET_DEV_OPS=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@ -613,6 +664,9 @@ CONFIG_PHYLIB=y
 # CONFIG_BROADCOM_PHY is not set
 # CONFIG_ICPLUS_PHY is not set
 # CONFIG_REALTEK_PHY is not set
 # CONFIG_NATIONAL_PHY is not set
 # CONFIG_STE10XP is not set
 # CONFIG_LSI_ET1011C_PHY is not set
 # CONFIG_FIXED_PHY is not set
 # CONFIG_MDIO_BITBANG is not set
 CONFIG_NET_ETHERNET=y
@ -623,9 +677,11 @@ CONFIG_BFIN_TX_DESC_NUM=10
 CONFIG_BFIN_RX_DESC_NUM=20
 CONFIG_BFIN_MAC_RMII=y
 # CONFIG_SMC91X is not set
 # CONFIG_SMSC911X is not set
 # CONFIG_DM9000 is not set
 # CONFIG_ENC28J60 is not set
 # CONFIG_ETHOC is not set
 # CONFIG_SMSC911X is not set
 # CONFIG_DNET is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
 # CONFIG_IBM_NEW_EMAC_TAH is not set
@ -633,6 +689,7 @@ CONFIG_BFIN_MAC_RMII=y
 # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
 # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
 # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 # CONFIG_B44 is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
@ -641,7 +698,10 @@ CONFIG_BFIN_MAC_RMII=y
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
-# CONFIG_IWLWIFI_LEDS is not set
+
 #
 # Enable WiMAX (Networking options) to see the WiMAX drivers
 #
 #
 # USB Network Adapters
@ -674,17 +734,13 @@ CONFIG_BFIN_MAC_RMII=y
 #
 # Character devices
 #
 # CONFIG_AD9960 is not set
 # CONFIG_SPI_ADC_BF533 is not set
 # CONFIG_BF5xx_PPIFCD is not set
 # CONFIG_BFIN_SIMPLE_TIMER is not set
 # CONFIG_BF5xx_PPI is not set
 # CONFIG_BF5xx_EPPI is not set
 # CONFIG_BFIN_SPORT is not set
 # CONFIG_BFIN_TIMER_LATENCY is not set
 # CONFIG_TWI_LCD is not set
 CONFIG_BFIN_DMA_INTERFACE=m
-CONFIG_SIMPLE_GPIO=m
+# CONFIG_BFIN_PPI is not set
 # CONFIG_BFIN_PPIFCD is not set
 # CONFIG_BFIN_SIMPLE_TIMER is not set
 # CONFIG_BFIN_SPI_ADC is not set
 # CONFIG_BFIN_SPORT is not set
 # CONFIG_BFIN_TWI_LCD is not set
 # CONFIG_VT is not set
 # CONFIG_DEVKMEM is not set
 # CONFIG_BFIN_JTAG_COMM is not set
@ -698,6 +754,7 @@ CONFIG_SIMPLE_GPIO=m
 #
 # Non-8250 serial port support
 #
 # CONFIG_SERIAL_MAX3100 is not set
 CONFIG_SERIAL_BFIN=y
 CONFIG_SERIAL_BFIN_CONSOLE=y
 CONFIG_SERIAL_BFIN_DMA=y
@ -710,6 +767,7 @@ CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_SERIAL_BFIN_SPORT is not set
 CONFIG_UNIX98_PTYS=y
 # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 # CONFIG_LEGACY_PTYS is not set
 CONFIG_BFIN_OTP=y
 # CONFIG_BFIN_OTP_WRITE_ENABLE is not set
@ -758,13 +816,9 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
 # Miscellaneous I2C Chip support
 #
 # CONFIG_DS1682 is not set
 # CONFIG_AT24 is not set
 # CONFIG_SENSORS_AD5252 is not set
 # CONFIG_SENSORS_EEPROM is not set
 # CONFIG_SENSORS_PCF8574 is not set
 # CONFIG_PCF8575 is not set
 # CONFIG_SENSORS_PCA9539 is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
@ -772,7 +826,6 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
 # CONFIG_I2C_DEBUG_BUS is not set
 # CONFIG_I2C_DEBUG_CHIP is not set
 CONFIG_SPI=y
 # CONFIG_SPI_DEBUG is not set
 CONFIG_SPI_MASTER=y
 #
@ -780,17 +833,17 @@ CONFIG_SPI_MASTER=y
 #
 CONFIG_SPI_BFIN=y
 # CONFIG_SPI_BFIN_LOCK is not set
 # CONFIG_SPI_BFIN_SPORT is not set
 # CONFIG_SPI_BITBANG is not set
 # CONFIG_SPI_GPIO is not set
 #
 # SPI Protocol Masters
 #
 # CONFIG_SPI_AT25 is not set
 # CONFIG_SPI_SPIDEV is not set
 # CONFIG_SPI_TLE62X0 is not set
 CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
 CONFIG_GPIOLIB=y
 # CONFIG_DEBUG_GPIO is not set
 CONFIG_GPIO_SYSFS=y
 #
@ -803,6 +856,7 @@ CONFIG_GPIO_SYSFS=y
 # CONFIG_GPIO_MAX732X is not set
 # CONFIG_GPIO_PCA953X is not set
 # CONFIG_GPIO_PCF857X is not set
 # CONFIG_GPIO_ADP5588 is not set
 #
 # PCI GPIO expanders:
@ -829,11 +883,13 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_ADT7462 is not set
 # CONFIG_SENSORS_ADT7470 is not set
 # CONFIG_SENSORS_ADT7473 is not set
 # CONFIG_SENSORS_ADT7475 is not set
 # CONFIG_SENSORS_ATXP1 is not set
 # CONFIG_SENSORS_DS1621 is not set
 # CONFIG_SENSORS_F71805F is not set
 # CONFIG_SENSORS_F71882FG is not set
 # CONFIG_SENSORS_F75375S is not set
 # CONFIG_SENSORS_G760A is not set
 # CONFIG_SENSORS_GL518SM is not set
 # CONFIG_SENSORS_GL520SM is not set
 # CONFIG_SENSORS_IT87 is not set
@ -849,11 +905,16 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_LM90 is not set
 # CONFIG_SENSORS_LM92 is not set
 # CONFIG_SENSORS_LM93 is not set
 # CONFIG_SENSORS_LTC4215 is not set
 # CONFIG_SENSORS_LTC4245 is not set
 # CONFIG_SENSORS_LM95241 is not set
 # CONFIG_SENSORS_MAX1111 is not set
 # CONFIG_SENSORS_MAX1619 is not set
 # CONFIG_SENSORS_MAX6650 is not set
 # CONFIG_SENSORS_PC87360 is not set
 # CONFIG_SENSORS_PC87427 is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_SENSORS_SHT15 is not set
 # CONFIG_SENSORS_DME1737 is not set
 # CONFIG_SENSORS_SMSC47M1 is not set
 # CONFIG_SENSORS_SMSC47M192 is not set
@ -885,6 +946,12 @@ CONFIG_BFIN_WDT=y
 # USB-based Watchdog Cards
 #
 # CONFIG_USBPCWATCHDOG is not set
 CONFIG_SSB_POSSIBLE=y
 #
 # Sonics Silicon Backplane
 #
 # CONFIG_SSB is not set
 #
 # Multifunction device drivers
@ -892,10 +959,14 @@ CONFIG_BFIN_WDT=y
 # CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
 # CONFIG_TPS65010 is not set
 # CONFIG_TWL4030_CORE is not set
 # CONFIG_MFD_TMIO is not set
 # CONFIG_PMIC_DA903X is not set
 # CONFIG_PMIC_ADP5520 is not set
 # CONFIG_MFD_WM8400 is not set
 # CONFIG_MFD_WM8350_I2C is not set
 # CONFIG_MFD_PCF50633 is not set
 # CONFIG_REGULATOR is not set
 #
@ -931,20 +1002,20 @@ CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 # CONFIG_USB_ARCH_HAS_OHCI is not set
 # CONFIG_USB_ARCH_HAS_EHCI is not set
-CONFIG_USB=y
+CONFIG_USB=m
 # CONFIG_USB_DEBUG is not set
-# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 #
 # Miscellaneous USB options
 #
-# CONFIG_USB_DEVICEFS is not set
+CONFIG_USB_DEVICEFS=y
-CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DEVICE_CLASS is not set
 # CONFIG_USB_DYNAMIC_MINORS is not set
 # CONFIG_USB_OTG is not set
 # CONFIG_USB_OTG_WHITELIST is not set
 CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_MON=y
+CONFIG_USB_MON=m
 # CONFIG_USB_WUSB is not set
 # CONFIG_USB_WUSB_CBAF is not set
@ -952,24 +1023,24 @@ CONFIG_USB_MON=y
 # USB Host Controller Drivers
 #
 # CONFIG_USB_C67X00_HCD is not set
 # CONFIG_USB_OXU210HP_HCD is not set
 # CONFIG_USB_ISP116X_HCD is not set
 # CONFIG_USB_ISP1760_HCD is not set
 # CONFIG_USB_ISP1362_HCD is not set
 # CONFIG_USB_SL811_HCD is not set
 # CONFIG_USB_R8A66597_HCD is not set
 # CONFIG_USB_HWA_HCD is not set
-CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_HDRC=m
 CONFIG_USB_MUSB_SOC=y
 #
 # Blackfin high speed USB Support
 #
-CONFIG_USB_MUSB_HOST=y
+# CONFIG_USB_MUSB_HOST is not set
-# CONFIG_USB_MUSB_PERIPHERAL is not set
+CONFIG_USB_MUSB_PERIPHERAL=y
 # CONFIG_USB_MUSB_OTG is not set
-CONFIG_USB_MUSB_HDRC_HCD=y
+CONFIG_USB_GADGET_MUSB_HDRC=y
 CONFIG_MUSB_PIO_ONLY=y
 CONFIG_MUSB_DMA_POLL=y
 # CONFIG_USB_MUSB_DEBUG is not set
 #
@ -981,18 +1052,31 @@ CONFIG_MUSB_DMA_POLL=y
 # CONFIG_USB_TMC is not set
 #
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
 #
 #
-# see USB_STORAGE Help for more information
+# also be needed; see USB_STORAGE Help for more info
 #
 CONFIG_USB_STORAGE=m
 # CONFIG_USB_STORAGE_DEBUG is not set
 # CONFIG_USB_STORAGE_DATAFAB is not set
 # CONFIG_USB_STORAGE_FREECOM is not set
 # CONFIG_USB_STORAGE_ISD200 is not set
 # CONFIG_USB_STORAGE_USBAT is not set
 # CONFIG_USB_STORAGE_SDDR09 is not set
 # CONFIG_USB_STORAGE_SDDR55 is not set
 # CONFIG_USB_STORAGE_JUMPSHOT is not set
 # CONFIG_USB_STORAGE_ALAUDA is not set
 # CONFIG_USB_STORAGE_KARMA is not set
 # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
 # CONFIG_USB_LIBUSUAL is not set
 #
 # USB Imaging devices
 #
 # CONFIG_USB_MDC800 is not set
 # CONFIG_USB_MICROTEK is not set
 #
 # USB port drivers
@ -1013,7 +1097,6 @@ CONFIG_MUSB_DMA_POLL=y
 # CONFIG_USB_LED is not set
 # CONFIG_USB_CYPRESS_CY7C63 is not set
 # CONFIG_USB_CYTHERM is not set
 # CONFIG_USB_PHIDGET is not set
 # CONFIG_USB_IDMOUSE is not set
 # CONFIG_USB_FTDI_ELAN is not set
 # CONFIG_USB_APPLEDISPLAY is not set
@ -1021,9 +1104,50 @@ CONFIG_MUSB_DMA_POLL=y
 # CONFIG_USB_LD is not set
 # CONFIG_USB_TRANCEVIBRATOR is not set
 # CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_TEST is not set
 # CONFIG_USB_ISIGHTFW is not set
 # CONFIG_USB_VST is not set
-# CONFIG_USB_GADGET is not set
+CONFIG_USB_GADGET=m
 # CONFIG_USB_GADGET_DEBUG_FILES is not set
 # CONFIG_USB_GADGET_DEBUG_FS is not set
 CONFIG_USB_GADGET_VBUS_DRAW=2
 CONFIG_USB_GADGET_SELECTED=y
 # CONFIG_USB_GADGET_AT91 is not set
 # CONFIG_USB_GADGET_ATMEL_USBA is not set
 # CONFIG_USB_GADGET_FSL_USB2 is not set
 # CONFIG_USB_GADGET_LH7A40X is not set
 # CONFIG_USB_GADGET_OMAP is not set
 # CONFIG_USB_GADGET_PXA25X is not set
 # CONFIG_USB_GADGET_PXA27X is not set
 # CONFIG_USB_GADGET_S3C2410 is not set
 # CONFIG_USB_GADGET_IMX is not set
 # CONFIG_USB_GADGET_M66592 is not set
 # CONFIG_USB_GADGET_AMD5536UDC is not set
 # CONFIG_USB_GADGET_FSL_QE is not set
 # CONFIG_USB_GADGET_CI13XXX is not set
 # CONFIG_USB_GADGET_NET2272 is not set
 # CONFIG_USB_GADGET_NET2280 is not set
 # CONFIG_USB_GADGET_GOKU is not set
 # CONFIG_USB_GADGET_DUMMY_HCD is not set
 CONFIG_USB_GADGET_DUALSPEED=y
 # CONFIG_USB_ZERO is not set
 # CONFIG_USB_AUDIO is not set
 CONFIG_USB_ETH=m
 CONFIG_USB_ETH_RNDIS=y
 # CONFIG_USB_GADGETFS is not set
 CONFIG_USB_FILE_STORAGE=m
 # CONFIG_USB_FILE_STORAGE_TEST is not set
 CONFIG_USB_G_SERIAL=m
 # CONFIG_USB_MIDI_GADGET is not set
 CONFIG_USB_G_PRINTER=m
 # CONFIG_USB_CDC_COMPOSITE is not set
 #
 # OTG and related infrastructure
 #
 CONFIG_USB_OTG_UTILS=y
 # CONFIG_USB_GPIO_VBUS is not set
 # CONFIG_NOP_USB_XCEIV is not set
 # CONFIG_MMC is not set
 # CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
@ -1090,6 +1214,7 @@ CONFIG_RTC_INTF_DEV=y
 #
 CONFIG_RTC_DRV_BFIN=y
 # CONFIG_DMADEVICES is not set
 # CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
 # CONFIG_STAGING is not set
@ -1102,9 +1227,10 @@ CONFIG_RTC_DRV_BFIN=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
 # CONFIG_OCFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
 CONFIG_FILE_LOCKING=y
 # CONFIG_DNOTIFY is not set
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@ -1113,6 +1239,11 @@ CONFIG_INOTIFY_USER=y
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
 #
 # Caches
 #
 # CONFIG_FSCACHE is not set
 #
 # CD-ROM/DVD Filesystems
 #
@ -1122,8 +1253,11 @@ CONFIG_INOTIFY_USER=y
 #
 # DOS/FAT/NT Filesystems
 #
-# CONFIG_MSDOS_FS is not set
+CONFIG_FAT_FS=y
-# CONFIG_VFAT_FS is not set
+CONFIG_MSDOS_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_FAT_DEFAULT_CODEPAGE=437
 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 # CONFIG_NTFS_FS is not set
 #
@ -1135,10 +1269,7 @@ CONFIG_SYSFS=y
 # CONFIG_TMPFS is not set
 # CONFIG_HUGETLB_PAGE is not set
 # CONFIG_CONFIGFS_FS is not set
-
+CONFIG_MISC_FILESYSTEMS=y
 #
 # Miscellaneous filesystems
 #
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
@ -1146,9 +1277,19 @@ CONFIG_SYSFS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-# CONFIG_YAFFS_FS is not set
+CONFIG_JFFS2_FS=y
-# CONFIG_JFFS2_FS is not set
+CONFIG_JFFS2_FS_DEBUG=0
 CONFIG_JFFS2_FS_WRITEBUFFER=y
 # CONFIG_JFFS2_FS_WBUF_VERIFY is not set
 # CONFIG_JFFS2_SUMMARY is not set
 # CONFIG_JFFS2_FS_XATTR is not set
 # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
 CONFIG_JFFS2_ZLIB=y
 # CONFIG_JFFS2_LZO is not set
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_OMFS_FS is not set
@ -1157,6 +1298,7 @@ CONFIG_SYSFS=y
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
 # CONFIG_NILFS2_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
@ -1167,7 +1309,6 @@ CONFIG_LOCKD=m
 CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=m
 # CONFIG_SUNRPC_REGISTER_V4 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@ -1182,9 +1323,9 @@ CONFIG_SMB_FS=m
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-CONFIG_NLS=m
+CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
-# CONFIG_NLS_CODEPAGE_437 is not set
+CONFIG_NLS_CODEPAGE_437=y
 # CONFIG_NLS_CODEPAGE_737 is not set
 # CONFIG_NLS_CODEPAGE_775 is not set
 # CONFIG_NLS_CODEPAGE_850 is not set
@ -1208,7 +1349,7 @@ CONFIG_NLS_DEFAULT="iso8859-1"
 # CONFIG_NLS_CODEPAGE_1250 is not set
 # CONFIG_NLS_CODEPAGE_1251 is not set
 # CONFIG_NLS_ASCII is not set
-# CONFIG_NLS_ISO8859_1 is not set
+CONFIG_NLS_ISO8859_1=y
 # CONFIG_NLS_ISO8859_2 is not set
 # CONFIG_NLS_ISO8859_3 is not set
 # CONFIG_NLS_ISO8859_4 is not set
@ -1235,55 +1376,34 @@ CONFIG_FRAME_WARN=1024
 # CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_SECTION_MISMATCH=y
-# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DEBUG_KERNEL is not set
-CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
 # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
 CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
 # CONFIG_DEBUG_OBJECTS is not set
 # CONFIG_DEBUG_SLAB is not set
 # CONFIG_DEBUG_RT_MUTEXES is not set
 # CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
 # CONFIG_DEBUG_MUTEXES is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
 CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_INFO is not set
 # CONFIG_DEBUG_VM is not set
 # CONFIG_DEBUG_WRITECOUNT is not set
 # CONFIG_DEBUG_MEMORY_INIT is not set
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
 # CONFIG_FRAME_POINTER is not set
 # CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_BACKTRACE_SELF_TEST is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-# CONFIG_FAULT_INJECTION is not set
+CONFIG_TRACING_SUPPORT=y
 # CONFIG_SYSCTL_SYSCALL_CHECK is not set
 #
 # Tracers
 #
 # CONFIG_FUNCTION_TRACER is not set
 # CONFIG_IRQSOFF_TRACER is not set
 # CONFIG_SCHED_TRACER is not set
 # CONFIG_CONTEXT_SWITCH_TRACER is not set
 # CONFIG_EVENT_TRACER is not set
 # CONFIG_BOOT_TRACER is not set
-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
 # CONFIG_STACK_TRACER is not set
 # CONFIG_KMEMTRACE is not set
 # CONFIG_WORKQUEUE_TRACER is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_KGDB is not set
 # CONFIG_DEBUG_STACKOVERFLOW is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
 # CONFIG_KGDB_TESTCASE is not set
 CONFIG_DEBUG_VERBOSE=y
-CONFIG_DEBUG_MMRS=y
+# CONFIG_DEBUG_MMRS is not set
 # CONFIG_DEBUG_HWERR is not set
 # CONFIG_DEBUG_DOUBLEFAULT is not set
 CONFIG_DEBUG_HUNT_FOR_ZERO=y
 CONFIG_DEBUG_BFIN_HWTRACE_ON=y
@ -1293,9 +1413,10 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
 CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
 # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
 # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-# CONFIG_EARLY_PRINTK is not set
+CONFIG_EARLY_PRINTK=y
 # CONFIG_CPLB_INFO is not set
 CONFIG_ACCESS_CHECK=y
 # CONFIG_BFIN_ISRAM_SELF_TEST is not set
 #
 # Security options
@ -1304,9 +1425,9 @@ CONFIG_ACCESS_CHECK=y
 CONFIG_SECURITY=y
 # CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_NETWORK is not set
 # CONFIG_SECURITY_PATH is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
-# CONFIG_SECURITY_ROOTPLUG is not set
+# CONFIG_SECURITY_TOMOYO is not set
 CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
 CONFIG_CRYPTO=y
 #
@ -1385,6 +1506,7 @@ CONFIG_CRYPTO=y
 # Compression
 #
 # CONFIG_CRYPTO_DEFLATE is not set
 # CONFIG_CRYPTO_ZLIB is not set
 # CONFIG_CRYPTO_LZO is not set
 #
@ -1392,20 +1514,24 @@ CONFIG_CRYPTO=y
 #
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRYPTO_HW=y
 # CONFIG_BINARY_PRINTF is not set
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
 CONFIG_GENERIC_FIND_LAST_BIT=y
 CONFIG_CRC_CCITT=m
 # CONFIG_CRC16 is not set
 # CONFIG_CRC_T10DIF is not set
-# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC_ITU_T=y
 CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
+CONFIG_CRC7=y
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
-CONFIG_PLIST=y
+CONFIG_ZLIB_DEFLATE=y
 CONFIG_DECOMPRESS_LZMA=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
 CONFIG_NLATTR=y
--- a/arch/blackfin/configs/CM-BF533_defconfig
+++ b/arch/blackfin/configs/CM-BF533_defconfig
--- a/arch/blackfin/configs/CM-BF537E_defconfig
+++ b/arch/blackfin/configs/CM-BF537E_defconfig
@ -1,13 +1,13 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.28.10
+# Linux kernel version: 2.6.30.5
 # Wed Jun  3 06:27:41 2009
 #
 # CONFIG_MMU is not set
 # CONFIG_FPU is not set
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
 CONFIG_BLACKFIN=y
 CONFIG_GENERIC_BUG=y
 CONFIG_ZONE_DMA=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
@ -16,6 +16,9 @@ CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_GENERIC_GPIO=y
 CONFIG_FORCE_MAX_ZONEORDER=14
 CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 #
@ -26,21 +29,40 @@ CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
 CONFIG_HAVE_KERNEL_GZIP=y
 CONFIG_HAVE_KERNEL_BZIP2=y
 CONFIG_HAVE_KERNEL_LZMA=y
 # CONFIG_KERNEL_GZIP is not set
 # CONFIG_KERNEL_BZIP2 is not set
 CONFIG_KERNEL_LZMA=y
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
 #
 # RCU Subsystem
 #
 CONFIG_CLASSIC_RCU=y
 # CONFIG_TREE_RCU is not set
 # CONFIG_PREEMPT_RCU is not set
 # CONFIG_TREE_RCU_TRACE is not set
 # CONFIG_PREEMPT_RCU_TRACE is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_CGROUPS is not set
 # CONFIG_GROUP_SCHED is not set
 # CONFIG_CGROUPS is not set
 # CONFIG_SYSFS_DEPRECATED_V2 is not set
 # CONFIG_RELAY is not set
 # CONFIG_NAMESPACES is not set
-# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 # CONFIG_RD_GZIP is not set
 # CONFIG_RD_BZIP2 is not set
 CONFIG_RD_LZMA=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SYSCTL=y
 CONFIG_ANON_INODES=y
@ -49,7 +71,8 @@ CONFIG_EMBEDDED=y
 # CONFIG_SYSCTL_SYSCALL is not set
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
-# CONFIG_HOTPLUG is not set
+# CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 # CONFIG_ELF_CORE is not set
@ -65,12 +88,13 @@ CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
 CONFIG_MMAP_ALLOW_UNINITIALIZED=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
 # CONFIG_SLOW_WORK is not set
 # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
 # CONFIG_MODULE_FORCE_LOAD is not set
@ -78,11 +102,8 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
@ -98,7 +119,6 @@ CONFIG_IOSCHED_CFQ=y
 # CONFIG_DEFAULT_CFQ is not set
 CONFIG_DEFAULT_NOOP=y
 CONFIG_DEFAULT_IOSCHED="noop"
 CONFIG_CLASSIC_RCU=y
 CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
@ -181,7 +201,8 @@ CONFIG_IRQ_MEM_DMA1=13
 CONFIG_IRQ_WATCH=13
 CONFIG_IRQ_SPI=10
 # CONFIG_BFIN537_STAMP is not set
-CONFIG_BFIN537_BLUETECHNIX_CM=y
+CONFIG_BFIN537_BLUETECHNIX_CM_E=y
 # CONFIG_BFIN537_BLUETECHNIX_CM_U is not set
 # CONFIG_BFIN537_BLUETECHNIX_TCM is not set
 # CONFIG_PNAV10 is not set
 # CONFIG_CAMSIG_MINOTAUR is not set
@ -283,10 +304,12 @@ CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
 CONFIG_UNEVICTABLE_LRU=y
 CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 # CONFIG_BFIN_GPTIMERS is not set
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
@ -297,10 +320,9 @@ CONFIG_DMA_UNCACHED_1M=y
 # Cache Support
 #
 CONFIG_BFIN_ICACHE=y
-# CONFIG_BFIN_ICACHE_LOCK is not set
+CONFIG_BFIN_EXTMEM_ICACHEABLE=y
 CONFIG_BFIN_DCACHE=y
 # CONFIG_BFIN_DCACHE_BANKA is not set
 CONFIG_BFIN_EXTMEM_ICACHEABLE=y
 CONFIG_BFIN_EXTMEM_DCACHEABLE=y
 CONFIG_BFIN_EXTMEM_WRITEBACK=y
 # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
@ -311,7 +333,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y
 # CONFIG_MPU is not set
 #
-# Asynchonous Memory Configuration
+# Asynchronous Memory Configuration
 #
 #
@ -337,6 +359,7 @@ CONFIG_BANK_3=0xFFC2
 # Bus options (PCI, PCMCIA, EISA, MCA, ISA)
 #
 # CONFIG_ARCH_SUPPORTS_MSI is not set
 # CONFIG_PCCARD is not set
 #
 # Executable file formats
@ -366,11 +389,6 @@ CONFIG_NET=y
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
 CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
 # CONFIG_XFRM_SUB_POLICY is not set
 # CONFIG_XFRM_MIGRATE is not set
 # CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
@ -394,7 +412,6 @@ CONFIG_IP_PNP=y
 # CONFIG_INET_XFRM_MODE_BEET is not set
 # CONFIG_INET_LRO is not set
 # CONFIG_INET_DIAG is not set
 CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
@ -418,7 +435,9 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
 # CONFIG_PHONET is not set
 # CONFIG_NET_SCHED is not set
 # CONFIG_DCB is not set
 #
 # Network testing
@ -429,8 +448,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
 # CONFIG_PHONET is not set
 # CONFIG_WIRELESS is not set
 # CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
@ -441,16 +460,21 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # Generic Driver Options
 #
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=y
 CONFIG_FIRMWARE_IN_KERNEL=y
 CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_SYS_HYPERVISOR is not set
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 # CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
 # CONFIG_MTD_AR7_PARTS is not set
 #
@ -486,22 +510,26 @@ CONFIG_MTD_CFI_I2=y
 CONFIG_MTD_CFI_INTELEXT=y
 # CONFIG_MTD_CFI_AMDSTD is not set
 # CONFIG_MTD_CFI_STAA is not set
 # CONFIG_MTD_PSD4256G is not set
 CONFIG_MTD_CFI_UTIL=y
 CONFIG_MTD_RAM=y
-# CONFIG_MTD_ROM is not set
+CONFIG_MTD_ROM=m
 # CONFIG_MTD_ABSENT is not set
 #
 # Mapping drivers for chip access
 #
 CONFIG_MTD_COMPLEX_MAPPINGS=y
 # CONFIG_MTD_PHYSMAP is not set
 CONFIG_MTD_GPIO_ADDR=y
-CONFIG_MTD_UCLINUX=y
+# CONFIG_MTD_UCLINUX is not set
 # CONFIG_MTD_PLATRAM is not set
 #
 # Self-contained MTD device drivers
 #
 # CONFIG_MTD_DATAFLASH is not set
 # CONFIG_MTD_M25P80 is not set
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
@ -516,6 +544,11 @@ CONFIG_MTD_UCLINUX=y
 # CONFIG_MTD_NAND is not set
 # CONFIG_MTD_ONENAND is not set
 #
 # LPDDR flash memory drivers
 #
 # CONFIG_MTD_LPDDR is not set
 #
 # UBI - Unsorted block images
 #
@ -533,9 +566,14 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
 # CONFIG_ATA_OVER_ETH is not set
 # CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_93CX6 is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
 # CONFIG_C2PORT is not set
 #
 # EEPROM support
 #
 # CONFIG_EEPROM_AT25 is not set
 # CONFIG_EEPROM_93CX6 is not set
 CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
@ -549,6 +587,7 @@ CONFIG_HAVE_IDE=y
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
 CONFIG_COMPAT_NET_DEV_OPS=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@ -570,6 +609,9 @@ CONFIG_PHYLIB=y
 # CONFIG_BROADCOM_PHY is not set
 # CONFIG_ICPLUS_PHY is not set
 # CONFIG_REALTEK_PHY is not set
 # CONFIG_NATIONAL_PHY is not set
 # CONFIG_STE10XP is not set
 # CONFIG_LSI_ET1011C_PHY is not set
 # CONFIG_FIXED_PHY is not set
 # CONFIG_MDIO_BITBANG is not set
 CONFIG_NET_ETHERNET=y
@ -580,8 +622,11 @@ CONFIG_BFIN_TX_DESC_NUM=10
 CONFIG_BFIN_RX_DESC_NUM=20
 # CONFIG_BFIN_MAC_RMII is not set
 # CONFIG_SMC91X is not set
 # CONFIG_SMSC911X is not set
 # CONFIG_DM9000 is not set
 # CONFIG_ENC28J60 is not set
 # CONFIG_ETHOC is not set
 # CONFIG_SMSC911X is not set
 # CONFIG_DNET is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
 # CONFIG_IBM_NEW_EMAC_TAH is not set
@ -598,7 +643,10 @@ CONFIG_BFIN_RX_DESC_NUM=20
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
-# CONFIG_IWLWIFI_LEDS is not set
+
 #
 # Enable WiMAX (Networking options) to see the WiMAX drivers
 #
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
@ -622,15 +670,12 @@ CONFIG_BFIN_RX_DESC_NUM=20
 #
 # Character devices
 #
 # CONFIG_AD9960 is not set
 CONFIG_BFIN_DMA_INTERFACE=m
 # CONFIG_BFIN_PPI is not set
 # CONFIG_BFIN_PPIFCD is not set
 # CONFIG_BFIN_SIMPLE_TIMER is not set
 # CONFIG_BFIN_SPI_ADC is not set
 CONFIG_BFIN_SPORT=y
 # CONFIG_BFIN_TIMER_LATENCY is not set
 # CONFIG_SIMPLE_GPIO is not set
 # CONFIG_VT is not set
 # CONFIG_DEVKMEM is not set
 # CONFIG_BFIN_JTAG_COMM is not set
@ -644,6 +689,7 @@ CONFIG_BFIN_SPORT=y
 #
 # Non-8250 serial port support
 #
 # CONFIG_SERIAL_MAX3100 is not set
 CONFIG_SERIAL_BFIN=y
 CONFIG_SERIAL_BFIN_CONSOLE=y
 CONFIG_SERIAL_BFIN_DMA=y
@ -656,6 +702,7 @@ CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_SERIAL_BFIN_SPORT is not set
 CONFIG_UNIX98_PTYS=y
 # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 # CONFIG_LEGACY_PTYS is not set
 #
@ -668,7 +715,23 @@ CONFIG_UNIX98_PTYS=y
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
 # CONFIG_I2C is not set
-# CONFIG_SPI is not set
+CONFIG_SPI=y
 CONFIG_SPI_MASTER=y
 #
 # SPI Master Controller Drivers
 #
 CONFIG_SPI_BFIN=y
 # CONFIG_SPI_BFIN_LOCK is not set
 # CONFIG_SPI_BFIN_SPORT is not set
 # CONFIG_SPI_BITBANG is not set
 # CONFIG_SPI_GPIO is not set
 #
 # SPI Protocol Masters
 #
 # CONFIG_SPI_SPIDEV is not set
 # CONFIG_SPI_TLE62X0 is not set
 CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
@ -688,15 +751,21 @@ CONFIG_GPIO_SYSFS=y
 #
 # SPI GPIO expanders:
 #
 # CONFIG_GPIO_MAX7301 is not set
 # CONFIG_GPIO_MCP23S08 is not set
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 CONFIG_HWMON=y
 # CONFIG_HWMON_VID is not set
 # CONFIG_SENSORS_ADCXX is not set
 # CONFIG_SENSORS_F71805F is not set
 # CONFIG_SENSORS_F71882FG is not set
 # CONFIG_SENSORS_IT87 is not set
 # CONFIG_SENSORS_LM70 is not set
 # CONFIG_SENSORS_MAX1111 is not set
 # CONFIG_SENSORS_PC87360 is not set
 # CONFIG_SENSORS_PC87427 is not set
 # CONFIG_SENSORS_SHT15 is not set
 # CONFIG_SENSORS_SMSC47M1 is not set
 # CONFIG_SENSORS_SMSC47B397 is not set
 # CONFIG_SENSORS_VT1211 is not set
@ -758,21 +827,74 @@ CONFIG_USB_ARCH_HAS_HCD=y
 # CONFIG_USB is not set
 # CONFIG_USB_OTG_WHITELIST is not set
 # CONFIG_USB_OTG_BLACKLIST_HUB is not set
 # CONFIG_USB_GADGET_MUSB_HDRC is not set
 #
-# Enable Host or Gadget support to see Inventra options
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
 #
 CONFIG_USB_GADGET=m
 # CONFIG_USB_GADGET_DEBUG_FILES is not set
 # CONFIG_USB_GADGET_DEBUG_FS is not set
 CONFIG_USB_GADGET_VBUS_DRAW=2
 CONFIG_USB_GADGET_SELECTED=y
 # CONFIG_USB_GADGET_AT91 is not set
 # CONFIG_USB_GADGET_ATMEL_USBA is not set
 # CONFIG_USB_GADGET_FSL_USB2 is not set
 # CONFIG_USB_GADGET_LH7A40X is not set
 # CONFIG_USB_GADGET_OMAP is not set
 # CONFIG_USB_GADGET_PXA25X is not set
 # CONFIG_USB_GADGET_PXA27X is not set
 # CONFIG_USB_GADGET_S3C2410 is not set
 # CONFIG_USB_GADGET_IMX is not set
 # CONFIG_USB_GADGET_M66592 is not set
 # CONFIG_USB_GADGET_AMD5536UDC is not set
 # CONFIG_USB_GADGET_FSL_QE is not set
 # CONFIG_USB_GADGET_CI13XXX is not set
 CONFIG_USB_GADGET_NET2272=y
 CONFIG_USB_NET2272=m
 # CONFIG_USB_GADGET_NET2280 is not set
 # CONFIG_USB_GADGET_GOKU is not set
 # CONFIG_USB_GADGET_DUMMY_HCD is not set
 CONFIG_USB_GADGET_DUALSPEED=y
 # CONFIG_USB_ZERO is not set
 # CONFIG_USB_AUDIO is not set
 CONFIG_USB_ETH=m
 CONFIG_USB_ETH_RNDIS=y
 # CONFIG_USB_GADGETFS is not set
 # CONFIG_USB_FILE_STORAGE is not set
 # CONFIG_USB_G_SERIAL is not set
 # CONFIG_USB_MIDI_GADGET is not set
 # CONFIG_USB_G_PRINTER is not set
 # CONFIG_USB_CDC_COMPOSITE is not set
 #
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
+# OTG and related infrastructure
 #
-# CONFIG_USB_GADGET is not set
+# CONFIG_USB_GPIO_VBUS is not set
-# CONFIG_MMC is not set
+# CONFIG_NOP_USB_XCEIV is not set
 CONFIG_MMC=y
 # CONFIG_MMC_DEBUG is not set
 # CONFIG_MMC_UNSAFE_RESUME is not set
 #
 # MMC/SD/SDIO Card Drivers
 #
 CONFIG_MMC_BLOCK=y
 # CONFIG_MMC_BLOCK_BOUNCE is not set
 # CONFIG_SDIO_UART is not set
 # CONFIG_MMC_TEST is not set
 #
 # MMC/SD/SDIO Host Controller Drivers
 #
 # CONFIG_MMC_SDHCI is not set
 CONFIG_MMC_SPI=m
 # CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_RTC_CLASS is not set
 # CONFIG_DMADEVICES is not set
 # CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
 # CONFIG_STAGING is not set
@ -789,9 +911,10 @@ CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
 # CONFIG_OCFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
 CONFIG_FILE_LOCKING=y
 # CONFIG_DNOTIFY is not set
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@ -800,6 +923,11 @@ CONFIG_INOTIFY_USER=y
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
 #
 # Caches
 #
 # CONFIG_FSCACHE is not set
 #
 # CD-ROM/DVD Filesystems
 #
@ -809,8 +937,11 @@ CONFIG_INOTIFY_USER=y
 #
 # DOS/FAT/NT Filesystems
 #
-# CONFIG_MSDOS_FS is not set
+CONFIG_FAT_FS=y
-# CONFIG_VFAT_FS is not set
+CONFIG_MSDOS_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_FAT_DEFAULT_CODEPAGE=437
 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 # CONFIG_NTFS_FS is not set
 #
@ -822,10 +953,7 @@ CONFIG_SYSFS=y
 # CONFIG_TMPFS is not set
 # CONFIG_HUGETLB_PAGE is not set
 # CONFIG_CONFIGFS_FS is not set
-
+CONFIG_MISC_FILESYSTEMS=y
 #
 # Miscellaneous filesystems
 #
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
@ -833,9 +961,19 @@ CONFIG_SYSFS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-# CONFIG_JFFS2_FS is not set
+CONFIG_JFFS2_FS=y
-# CONFIG_YAFFS_FS is not set
+CONFIG_JFFS2_FS_DEBUG=0
 CONFIG_JFFS2_FS_WRITEBUFFER=y
 # CONFIG_JFFS2_FS_WBUF_VERIFY is not set
 # CONFIG_JFFS2_SUMMARY is not set
 # CONFIG_JFFS2_FS_XATTR is not set
 # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
 CONFIG_JFFS2_ZLIB=y
 # CONFIG_JFFS2_LZO is not set
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_OMFS_FS is not set
@ -844,14 +982,70 @@ CONFIG_SYSFS=y
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
+# CONFIG_NILFS2_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
 # CONFIG_NFSD is not set
 CONFIG_LOCKD=m
 CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=m
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-# CONFIG_NLS is not set
+CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_NLS_CODEPAGE_437=y
 # CONFIG_NLS_CODEPAGE_737 is not set
 # CONFIG_NLS_CODEPAGE_775 is not set
 # CONFIG_NLS_CODEPAGE_850 is not set
 # CONFIG_NLS_CODEPAGE_852 is not set
 # CONFIG_NLS_CODEPAGE_855 is not set
 # CONFIG_NLS_CODEPAGE_857 is not set
 # CONFIG_NLS_CODEPAGE_860 is not set
 # CONFIG_NLS_CODEPAGE_861 is not set
 # CONFIG_NLS_CODEPAGE_862 is not set
 # CONFIG_NLS_CODEPAGE_863 is not set
 # CONFIG_NLS_CODEPAGE_864 is not set
 # CONFIG_NLS_CODEPAGE_865 is not set
 # CONFIG_NLS_CODEPAGE_866 is not set
 # CONFIG_NLS_CODEPAGE_869 is not set
 # CONFIG_NLS_CODEPAGE_936 is not set
 # CONFIG_NLS_CODEPAGE_950 is not set
 # CONFIG_NLS_CODEPAGE_932 is not set
 # CONFIG_NLS_CODEPAGE_949 is not set
 # CONFIG_NLS_CODEPAGE_874 is not set
 # CONFIG_NLS_ISO8859_8 is not set
 # CONFIG_NLS_CODEPAGE_1250 is not set
 # CONFIG_NLS_CODEPAGE_1251 is not set
 # CONFIG_NLS_ASCII is not set
 CONFIG_NLS_ISO8859_1=y
 # CONFIG_NLS_ISO8859_2 is not set
 # CONFIG_NLS_ISO8859_3 is not set
 # CONFIG_NLS_ISO8859_4 is not set
 # CONFIG_NLS_ISO8859_5 is not set
 # CONFIG_NLS_ISO8859_6 is not set
 # CONFIG_NLS_ISO8859_7 is not set
 # CONFIG_NLS_ISO8859_9 is not set
 # CONFIG_NLS_ISO8859_13 is not set
 # CONFIG_NLS_ISO8859_14 is not set
 # CONFIG_NLS_ISO8859_15 is not set
 # CONFIG_NLS_KOI8_R is not set
 # CONFIG_NLS_KOI8_U is not set
 # CONFIG_NLS_UTF8 is not set
 # CONFIG_DLM is not set
 #
@ -867,14 +1061,28 @@ CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_SECTION_MISMATCH=y
 # CONFIG_DEBUG_KERNEL is not set
-CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
 # CONFIG_DEBUG_MEMORY_INIT is not set
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
 CONFIG_HAVE_FUNCTION_TRACER=y
 CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
 CONFIG_TRACING_SUPPORT=y
 #
 # Tracers
 #
-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_FUNCTION_TRACER is not set
 # CONFIG_IRQSOFF_TRACER is not set
 # CONFIG_SCHED_TRACER is not set
 # CONFIG_CONTEXT_SWITCH_TRACER is not set
 # CONFIG_EVENT_TRACER is not set
 # CONFIG_BOOT_TRACER is not set
 # CONFIG_TRACE_BRANCH_PROFILING is not set
 # CONFIG_STACK_TRACER is not set
 # CONFIG_KMEMTRACE is not set
 # CONFIG_WORKQUEUE_TRACER is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 CONFIG_DEBUG_VERBOSE=y
@ -888,9 +1096,10 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
 CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
 # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
 # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-# CONFIG_EARLY_PRINTK is not set
+CONFIG_EARLY_PRINTK=y
 CONFIG_CPLB_INFO=y
 CONFIG_ACCESS_CHECK=y
 # CONFIG_BFIN_ISRAM_SELF_TEST is not set
 #
 # Security options
@ -899,8 +1108,9 @@ CONFIG_ACCESS_CHECK=y
 CONFIG_SECURITY=y
 # CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_NETWORK is not set
 # CONFIG_SECURITY_PATH is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
-CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
+# CONFIG_SECURITY_TOMOYO is not set
 CONFIG_CRYPTO=y
 #
@ -979,6 +1189,7 @@ CONFIG_CRYPTO=y
 # Compression
 #
 # CONFIG_CRYPTO_DEFLATE is not set
 # CONFIG_CRYPTO_ZLIB is not set
 # CONFIG_CRYPTO_LZO is not set
 #
@ -986,19 +1197,24 @@ CONFIG_CRYPTO=y
 #
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRYPTO_HW=y
 # CONFIG_BINARY_PRINTF is not set
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
 CONFIG_GENERIC_FIND_LAST_BIT=y
 CONFIG_CRC_CCITT=m
 # CONFIG_CRC16 is not set
 # CONFIG_CRC_T10DIF is not set
-# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC_ITU_T=y
 CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
+CONFIG_CRC7=y
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
 CONFIG_DECOMPRESS_LZMA=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
 CONFIG_NLATTR=y
--- a/arch/blackfin/configs/CM-BF537U_defconfig
+++ b/arch/blackfin/configs/CM-BF537U_defconfig
--- a/arch/blackfin/configs/CM-BF548_defconfig
+++ b/arch/blackfin/configs/CM-BF548_defconfig
--- a/arch/blackfin/configs/CM-BF561_defconfig
+++ b/arch/blackfin/configs/CM-BF561_defconfig
--- a/arch/blackfin/configs/H8606_defconfig
+++ b/arch/blackfin/configs/H8606_defconfig
@ -67,6 +67,7 @@ CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
 CONFIG_MMAP_ALLOW_UNINITIALIZED=y
 CONFIG_RT_MUTEXES=y
 CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
@ -249,6 +250,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_LARGE_ALLOCS=y
 CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 CONFIG_BFIN_GPTIMERS=y
 # CONFIG_DMA_UNCACHED_2M is not set
 CONFIG_DMA_UNCACHED_1M=y
--- a/arch/blackfin/configs/IP0X_defconfig
+++ b/arch/blackfin/configs/IP0X_defconfig
@ -68,6 +68,7 @@ CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
 CONFIG_MMAP_ALLOW_UNINITIALIZED=y
 CONFIG_RT_MUTEXES=y
 CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
@ -261,6 +262,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_LARGE_ALLOCS=y
 CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 # CONFIG_BFIN_GPTIMERS is not set
 # CONFIG_DMA_UNCACHED_2M is not set
 CONFIG_DMA_UNCACHED_1M=y
--- a/arch/blackfin/configs/PNAV-10_defconfig
+++ b/arch/blackfin/configs/PNAV-10_defconfig
@ -63,6 +63,7 @@ CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
 CONFIG_MMAP_ALLOW_UNINITIALIZED=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
@ -285,6 +286,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
 CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 CONFIG_BFIN_GPTIMERS=y
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
--- a/arch/blackfin/configs/SRV1_defconfig
+++ b/arch/blackfin/configs/SRV1_defconfig
@ -72,6 +72,7 @@ CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
 CONFIG_MMAP_ALLOW_UNINITIALIZED=y
 CONFIG_RT_MUTEXES=y
 CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
@ -271,6 +272,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_LARGE_ALLOCS=y
 CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 CONFIG_DMA_UNCACHED_2M=y
 # CONFIG_DMA_UNCACHED_1M is not set
 # CONFIG_DMA_UNCACHED_NONE is not set
@ -700,7 +702,7 @@ CONFIG_INPUT_MISC=y
 # CONFIG_INPUT_YEALINK is not set
 CONFIG_INPUT_UINPUT=y
 # CONFIG_BF53X_PFBUTTONS is not set
-# CONFIG_TWI_KEYPAD is not set
+# CONFIG_INPUT_PCF8574 is not set
 #
 # Hardware I/O ports
--- a/arch/blackfin/configs/TCM-BF537_defconfig
+++ b/arch/blackfin/configs/TCM-BF537_defconfig
@ -1,13 +1,13 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.28-rc2
+# Linux kernel version: 2.6.30.5
 # Tue Jan  6 09:22:17 2009
 #
 # CONFIG_MMU is not set
 # CONFIG_FPU is not set
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
 CONFIG_BLACKFIN=y
 CONFIG_GENERIC_BUG=y
 CONFIG_ZONE_DMA=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
@ -16,6 +16,9 @@ CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_GENERIC_GPIO=y
 CONFIG_FORCE_MAX_ZONEORDER=14
 CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 #
@ -26,49 +29,72 @@ CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
 CONFIG_HAVE_KERNEL_GZIP=y
 CONFIG_HAVE_KERNEL_BZIP2=y
 CONFIG_HAVE_KERNEL_LZMA=y
 # CONFIG_KERNEL_GZIP is not set
 # CONFIG_KERNEL_BZIP2 is not set
 CONFIG_KERNEL_LZMA=y
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
 #
 # RCU Subsystem
 #
 CONFIG_CLASSIC_RCU=y
 # CONFIG_TREE_RCU is not set
 # CONFIG_PREEMPT_RCU is not set
 # CONFIG_TREE_RCU_TRACE is not set
 # CONFIG_PREEMPT_RCU_TRACE is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_CGROUPS is not set
 # CONFIG_GROUP_SCHED is not set
 # CONFIG_CGROUPS is not set
 # CONFIG_SYSFS_DEPRECATED_V2 is not set
 # CONFIG_RELAY is not set
 # CONFIG_NAMESPACES is not set
-# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 # CONFIG_RD_GZIP is not set
 # CONFIG_RD_BZIP2 is not set
 CONFIG_RD_LZMA=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-# CONFIG_SYSCTL is not set
+CONFIG_SYSCTL=y
 CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
 # CONFIG_UID16 is not set
 # CONFIG_SYSCTL_SYSCALL is not set
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
-# CONFIG_HOTPLUG is not set
+# CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 # CONFIG_ELF_CORE is not set
 CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 # CONFIG_FUTEX is not set
 CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 # CONFIG_AIO is not set
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
 CONFIG_MMAP_ALLOW_UNINITIALIZED=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
 # CONFIG_SLOW_WORK is not set
 # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
 # CONFIG_MODULE_FORCE_LOAD is not set
@ -76,11 +102,8 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
@ -96,7 +119,6 @@ CONFIG_IOSCHED_CFQ=y
 # CONFIG_DEFAULT_CFQ is not set
 CONFIG_DEFAULT_NOOP=y
 CONFIG_DEFAULT_IOSCHED="noop"
 CONFIG_CLASSIC_RCU=y
 CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
@ -128,10 +150,15 @@ CONFIG_BF537=y
 # CONFIG_BF538 is not set
 # CONFIG_BF539 is not set
 # CONFIG_BF542 is not set
 # CONFIG_BF542M is not set
 # CONFIG_BF544 is not set
 # CONFIG_BF544M is not set
 # CONFIG_BF547 is not set
 # CONFIG_BF547M is not set
 # CONFIG_BF548 is not set
 # CONFIG_BF548M is not set
 # CONFIG_BF549 is not set
 # CONFIG_BF549M is not set
 # CONFIG_BF561 is not set
 CONFIG_BF_REV_MIN=2
 CONFIG_BF_REV_MAX=3
@ -173,11 +200,11 @@ CONFIG_IRQ_MEM_DMA1=13
 CONFIG_IRQ_WATCH=13
 CONFIG_IRQ_SPI=10
 # CONFIG_BFIN537_STAMP is not set
-# CONFIG_BFIN537_BLUETECHNIX_CM is not set
+# CONFIG_BFIN537_BLUETECHNIX_CM_E is not set
 # CONFIG_BFIN537_BLUETECHNIX_CM_U is not set
 CONFIG_BFIN537_BLUETECHNIX_TCM=y
 # CONFIG_PNAV10 is not set
 # CONFIG_CAMSIG_MINOTAUR is not set
 # CONFIG_GENERIC_BF537_BOARD is not set
 #
 # BF537 Specific Configuration
@ -223,7 +250,10 @@ CONFIG_HZ=250
 # CONFIG_SCHED_HRTICK is not set
 CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 # CONFIG_TICKSOURCE_GPTMR0 is not set
 CONFIG_TICKSOURCE_CORETMR=y
 # CONFIG_CYCLES_CLOCKSOURCE is not set
 # CONFIG_GPTMR0_CLOCKSOURCE is not set
 # CONFIG_NO_HZ is not set
 # CONFIG_HIGH_RES_TIMERS is not set
 CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
@ -273,10 +303,12 @@ CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
 CONFIG_UNEVICTABLE_LRU=y
 CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 # CONFIG_BFIN_GPTIMERS is not set
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
@ -287,10 +319,9 @@ CONFIG_DMA_UNCACHED_1M=y
 # Cache Support
 #
 CONFIG_BFIN_ICACHE=y
-# CONFIG_BFIN_ICACHE_LOCK is not set
+CONFIG_BFIN_EXTMEM_ICACHEABLE=y
 CONFIG_BFIN_DCACHE=y
 # CONFIG_BFIN_DCACHE_BANKA is not set
 CONFIG_BFIN_EXTMEM_ICACHEABLE=y
 CONFIG_BFIN_EXTMEM_DCACHEABLE=y
 CONFIG_BFIN_EXTMEM_WRITEBACK=y
 # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
@ -301,7 +332,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y
 # CONFIG_MPU is not set
 #
-# Asynchonous Memory Configuration
+# Asynchronous Memory Configuration
 #
 #
@ -327,6 +358,7 @@ CONFIG_BANK_3=0xFFC2
 # Bus options (PCI, PCMCIA, EISA, MCA, ISA)
 #
 # CONFIG_ARCH_SUPPORTS_MSI is not set
 # CONFIG_PCCARD is not set
 #
 # Executable file formats
@ -343,13 +375,83 @@ CONFIG_BINFMT_SHARED_FLAT=y
 #
 # CONFIG_PM is not set
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
 # CONFIG_PM_WAKEUP_BY_GPIO is not set
 #
 # CPU Frequency scaling
 #
 # CONFIG_CPU_FREQ is not set
-# CONFIG_NET is not set
+CONFIG_NET=y
 #
 # Networking options
 #
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
 CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
 # CONFIG_XFRM_SUB_POLICY is not set
 # CONFIG_XFRM_MIGRATE is not set
 # CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
 # CONFIG_IP_ADVANCED_ROUTER is not set
 CONFIG_IP_FIB_HASH=y
 # CONFIG_IP_PNP is not set
 # CONFIG_NET_IPIP is not set
 # CONFIG_NET_IPGRE is not set
 # CONFIG_ARPD is not set
 # CONFIG_SYN_COOKIES is not set
 # CONFIG_INET_AH is not set
 # CONFIG_INET_ESP is not set
 # CONFIG_INET_IPCOMP is not set
 # CONFIG_INET_XFRM_TUNNEL is not set
 # CONFIG_INET_TUNNEL is not set
 CONFIG_INET_XFRM_MODE_TRANSPORT=y
 CONFIG_INET_XFRM_MODE_TUNNEL=y
 CONFIG_INET_XFRM_MODE_BEET=y
 CONFIG_INET_LRO=y
 # CONFIG_INET_DIAG is not set
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
 # CONFIG_IP_DCCP is not set
 # CONFIG_IP_SCTP is not set
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
 # CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 # CONFIG_LLC2 is not set
 # CONFIG_IPX is not set
 # CONFIG_ATALK is not set
 # CONFIG_X25 is not set
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
 # CONFIG_PHONET is not set
 # CONFIG_NET_SCHED is not set
 # CONFIG_DCB is not set
 #
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
 # CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
 # CONFIG_WIRELESS is not set
 # CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
 #
 # Device Drivers
@ -358,15 +460,21 @@ CONFIG_ARCH_SUSPEND_POSSIBLE=y
 #
 # Generic Driver Options
 #
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=y
 CONFIG_FIRMWARE_IN_KERNEL=y
 CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_SYS_HYPERVISOR is not set
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 # CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
 # CONFIG_MTD_AR7_PARTS is not set
 #
@ -402,9 +510,10 @@ CONFIG_MTD_CFI_I2=y
 CONFIG_MTD_CFI_INTELEXT=y
 # CONFIG_MTD_CFI_AMDSTD is not set
 # CONFIG_MTD_CFI_STAA is not set
 # CONFIG_MTD_PSD4256G is not set
 CONFIG_MTD_CFI_UTIL=y
 CONFIG_MTD_RAM=y
-# CONFIG_MTD_ROM is not set
+CONFIG_MTD_ROM=m
 # CONFIG_MTD_ABSENT is not set
 #
@ -413,7 +522,7 @@ CONFIG_MTD_RAM=y
 CONFIG_MTD_COMPLEX_MAPPINGS=y
 # CONFIG_MTD_PHYSMAP is not set
 CONFIG_MTD_GPIO_ADDR=y
-CONFIG_MTD_UCLINUX=y
+# CONFIG_MTD_UCLINUX is not set
 # CONFIG_MTD_PLATRAM is not set
 #
@ -435,6 +544,11 @@ CONFIG_MTD_UCLINUX=y
 # CONFIG_MTD_NAND is not set
 # CONFIG_MTD_ONENAND is not set
 #
 # LPDDR flash memory drivers
 #
 # CONFIG_MTD_LPDDR is not set
 #
 # UBI - Unsorted block images
 #
@ -443,15 +557,23 @@ CONFIG_MTD_UCLINUX=y
 CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 # CONFIG_BLK_DEV_LOOP is not set
 # CONFIG_BLK_DEV_NBD is not set
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=4096
 # CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
 # CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_93CX6 is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
 # CONFIG_C2PORT is not set
 #
 # EEPROM support
 #
 # CONFIG_EEPROM_AT25 is not set
 # CONFIG_EEPROM_93CX6 is not set
 CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
@ -464,6 +586,74 @@ CONFIG_HAVE_IDE=y
 # CONFIG_SCSI_NETLINK is not set
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
 CONFIG_COMPAT_NET_DEV_OPS=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
 # CONFIG_VETH is not set
 CONFIG_PHYLIB=y
 #
 # MII PHY device drivers
 #
 # CONFIG_MARVELL_PHY is not set
 # CONFIG_DAVICOM_PHY is not set
 # CONFIG_QSEMI_PHY is not set
 # CONFIG_LXT_PHY is not set
 # CONFIG_CICADA_PHY is not set
 # CONFIG_VITESSE_PHY is not set
 # CONFIG_SMSC_PHY is not set
 # CONFIG_BROADCOM_PHY is not set
 # CONFIG_ICPLUS_PHY is not set
 # CONFIG_REALTEK_PHY is not set
 # CONFIG_NATIONAL_PHY is not set
 # CONFIG_STE10XP is not set
 # CONFIG_LSI_ET1011C_PHY is not set
 # CONFIG_FIXED_PHY is not set
 # CONFIG_MDIO_BITBANG is not set
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
 CONFIG_BFIN_MAC=y
 CONFIG_BFIN_MAC_USE_L1=y
 CONFIG_BFIN_TX_DESC_NUM=10
 CONFIG_BFIN_RX_DESC_NUM=20
 # CONFIG_BFIN_MAC_RMII is not set
 # CONFIG_SMC91X is not set
 # CONFIG_DM9000 is not set
 # CONFIG_ENC28J60 is not set
 # CONFIG_ETHOC is not set
 # CONFIG_SMSC911X is not set
 # CONFIG_DNET is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
 # CONFIG_IBM_NEW_EMAC_TAH is not set
 # CONFIG_IBM_NEW_EMAC_EMAC4 is not set
 # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
 # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
 # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 # CONFIG_B44 is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
 #
 # Wireless LAN
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
 #
 # Enable WiMAX (Networking options) to see the WiMAX drivers
 #
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
 # CONFIG_ISDN is not set
 # CONFIG_PHONE is not set
 #
@ -480,15 +670,12 @@ CONFIG_HAVE_IDE=y
 #
 # Character devices
 #
 # CONFIG_AD9960 is not set
 # CONFIG_SPI_ADC_BF533 is not set
 # CONFIG_BF5xx_PPIFCD is not set
 # CONFIG_BFIN_SIMPLE_TIMER is not set
 # CONFIG_BF5xx_PPI is not set
 CONFIG_BFIN_SPORT=y
 # CONFIG_BFIN_TIMER_LATENCY is not set
 CONFIG_BFIN_DMA_INTERFACE=m
-# CONFIG_SIMPLE_GPIO is not set
+# CONFIG_BFIN_PPI is not set
 # CONFIG_BFIN_PPIFCD is not set
 # CONFIG_BFIN_SIMPLE_TIMER is not set
 # CONFIG_BFIN_SPI_ADC is not set
 CONFIG_BFIN_SPORT=y
 # CONFIG_VT is not set
 # CONFIG_DEVKMEM is not set
 # CONFIG_BFIN_JTAG_COMM is not set
@ -502,6 +689,7 @@ CONFIG_BFIN_DMA_INTERFACE=m
 #
 # Non-8250 serial port support
 #
 # CONFIG_SERIAL_MAX3100 is not set
 CONFIG_SERIAL_BFIN=y
 CONFIG_SERIAL_BFIN_CONSOLE=y
 CONFIG_SERIAL_BFIN_DMA=y
@ -514,6 +702,7 @@ CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_SERIAL_BFIN_SPORT is not set
 CONFIG_UNIX98_PTYS=y
 # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 # CONFIG_LEGACY_PTYS is not set
 #
@ -534,39 +723,17 @@ CONFIG_SPI_MASTER=y
 #
 CONFIG_SPI_BFIN=y
 # CONFIG_SPI_BFIN_LOCK is not set
 # CONFIG_SPI_BFIN_SPORT is not set
 # CONFIG_SPI_BITBANG is not set
 # CONFIG_SPI_GPIO is not set
 #
 # SPI Protocol Masters
 #
 # CONFIG_EEPROM_AT25 is not set
 # CONFIG_SPI_SPIDEV is not set
 # CONFIG_SPI_TLE62X0 is not set
 CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
-CONFIG_GPIOLIB=y
+# CONFIG_GPIOLIB is not set
 # CONFIG_DEBUG_GPIO is not set
 CONFIG_GPIO_SYSFS=y
 #
 # Memory mapped GPIO expanders:
 #
 #
 # I2C GPIO expanders:
 #
 # CONFIG_GPIO_MAX732X is not set
 # CONFIG_GPIO_PCA953X is not set
 # CONFIG_GPIO_PCF857X is not set
 #
 # PCI GPIO expanders:
 #
 #
 # SPI GPIO expanders:
 #
 # CONFIG_GPIO_MAX7301 is not set
 # CONFIG_GPIO_MCP23S08 is not set
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
@ -580,6 +747,12 @@ CONFIG_WATCHDOG=y
 #
 # CONFIG_SOFT_WATCHDOG is not set
 CONFIG_BFIN_WDT=y
 CONFIG_SSB_POSSIBLE=y
 #
 # Sonics Silicon Backplane
 #
 # CONFIG_SSB is not set
 #
 # Multifunction device drivers
@ -588,7 +761,7 @@ CONFIG_BFIN_WDT=y
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
 # CONFIG_MFD_TMIO is not set
-# CONFIG_MFD_WM8400 is not set
+# CONFIG_REGULATOR is not set
 #
 # Multimedia devices
@ -598,6 +771,7 @@ CONFIG_BFIN_WDT=y
 # Multimedia core support
 #
 # CONFIG_VIDEO_DEV is not set
 # CONFIG_DVB_CORE is not set
 # CONFIG_VIDEO_MEDIA is not set
 #
@ -618,13 +792,81 @@ CONFIG_BFIN_WDT=y
 #
 # CONFIG_DISPLAY_SUPPORT is not set
 # CONFIG_SOUND is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
-# CONFIG_MMC is not set
+CONFIG_USB_ARCH_HAS_HCD=y
 # CONFIG_USB_ARCH_HAS_OHCI is not set
 # CONFIG_USB_ARCH_HAS_EHCI is not set
 # CONFIG_USB is not set
 # CONFIG_USB_OTG_WHITELIST is not set
 # CONFIG_USB_OTG_BLACKLIST_HUB is not set
 # CONFIG_USB_GADGET_MUSB_HDRC is not set
 #
 # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
 #
 CONFIG_USB_GADGET=y
 # CONFIG_USB_GADGET_DEBUG_FILES is not set
 # CONFIG_USB_GADGET_DEBUG_FS is not set
 CONFIG_USB_GADGET_VBUS_DRAW=2
 CONFIG_USB_GADGET_SELECTED=y
 # CONFIG_USB_GADGET_AT91 is not set
 # CONFIG_USB_GADGET_ATMEL_USBA is not set
 # CONFIG_USB_GADGET_FSL_USB2 is not set
 # CONFIG_USB_GADGET_LH7A40X is not set
 # CONFIG_USB_GADGET_OMAP is not set
 # CONFIG_USB_GADGET_PXA25X is not set
 # CONFIG_USB_GADGET_PXA27X is not set
 # CONFIG_USB_GADGET_S3C2410 is not set
 # CONFIG_USB_GADGET_IMX is not set
 # CONFIG_USB_GADGET_M66592 is not set
 # CONFIG_USB_GADGET_AMD5536UDC is not set
 # CONFIG_USB_GADGET_FSL_QE is not set
 # CONFIG_USB_GADGET_CI13XXX is not set
 CONFIG_USB_GADGET_NET2272=y
 CONFIG_USB_NET2272=y
 # CONFIG_USB_GADGET_NET2280 is not set
 # CONFIG_USB_GADGET_GOKU is not set
 # CONFIG_USB_GADGET_DUMMY_HCD is not set
 CONFIG_USB_GADGET_DUALSPEED=y
 # CONFIG_USB_ZERO is not set
 # CONFIG_USB_AUDIO is not set
 CONFIG_USB_ETH=y
 CONFIG_USB_ETH_RNDIS=y
 # CONFIG_USB_GADGETFS is not set
 # CONFIG_USB_FILE_STORAGE is not set
 # CONFIG_USB_G_SERIAL is not set
 # CONFIG_USB_MIDI_GADGET is not set
 # CONFIG_USB_G_PRINTER is not set
 # CONFIG_USB_CDC_COMPOSITE is not set
 #
 # OTG and related infrastructure
 #
 # CONFIG_USB_GPIO_VBUS is not set
 # CONFIG_NOP_USB_XCEIV is not set
 CONFIG_MMC=y
 # CONFIG_MMC_DEBUG is not set
 # CONFIG_MMC_UNSAFE_RESUME is not set
 #
 # MMC/SD/SDIO Card Drivers
 #
 CONFIG_MMC_BLOCK=y
 CONFIG_MMC_BLOCK_BOUNCE=y
 # CONFIG_SDIO_UART is not set
 # CONFIG_MMC_TEST is not set
 #
 # MMC/SD/SDIO Host Controller Drivers
 #
 # CONFIG_MMC_SDHCI is not set
 CONFIG_MMC_SPI=m
 # CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_RTC_CLASS is not set
 # CONFIG_DMADEVICES is not set
 # CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
 # CONFIG_STAGING is not set
@ -641,8 +883,10 @@ CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
 # CONFIG_OCFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
 CONFIG_FILE_LOCKING=y
 # CONFIG_DNOTIFY is not set
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@ -651,6 +895,11 @@ CONFIG_INOTIFY_USER=y
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
 #
 # Caches
 #
 # CONFIG_FSCACHE is not set
 #
 # CD-ROM/DVD Filesystems
 #
@ -660,8 +909,11 @@ CONFIG_INOTIFY_USER=y
 #
 # DOS/FAT/NT Filesystems
 #
-# CONFIG_MSDOS_FS is not set
+CONFIG_FAT_FS=y
-# CONFIG_VFAT_FS is not set
+CONFIG_MSDOS_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_FAT_DEFAULT_CODEPAGE=437
 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 # CONFIG_NTFS_FS is not set
 #
@ -673,10 +925,7 @@ CONFIG_SYSFS=y
 # CONFIG_TMPFS is not set
 # CONFIG_HUGETLB_PAGE is not set
 # CONFIG_CONFIGFS_FS is not set
-
+CONFIG_MISC_FILESYSTEMS=y
 #
 # Miscellaneous filesystems
 #
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
@ -684,9 +933,19 @@ CONFIG_SYSFS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-# CONFIG_YAFFS_FS is not set
+CONFIG_JFFS2_FS=y
-# CONFIG_JFFS2_FS is not set
+CONFIG_JFFS2_FS_DEBUG=0
 CONFIG_JFFS2_FS_WRITEBUFFER=y
 # CONFIG_JFFS2_FS_WBUF_VERIFY is not set
 # CONFIG_JFFS2_SUMMARY is not set
 # CONFIG_JFFS2_FS_XATTR is not set
 # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
 CONFIG_JFFS2_ZLIB=y
 # CONFIG_JFFS2_LZO is not set
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_OMFS_FS is not set
@ -695,13 +954,62 @@ CONFIG_SYSFS=y
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
 # CONFIG_NILFS2_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
 # CONFIG_NFS_FS is not set
 # CONFIG_NFSD is not set
 # CONFIG_SMB_FS is not set
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-# CONFIG_NLS is not set
+CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_NLS_CODEPAGE_437=y
 # CONFIG_NLS_CODEPAGE_737 is not set
 # CONFIG_NLS_CODEPAGE_775 is not set
 # CONFIG_NLS_CODEPAGE_850 is not set
 # CONFIG_NLS_CODEPAGE_852 is not set
 # CONFIG_NLS_CODEPAGE_855 is not set
 # CONFIG_NLS_CODEPAGE_857 is not set
 # CONFIG_NLS_CODEPAGE_860 is not set
 # CONFIG_NLS_CODEPAGE_861 is not set
 # CONFIG_NLS_CODEPAGE_862 is not set
 # CONFIG_NLS_CODEPAGE_863 is not set
 # CONFIG_NLS_CODEPAGE_864 is not set
 # CONFIG_NLS_CODEPAGE_865 is not set
 # CONFIG_NLS_CODEPAGE_866 is not set
 # CONFIG_NLS_CODEPAGE_869 is not set
 # CONFIG_NLS_CODEPAGE_936 is not set
 # CONFIG_NLS_CODEPAGE_950 is not set
 # CONFIG_NLS_CODEPAGE_932 is not set
 # CONFIG_NLS_CODEPAGE_949 is not set
 # CONFIG_NLS_CODEPAGE_874 is not set
 # CONFIG_NLS_ISO8859_8 is not set
 # CONFIG_NLS_CODEPAGE_1250 is not set
 # CONFIG_NLS_CODEPAGE_1251 is not set
 # CONFIG_NLS_ASCII is not set
 CONFIG_NLS_ISO8859_1=y
 # CONFIG_NLS_ISO8859_2 is not set
 # CONFIG_NLS_ISO8859_3 is not set
 # CONFIG_NLS_ISO8859_4 is not set
 # CONFIG_NLS_ISO8859_5 is not set
 # CONFIG_NLS_ISO8859_6 is not set
 # CONFIG_NLS_ISO8859_7 is not set
 # CONFIG_NLS_ISO8859_9 is not set
 # CONFIG_NLS_ISO8859_13 is not set
 # CONFIG_NLS_ISO8859_14 is not set
 # CONFIG_NLS_ISO8859_15 is not set
 # CONFIG_NLS_KOI8_R is not set
 # CONFIG_NLS_KOI8_U is not set
 # CONFIG_NLS_UTF8 is not set
 # CONFIG_DLM is not set
 #
 # Kernel hacking
@ -714,12 +1022,30 @@ CONFIG_FRAME_WARN=1024
 # CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_SECTION_MISMATCH=y
 # CONFIG_DEBUG_KERNEL is not set
-CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
 # CONFIG_DEBUG_MEMORY_INIT is not set
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
 CONFIG_TRACING_SUPPORT=y
 #
 # Tracers
 #
 # CONFIG_FUNCTION_TRACER is not set
 # CONFIG_IRQSOFF_TRACER is not set
 # CONFIG_SCHED_TRACER is not set
 # CONFIG_CONTEXT_SWITCH_TRACER is not set
 # CONFIG_EVENT_TRACER is not set
 # CONFIG_BOOT_TRACER is not set
 # CONFIG_TRACE_BRANCH_PROFILING is not set
 # CONFIG_STACK_TRACER is not set
 # CONFIG_KMEMTRACE is not set
 # CONFIG_WORKQUEUE_TRACER is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 CONFIG_DEBUG_VERBOSE=y
@ -733,9 +1059,10 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
 CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
 # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
 # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-# CONFIG_EARLY_PRINTK is not set
+CONFIG_EARLY_PRINTK=y
 CONFIG_CPLB_INFO=y
 CONFIG_ACCESS_CHECK=y
 # CONFIG_BFIN_ISRAM_SELF_TEST is not set
 #
 # Security options
@ -744,20 +1071,110 @@ CONFIG_ACCESS_CHECK=y
 # CONFIG_SECURITY is not set
 # CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
-# CONFIG_CRYPTO is not set
+CONFIG_CRYPTO=y
 #
 # Crypto core or helper
 #
 # CONFIG_CRYPTO_FIPS is not set
 # CONFIG_CRYPTO_MANAGER is not set
 # CONFIG_CRYPTO_MANAGER2 is not set
 # CONFIG_CRYPTO_GF128MUL is not set
 # CONFIG_CRYPTO_NULL is not set
 # CONFIG_CRYPTO_CRYPTD is not set
 # CONFIG_CRYPTO_AUTHENC is not set
 # CONFIG_CRYPTO_TEST is not set
 #
 # Authenticated Encryption with Associated Data
 #
 # CONFIG_CRYPTO_CCM is not set
 # CONFIG_CRYPTO_GCM is not set
 # CONFIG_CRYPTO_SEQIV is not set
 #
 # Block modes
 #
 # CONFIG_CRYPTO_CBC is not set
 # CONFIG_CRYPTO_CTR is not set
 # CONFIG_CRYPTO_CTS is not set
 # CONFIG_CRYPTO_ECB is not set
 # CONFIG_CRYPTO_LRW is not set
 # CONFIG_CRYPTO_PCBC is not set
 # CONFIG_CRYPTO_XTS is not set
 #
 # Hash modes
 #
 # CONFIG_CRYPTO_HMAC is not set
 # CONFIG_CRYPTO_XCBC is not set
 #
 # Digest
 #
 # CONFIG_CRYPTO_CRC32C is not set
 # CONFIG_CRYPTO_MD4 is not set
 # CONFIG_CRYPTO_MD5 is not set
 # CONFIG_CRYPTO_MICHAEL_MIC is not set
 # CONFIG_CRYPTO_RMD128 is not set
 # CONFIG_CRYPTO_RMD160 is not set
 # CONFIG_CRYPTO_RMD256 is not set
 # CONFIG_CRYPTO_RMD320 is not set
 # CONFIG_CRYPTO_SHA1 is not set
 # CONFIG_CRYPTO_SHA256 is not set
 # CONFIG_CRYPTO_SHA512 is not set
 # CONFIG_CRYPTO_TGR192 is not set
 # CONFIG_CRYPTO_WP512 is not set
 #
 # Ciphers
 #
 # CONFIG_CRYPTO_AES is not set
 # CONFIG_CRYPTO_ANUBIS is not set
 # CONFIG_CRYPTO_ARC4 is not set
 # CONFIG_CRYPTO_BLOWFISH is not set
 # CONFIG_CRYPTO_CAMELLIA is not set
 # CONFIG_CRYPTO_CAST5 is not set
 # CONFIG_CRYPTO_CAST6 is not set
 # CONFIG_CRYPTO_DES is not set
 # CONFIG_CRYPTO_FCRYPT is not set
 # CONFIG_CRYPTO_KHAZAD is not set
 # CONFIG_CRYPTO_SALSA20 is not set
 # CONFIG_CRYPTO_SEED is not set
 # CONFIG_CRYPTO_SERPENT is not set
 # CONFIG_CRYPTO_TEA is not set
 # CONFIG_CRYPTO_TWOFISH is not set
 #
 # Compression
 #
 # CONFIG_CRYPTO_DEFLATE is not set
 # CONFIG_CRYPTO_ZLIB is not set
 # CONFIG_CRYPTO_LZO is not set
 #
 # Random Number Generation
 #
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRYPTO_HW=y
 # CONFIG_BINARY_PRINTF is not set
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
 CONFIG_GENERIC_FIND_LAST_BIT=y
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
 # CONFIG_CRC_T10DIF is not set
-# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC_ITU_T=y
-# CONFIG_CRC32 is not set
+CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
+CONFIG_CRC7=y
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
-CONFIG_PLIST=y
+CONFIG_ZLIB_DEFLATE=y
 CONFIG_DECOMPRESS_LZMA=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
 CONFIG_NLATTR=y
--- a/arch/blackfin/include/asm/bfin-global.h
+++ b/arch/blackfin/include/asm/bfin-global.h
@ -11,9 +11,6 @@
 #ifndef __ASSEMBLY__
 #include <asm/sections.h>
 #include <asm/ptrace.h>
 #include <asm/user.h>
 #include <linux/linkage.h>
 #include <linux/types.h>
@ -23,6 +20,12 @@
 # define DMA_UNCACHED_REGION (2 * 1024 * 1024)
 #elif defined(CONFIG_DMA_UNCACHED_1M)
 # define DMA_UNCACHED_REGION (1024 * 1024)
 #elif defined(CONFIG_DMA_UNCACHED_512K)
 # define DMA_UNCACHED_REGION (512 * 1024)
 #elif defined(CONFIG_DMA_UNCACHED_256K)
 # define DMA_UNCACHED_REGION (256 * 1024)
 #elif defined(CONFIG_DMA_UNCACHED_128K)
 # define DMA_UNCACHED_REGION (128 * 1024)
 #else
 # define DMA_UNCACHED_REGION (0)
 #endif
@ -35,6 +38,7 @@ extern unsigned long get_sclk(void);
 extern unsigned long sclk_to_usecs(unsigned long sclk);
 extern unsigned long usecs_to_sclk(unsigned long usecs);
 struct pt_regs;
 extern void dump_bfin_process(struct pt_regs *regs);
 extern void dump_bfin_mem(struct pt_regs *regs);
 extern void dump_bfin_trace_buffer(void);
--- a/arch/blackfin/include/asm/bug.h
+++ b/arch/blackfin/include/asm/bug.h
@ -47,7 +47,7 @@
 #define BUG()								\
 	do {								\
 		_BUG_OR_WARN(0);					\
-		for (;;);						\
+		unreachable();						\
 	} while (0)
 #define WARN_ON(condition)							\
--- a/arch/blackfin/include/asm/cacheflush.h
+++ b/arch/blackfin/include/asm/cacheflush.h
@ -10,6 +10,7 @@
 #define _BLACKFIN_CACHEFLUSH_H
 #include <asm/blackfin.h>	/* for SSYNC() */
 #include <asm/sections.h>	/* for _ramend */
 extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address);
 extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address);
--- a/arch/blackfin/include/asm/checksum.h
+++ b/arch/blackfin/include/asm/checksum.h
@ -8,64 +8,13 @@
 #ifndef _BFIN_CHECKSUM_H
 #define _BFIN_CHECKSUM_H
 /*
 * computes the checksum of a memory block at buff, length len,
 * and adds in "sum" (32-bit)
 *
 * returns a 32-bit number suitable for feeding into itself
 * or csum_tcpudp_magic
 *
 * this function must be called with even lengths, except
 * for the last fragment, which may be odd
 *
 * it's best to have buff aligned on a 32-bit boundary
 */
 __wsum csum_partial(const void *buff, int len, __wsum sum);
 /*
 * the same as csum_partial, but copies from src while it
 * checksums
 *
 * here even more important to align src and dst on a 32-bit (or even
 * better 64-bit) boundary
 */
 __wsum csum_partial_copy(const void *src, void *dst,
 			       int len, __wsum sum);
 /*
 * the same as csum_partial_copy, but copies from user space.
 *
 * here even more important to align src and dst on a 32-bit (or even
 * better 64-bit) boundary
 */
 extern __wsum csum_partial_copy_from_user(const void __user *src, void *dst,
 					  int len, __wsum sum, int *csum_err);
 #define csum_partial_copy_nocheck(src, dst, len, sum)	\
 	csum_partial_copy((src), (dst), (len), (sum))
 __sum16 ip_fast_csum(unsigned char *iph, unsigned int ihl);
 /*
 *	Fold a partial checksum
 */
 static inline __sum16 csum_fold(__wsum sum)
 {
 	while (sum >> 16)
 		sum = (sum & 0xffff) + (sum >> 16);
 	return ((~(sum << 16)) >> 16);
 }
 /*
 * computes the checksum of the TCP/UDP pseudo-header
 * returns a 16-bit checksum, already complemented
 */
 static inline __wsum
-csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
+__csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
 		   unsigned short proto, __wsum sum)
 {
 	unsigned int carry;
@ -88,19 +37,8 @@ csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
 	return (sum);
 }
 #define csum_tcpudp_nofold __csum_tcpudp_nofold
-static inline __sum16
+#include <asm-generic/checksum.h>
 csum_tcpudp_magic(__be32 saddr, __be32 daddr, unsigned short len,
 		  unsigned short proto, __wsum sum)
 {
 	return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum));
 }
-/*
+#endif
 * this routine is used for miscellaneous IP-like checksums, mainly
 * in icmp.c
 */
 extern __sum16 ip_compute_csum(const void *buff, int len);
 #endif				/* _BFIN_CHECKSUM_H */
--- a/arch/blackfin/include/asm/clocks.h
+++ b/arch/blackfin/include/asm/clocks.h
@ -9,6 +9,8 @@
 #ifndef _BFIN_CLOCKS_H
 #define _BFIN_CLOCKS_H
 #include <asm/dpmc.h>
 #ifdef CONFIG_CCLK_DIV_1
 # define CONFIG_CCLK_ACT_DIV   CCLK_DIV1
 # define CONFIG_CCLK_DIV 1
--- a/arch/blackfin/include/asm/dma-mapping.h
+++ b/arch/blackfin/include/asm/dma-mapping.h
@ -7,9 +7,9 @@
 #ifndef _BLACKFIN_DMA_MAPPING_H
 #define _BLACKFIN_DMA_MAPPING_H
-#include <asm/scatterlist.h>
+#include <asm/cacheflush.h>
 struct scatterlist;
 void dma_alloc_init(unsigned long start, unsigned long end);
 void *dma_alloc_coherent(struct device *dev, size_t size,
 			 dma_addr_t *dma_handle, gfp_t gfp);
 void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
@ -20,13 +20,51 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
 */
 #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
 #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
 #define dma_supported(d, m)         (1)
 #define dma_get_cache_alignment()   (32)
 #define dma_is_consistent(d, h)     (1)
-static inline
+static inline int
-int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
+dma_set_mask(struct device *dev, u64 dma_mask)
 {
 	if (!dev->dma_mask || !dma_supported(dev, dma_mask))
 		return -EIO;
 	*dev->dma_mask = dma_mask;
 	return 0;
 }
 static inline int
 dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
 {
 	return 0;
 }
 extern void
 __dma_sync(dma_addr_t addr, size_t size, enum dma_data_direction dir);
 static inline void
 _dma_sync(dma_addr_t addr, size_t size, enum dma_data_direction dir)
 {
 	if (!__builtin_constant_p(dir)) {
 		__dma_sync(addr, size, dir);
 		return;
 	}
 	switch (dir) {
 	case DMA_NONE:
 		BUG();
 	case DMA_TO_DEVICE:		/* writeback only */
 		flush_dcache_range(addr, addr + size);
 		break;
 	case DMA_FROM_DEVICE: /* invalidate only */
 	case DMA_BIDIRECTIONAL: /* flush and invalidate */
 		/* Blackfin has no dedicated invalidate (it includes a flush) */
 		invalidate_dcache_range(addr, addr + size);
 		break;
 	}
 }
 /*
 * Map a single buffer of the indicated size for DMA in streaming mode.
 * The 32-bit bus address to use is returned.
@ -34,8 +72,13 @@ int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
 * Once the device is given the dma address, the device owns this memory
 * until either pci_unmap_single or pci_dma_sync_single is performed.
 */
-extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
+static inline dma_addr_t
-				 enum dma_data_direction direction);
+dma_map_single(struct device *dev, void *ptr, size_t size,
 	       enum dma_data_direction dir)
 {
 	_dma_sync((dma_addr_t)ptr, size, dir);
 	return (dma_addr_t) ptr;
 }
 static inline dma_addr_t
 dma_map_page(struct device *dev, struct page *page,
@ -53,8 +96,12 @@ dma_map_page(struct device *dev, struct page *page,
 * After this call, reads by the cpu to the buffer are guarenteed to see
 * whatever the device wrote there.
 */
-extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
+static inline void
-			  enum dma_data_direction direction);
+dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
 		 enum dma_data_direction dir)
 {
 	BUG_ON(!valid_dma_direction(dir));
 }
 static inline void
 dma_unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
@ -80,38 +127,66 @@ dma_unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
 * the same here.
 */
 extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
-		      enum dma_data_direction direction);
+		      enum dma_data_direction dir);
 /*
 * Unmap a set of streaming mode DMA translations.
 * Again, cpu read rules concerning calls here are the same as for
 * pci_unmap_single() above.
 */
-extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
+static inline void
-		      int nhwentries, enum dma_data_direction direction);
+dma_unmap_sg(struct device *dev, struct scatterlist *sg,
-
+	     int nhwentries, enum dma_data_direction dir)
 static inline void dma_sync_single_for_cpu(struct device *dev,
 					dma_addr_t handle, size_t size,
 					enum dma_data_direction dir)
 {
 	BUG_ON(!valid_dma_direction(dir));
 }
-static inline void dma_sync_single_for_device(struct device *dev,
+static inline void
-					dma_addr_t handle, size_t size,
+dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t handle,
-					enum dma_data_direction dir)
+			      unsigned long offset, size_t size,
 			      enum dma_data_direction dir)
 {
 	BUG_ON(!valid_dma_direction(dir));
 }
-static inline void dma_sync_sg_for_cpu(struct device *dev,
+static inline void
-					struct scatterlist *sg,
+dma_sync_single_range_for_device(struct device *dev, dma_addr_t handle,
-					int nents, enum dma_data_direction dir)
+				 unsigned long offset, size_t size,
 				 enum dma_data_direction dir)
 {
 	_dma_sync(handle + offset, size, dir);
 }
-static inline void dma_sync_sg_for_device(struct device *dev,
+static inline void
-					struct scatterlist *sg,
+dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle, size_t size,
-					int nents, enum dma_data_direction dir)
+			enum dma_data_direction dir)
 {
 	dma_sync_single_range_for_cpu(dev, handle, 0, size, dir);
 }
 static inline void
 dma_sync_single_for_device(struct device *dev, dma_addr_t handle, size_t size,
 			   enum dma_data_direction dir)
 {
 	dma_sync_single_range_for_device(dev, handle, 0, size, dir);
 }
 static inline void
 dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nents,
 		    enum dma_data_direction dir)
 {
 	BUG_ON(!valid_dma_direction(dir));
 }
 extern void
 dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
 		       int nents, enum dma_data_direction dir);
 static inline void
 dma_cache_sync(struct device *dev, void *vaddr, size_t size,
 	       enum dma_data_direction dir)
 {
 	_dma_sync((dma_addr_t)vaddr, size, dir);
 }
 #endif				/* _BLACKFIN_DMA_MAPPING_H */
--- a/arch/blackfin/include/asm/dma.h
+++ b/arch/blackfin/include/asm/dma.h
@ -10,46 +10,70 @@
 #include <linux/interrupt.h>
 #include <mach/dma.h>
 #include <asm/atomic.h>
 #include <asm/blackfin.h>
 #include <asm/page.h>
 #include <asm-generic/dma.h>
-#define MAX_DMA_ADDRESS PAGE_OFFSET
+/* DMA_CONFIG Masks */
 #define DMAEN			0x0001	/* DMA Channel Enable */
 #define WNR				0x0002	/* Channel Direction (W/R*) */
 #define WDSIZE_8		0x0000	/* Transfer Word Size = 8 */
 #define WDSIZE_16		0x0004	/* Transfer Word Size = 16 */
 #define WDSIZE_32		0x0008	/* Transfer Word Size = 32 */
 #define DMA2D			0x0010	/* DMA Mode (2D/1D*) */
 #define RESTART			0x0020	/* DMA Buffer Clear */
 #define DI_SEL			0x0040	/* Data Interrupt Timing Select */
 #define DI_EN			0x0080	/* Data Interrupt Enable */
 #define NDSIZE_0		0x0000	/* Next Descriptor Size = 0 (Stop/Autobuffer) */
 #define NDSIZE_1		0x0100	/* Next Descriptor Size = 1 */
 #define NDSIZE_2		0x0200	/* Next Descriptor Size = 2 */
 #define NDSIZE_3		0x0300	/* Next Descriptor Size = 3 */
 #define NDSIZE_4		0x0400	/* Next Descriptor Size = 4 */
 #define NDSIZE_5		0x0500	/* Next Descriptor Size = 5 */
 #define NDSIZE_6		0x0600	/* Next Descriptor Size = 6 */
 #define NDSIZE_7		0x0700	/* Next Descriptor Size = 7 */
 #define NDSIZE_8		0x0800	/* Next Descriptor Size = 8 */
 #define NDSIZE_9		0x0900	/* Next Descriptor Size = 9 */
 #define NDSIZE			0x0f00	/* Next Descriptor Size */
 #define DMAFLOW			0x7000	/* Flow Control */
 #define DMAFLOW_STOP	0x0000	/* Stop Mode */
 #define DMAFLOW_AUTO	0x1000	/* Autobuffer Mode */
 #define DMAFLOW_ARRAY	0x4000	/* Descriptor Array Mode */
 #define DMAFLOW_SMALL	0x6000	/* Small Model Descriptor List Mode */
 #define DMAFLOW_LARGE	0x7000	/* Large Model Descriptor List Mode */
-/*****************************************************************************
+/* DMA_IRQ_STATUS Masks */
-*        Generic DMA  Declarations
+#define DMA_DONE		0x0001	/* DMA Completion Interrupt Status */
-*
+#define DMA_ERR			0x0002	/* DMA Error Interrupt Status */
-****************************************************************************/
+#define DFETCH			0x0004	/* DMA Descriptor Fetch Indicator */
-enum dma_chan_status {
+#define DMA_RUN			0x0008	/* DMA Channel Running Indicator */
 	DMA_CHANNEL_FREE,
 	DMA_CHANNEL_REQUESTED,
 	DMA_CHANNEL_ENABLED,
 };
 /*-------------------------
 * config reg bits value
 *-------------------------*/
-#define DATA_SIZE_8 		0
+#define DATA_SIZE_8			0
-#define DATA_SIZE_16 		1
+#define DATA_SIZE_16		1
-#define DATA_SIZE_32 		2
+#define DATA_SIZE_32		2
-#define DMA_FLOW_STOP 		0
+#define DMA_FLOW_STOP		0
-#define DMA_FLOW_AUTO 		1
+#define DMA_FLOW_AUTO		1
-#define DMA_FLOW_ARRAY 		4
+#define DMA_FLOW_ARRAY		4
-#define DMA_FLOW_SMALL 		6
+#define DMA_FLOW_SMALL		6
-#define DMA_FLOW_LARGE 		7
+#define DMA_FLOW_LARGE		7
-#define DIMENSION_LINEAR    0
+#define DIMENSION_LINEAR	0
-#define DIMENSION_2D           1
+#define DIMENSION_2D		1
-#define DIR_READ     0
+#define DIR_READ			0
-#define DIR_WRITE    1
+#define DIR_WRITE			1
-#define INTR_DISABLE   0
+#define INTR_DISABLE		0
-#define INTR_ON_BUF    2
+#define INTR_ON_BUF			2
-#define INTR_ON_ROW    3
+#define INTR_ON_ROW			3
 #define DMA_NOSYNC_KEEP_DMA_BUF	0
-#define DMA_SYNC_RESTART	1
+#define DMA_SYNC_RESTART		1
 struct dmasg {
 	void *next_desc_addr;
@ -104,11 +128,9 @@ struct dma_register {
 };
 struct mutex;
 struct dma_channel {
 	struct mutex dmalock;
 	const char *device_id;
-	enum dma_chan_status chan_status;
+	atomic_t chan_status;
 	volatile struct dma_register *regs;
 	struct dmasg *sg;		/* large mode descriptor */
 	unsigned int irq;
@ -220,27 +242,20 @@ static inline void set_dma_sg(unsigned int channel, struct dmasg *sg, int ndsize
 static inline int dma_channel_active(unsigned int channel)
 {
-	if (dma_ch[channel].chan_status == DMA_CHANNEL_FREE)
+	return atomic_read(&dma_ch[channel].chan_status);
 		return 0;
 	else
 		return 1;
 }
 static inline void disable_dma(unsigned int channel)
 {
 	dma_ch[channel].regs->cfg &= ~DMAEN;
 	SSYNC();
 	dma_ch[channel].chan_status = DMA_CHANNEL_REQUESTED;
 }
 static inline void enable_dma(unsigned int channel)
 {
 	dma_ch[channel].regs->curr_x_count = 0;
 	dma_ch[channel].regs->curr_y_count = 0;
 	dma_ch[channel].regs->cfg |= DMAEN;
 	dma_ch[channel].chan_status = DMA_CHANNEL_ENABLED;
 }
 void free_dma(unsigned int channel);
 int request_dma(unsigned int channel, const char *device_id);
 int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data);
 static inline void dma_disable_irq(unsigned int channel)
--- a/arch/blackfin/include/asm/dpmc.h
+++ b/arch/blackfin/include/asm/dpmc.h
@ -1,7 +1,7 @@
 /*
 * Miscellaneous IOCTL commands for Dynamic Power Management Controller Driver
 *
- * Copyright (C) 2004-2008 Analog Device Inc.
+ * Copyright (C) 2004-2009 Analog Device Inc.
 *
 * Licensed under the GPL-2
 */
@ -9,7 +9,109 @@
 #ifndef _BLACKFIN_DPMC_H_
 #define _BLACKFIN_DPMC_H_
-#ifdef __KERNEL__
+/* PLL_CTL Masks */
 #define DF			0x0001	/* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
 #define PLL_OFF			0x0002	/* PLL Not Powered */
 #define STOPCK			0x0008	/* Core Clock Off */
 #define PDWN			0x0020	/* Enter Deep Sleep Mode */
 #ifdef __ADSPBF539__
 # define IN_DELAY		0x0014	/* Add 200ps Delay To EBIU Input Latches */
 # define OUT_DELAY		0x00C0	/* Add 200ps Delay To EBIU Output Signals */
 #else
 # define IN_DELAY		0x0040	/* Add 200ps Delay To EBIU Input Latches */
 # define OUT_DELAY		0x0080	/* Add 200ps Delay To EBIU Output Signals */
 #endif
 #define BYPASS			0x0100	/* Bypass the PLL */
 #define MSEL			0x7E00	/* Multiplier Select For CCLK/VCO Factors */
 #define SPORT_HYST		0x8000	/* Enable Additional Hysteresis on SPORT Input Pins */
 #define SET_MSEL(x)		(((x)&0x3F) << 0x9)	/* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
 /* PLL_DIV Masks */
 #define SSEL			0x000F	/* System Select */
 #define CSEL			0x0030	/* Core Select */
 #define CSEL_DIV1		0x0000	/* CCLK = VCO / 1 */
 #define CSEL_DIV2		0x0010	/* CCLK = VCO / 2 */
 #define CSEL_DIV4		0x0020	/* CCLK = VCO / 4 */
 #define CSEL_DIV8		0x0030	/* CCLK = VCO / 8 */
 #define CCLK_DIV1 CSEL_DIV1
 #define CCLK_DIV2 CSEL_DIV2
 #define CCLK_DIV4 CSEL_DIV4
 #define CCLK_DIV8 CSEL_DIV8
 #define SET_SSEL(x)	((x) & 0xF)	/* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
 #define SCLK_DIV(x)	(x)		/* SCLK = VCO / x */
 /* PLL_STAT Masks */
 #define ACTIVE_PLLENABLED	0x0001	/* Processor In Active Mode With PLL Enabled */
 #define FULL_ON			0x0002	/* Processor In Full On Mode */
 #define ACTIVE_PLLDISABLED	0x0004	/* Processor In Active Mode With PLL Disabled */
 #define PLL_LOCKED		0x0020	/* PLL_LOCKCNT Has Been Reached */
 #define RTCWS			0x0400	/* RTC/Reset Wake-Up Status */
 #define CANWS			0x0800	/* CAN Wake-Up Status */
 #define USBWS			0x2000	/* USB Wake-Up Status */
 #define KPADWS			0x4000	/* Keypad Wake-Up Status */
 #define ROTWS			0x8000	/* Rotary Wake-Up Status */
 #define GPWS			0x1000	/* General-Purpose Wake-Up Status */
 /* VR_CTL Masks */
 #if defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
 #define FREQ			0x3000	/* Switching Oscillator Frequency For Regulator */
 #define FREQ_1000		0x3000	/* Switching Frequency Is 1 MHz */
 #else
 #define FREQ			0x0003	/* Switching Oscillator Frequency For Regulator */
 #define FREQ_333		0x0001	/* Switching Frequency Is 333 kHz */
 #define FREQ_667		0x0002	/* Switching Frequency Is 667 kHz */
 #define FREQ_1000		0x0003	/* Switching Frequency Is 1 MHz */
 #endif
 #define HIBERNATE		0x0000	/* Powerdown/Bypass On-Board Regulation */
 #define GAIN			0x000C	/* Voltage Level Gain */
 #define GAIN_5			0x0000	/* GAIN = 5 */
 #define GAIN_10			0x0004	/* GAIN = 1 */
 #define GAIN_20			0x0008	/* GAIN = 2 */
 #define GAIN_50			0x000C	/* GAIN = 5 */
 #define VLEV			0x00F0	/* Internal Voltage Level */
 #ifdef __ADSPBF52x__
 #define VLEV_085 		0x0040	/* VLEV = 0.85 V (-5% - +10% Accuracy) */
 #define VLEV_090		0x0050	/* VLEV = 0.90 V (-5% - +10% Accuracy) */
 #define VLEV_095		0x0060	/* VLEV = 0.95 V (-5% - +10% Accuracy) */
 #define VLEV_100		0x0070	/* VLEV = 1.00 V (-5% - +10% Accuracy) */
 #define VLEV_105		0x0080	/* VLEV = 1.05 V (-5% - +10% Accuracy) */
 #define VLEV_110		0x0090	/* VLEV = 1.10 V (-5% - +10% Accuracy) */
 #define VLEV_115		0x00A0	/* VLEV = 1.15 V (-5% - +10% Accuracy) */
 #define VLEV_120		0x00B0	/* VLEV = 1.20 V (-5% - +10% Accuracy) */
 #else
 #define VLEV_085 		0x0060	/* VLEV = 0.85 V (-5% - +10% Accuracy) */
 #define VLEV_090		0x0070	/* VLEV = 0.90 V (-5% - +10% Accuracy) */
 #define VLEV_095		0x0080	/* VLEV = 0.95 V (-5% - +10% Accuracy) */
 #define VLEV_100		0x0090	/* VLEV = 1.00 V (-5% - +10% Accuracy) */
 #define VLEV_105		0x00A0	/* VLEV = 1.05 V (-5% - +10% Accuracy) */
 #define VLEV_110		0x00B0	/* VLEV = 1.10 V (-5% - +10% Accuracy) */
 #define VLEV_115		0x00C0	/* VLEV = 1.15 V (-5% - +10% Accuracy) */
 #define VLEV_120		0x00D0	/* VLEV = 1.20 V (-5% - +10% Accuracy) */
 #define VLEV_125		0x00E0	/* VLEV = 1.25 V (-5% - +10% Accuracy) */
 #define VLEV_130		0x00F0	/* VLEV = 1.30 V (-5% - +10% Accuracy) */
 #endif
 #define WAKE			0x0100	/* Enable RTC/Reset Wakeup From Hibernate */
 #define CANWE			0x0200	/* Enable CAN Wakeup From Hibernate */
 #define PHYWE			0x0400	/* Enable PHY Wakeup From Hibernate */
 #define GPWE			0x0400	/* General-Purpose Wake-Up Enable */
 #define MXVRWE			0x0400	/* Enable MXVR Wakeup From Hibernate */
 #define KPADWE			0x1000	/* Keypad Wake-Up Enable */
 #define ROTWE			0x2000	/* Rotary Wake-Up Enable */
 #define CLKBUFOE		0x4000	/* CLKIN Buffer Output Enable */
 #define SCKELOW			0x8000	/* Do Not Drive SCKE High During Reset After Hibernate */
 #if defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
 #define USBWE			0x0200	/* Enable USB Wakeup From Hibernate */
 #else
 #define USBWE			0x0800	/* Enable USB Wakeup From Hibernate */
 #endif
 #ifndef __ASSEMBLY__
 void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
@ -54,6 +156,5 @@ struct bfin_dpmc_platform_data {
 	w[P0 + (x - PLL_CTL)] = R0;\
 #endif
 #endif	/* __KERNEL__ */
 #endif	/*_BLACKFIN_DPMC_H_*/
--- a/arch/blackfin/include/asm/gpio.h
+++ b/arch/blackfin/include/asm/gpio.h
@ -159,6 +159,11 @@ struct gpio_port_t {
 };
 #endif
 #ifdef BFIN_SPECIAL_GPIO_BANKS
 void bfin_special_gpio_free(unsigned gpio);
 int bfin_special_gpio_request(unsigned gpio, const char *label);
 #endif
 #ifdef CONFIG_PM
 unsigned int bfin_pm_standby_setup(void);
--- a/arch/blackfin/include/asm/gptimers.h
+++ b/arch/blackfin/include/asm/gptimers.h
@ -172,25 +172,25 @@
 /* The actual gptimer API */
-void     set_gptimer_pwidth(int timer_id, uint32_t width);
+void     set_gptimer_pwidth(unsigned int timer_id, uint32_t width);
-uint32_t get_gptimer_pwidth(int timer_id);
+uint32_t get_gptimer_pwidth(unsigned int timer_id);
-void     set_gptimer_period(int timer_id, uint32_t period);
+void     set_gptimer_period(unsigned int timer_id, uint32_t period);
-uint32_t get_gptimer_period(int timer_id);
+uint32_t get_gptimer_period(unsigned int timer_id);
-uint32_t get_gptimer_count(int timer_id);
+uint32_t get_gptimer_count(unsigned int timer_id);
-int      get_gptimer_intr(int timer_id);
+int      get_gptimer_intr(unsigned int timer_id);
-void     clear_gptimer_intr(int timer_id);
+void     clear_gptimer_intr(unsigned int timer_id);
-int      get_gptimer_over(int timer_id);
+int      get_gptimer_over(unsigned int timer_id);
-void     clear_gptimer_over(int timer_id);
+void     clear_gptimer_over(unsigned int timer_id);
-void     set_gptimer_config(int timer_id, uint16_t config);
+void     set_gptimer_config(unsigned int timer_id, uint16_t config);
-uint16_t get_gptimer_config(int timer_id);
+uint16_t get_gptimer_config(unsigned int timer_id);
-int      get_gptimer_run(int timer_id);
+int      get_gptimer_run(unsigned int timer_id);
-void     set_gptimer_pulse_hi(int timer_id);
+void     set_gptimer_pulse_hi(unsigned int timer_id);
-void     clear_gptimer_pulse_hi(int timer_id);
+void     clear_gptimer_pulse_hi(unsigned int timer_id);
 void     enable_gptimers(uint16_t mask);
 void     disable_gptimers(uint16_t mask);
 void     disable_gptimers_sync(uint16_t mask);
 uint16_t get_enabled_gptimers(void);
-uint32_t get_gptimer_status(int group);
+uint32_t get_gptimer_status(unsigned int group);
-void     set_gptimer_status(int group, uint32_t value);
+void     set_gptimer_status(unsigned int group, uint32_t value);
 #endif
--- a/arch/blackfin/include/asm/io.h
+++ b/arch/blackfin/include/asm/io.h
@ -31,12 +31,14 @@ static inline unsigned char readb(const volatile void __iomem *addr)
 	unsigned int val;
 	int tmp;
-	__asm__ __volatile__ ("cli %1;\n\t"
+	__asm__ __volatile__ (
-			"NOP; NOP; SSYNC;\n\t"
+		"cli %1;"
-			"%0 = b [%2] (z);\n\t"
+		"NOP; NOP; SSYNC;"
-			"sti %1;\n\t"
+		"%0 = b [%2] (z);"
-			: "=d"(val), "=d"(tmp): "a"(addr)
+		"sti %1;"
-			);
+		: "=d"(val), "=d"(tmp)
 		: "a"(addr)
 	);
 	return (unsigned char) val;
 }
@ -46,12 +48,14 @@ static inline unsigned short readw(const volatile void __iomem *addr)
 	unsigned int val;
 	int tmp;
-	__asm__ __volatile__ ("cli %1;\n\t"
+	__asm__ __volatile__ (
-			"NOP; NOP; SSYNC;\n\t"
+		"cli %1;"
-			"%0 = w [%2] (z);\n\t"
+		"NOP; NOP; SSYNC;"
-			"sti %1;\n\t"
+		"%0 = w [%2] (z);"
-		      	: "=d"(val), "=d"(tmp): "a"(addr)
+		"sti %1;"
-			);
+		: "=d"(val), "=d"(tmp)
 		: "a"(addr)
 	);
 	return (unsigned short) val;
 }
@ -61,20 +65,23 @@ static inline unsigned int readl(const volatile void __iomem *addr)
 	unsigned int val;
 	int tmp;
-	__asm__ __volatile__ ("cli %1;\n\t"
+	__asm__ __volatile__ (
-			"NOP; NOP; SSYNC;\n\t"
+		"cli %1;"
-			"%0 = [%2];\n\t"
+		"NOP; NOP; SSYNC;"
-			"sti %1;\n\t"
+		"%0 = [%2];"
-		      	: "=d"(val), "=d"(tmp): "a"(addr)
+		"sti %1;"
-			);
+		: "=d"(val), "=d"(tmp)
 		: "a"(addr)
 	);
 	return val;
 }
 #endif /*  __ASSEMBLY__ */
-#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
+#define writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b))
-#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
+#define writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b))
-#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
+#define writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b))
 #define __raw_readb readb
 #define __raw_readw readw
@ -82,9 +89,9 @@ static inline unsigned int readl(const volatile void __iomem *addr)
 #define __raw_writeb writeb
 #define __raw_writew writew
 #define __raw_writel writel
-#define memset_io(a,b,c)	memset((void *)(a),(b),(c))
+#define memset_io(a, b, c)	memset((void *)(a), (b), (c))
-#define memcpy_fromio(a,b,c)	memcpy((a),(void *)(b),(c))
+#define memcpy_fromio(a, b, c)	memcpy((a), (void *)(b), (c))
-#define memcpy_toio(a,b,c)	memcpy((void *)(a),(b),(c))
+#define memcpy_toio(a, b, c)	memcpy((void *)(a), (b), (c))
 /* Convert "I/O port addresses" to actual addresses.  i.e. ugly casts. */
 #define __io(port) ((void *)(unsigned long)(port))
@ -92,30 +99,30 @@ static inline unsigned int readl(const volatile void __iomem *addr)
 #define inb(port)    readb(__io(port))
 #define inw(port)    readw(__io(port))
 #define inl(port)    readl(__io(port))
-#define outb(x,port) writeb(x,__io(port))
+#define outb(x, port) writeb(x, __io(port))
-#define outw(x,port) writew(x,__io(port))
+#define outw(x, port) writew(x, __io(port))
-#define outl(x,port) writel(x,__io(port))
+#define outl(x, port) writel(x, __io(port))
 #define inb_p(port)    inb(__io(port))
 #define inw_p(port)    inw(__io(port))
 #define inl_p(port)    inl(__io(port))
-#define outb_p(x,port) outb(x,__io(port))
+#define outb_p(x, port) outb(x, __io(port))
-#define outw_p(x,port) outw(x,__io(port))
+#define outw_p(x, port) outw(x, __io(port))
-#define outl_p(x,port) outl(x,__io(port))
+#define outl_p(x, port) outl(x, __io(port))
-#define ioread8_rep(a,d,c)	readsb(a,d,c)
+#define ioread8_rep(a, d, c)	readsb(a, d, c)
-#define ioread16_rep(a,d,c)	readsw(a,d,c)
+#define ioread16_rep(a, d, c)	readsw(a, d, c)
-#define ioread32_rep(a,d,c)	readsl(a,d,c)
+#define ioread32_rep(a, d, c)	readsl(a, d, c)
-#define iowrite8_rep(a,s,c)	writesb(a,s,c)
+#define iowrite8_rep(a, s, c)	writesb(a, s, c)
-#define iowrite16_rep(a,s,c)	writesw(a,s,c)
+#define iowrite16_rep(a, s, c)	writesw(a, s, c)
-#define iowrite32_rep(a,s,c)	writesl(a,s,c)
+#define iowrite32_rep(a, s, c)	writesl(a, s, c)
-#define ioread8(X)			readb(X)
+#define ioread8(x)			readb(x)
-#define ioread16(X)			readw(X)
+#define ioread16(x)			readw(x)
-#define ioread32(X)			readl(X)
+#define ioread32(x)			readl(x)
-#define iowrite8(val,X)			writeb(val,X)
+#define iowrite8(val, x)		writeb(val, x)
-#define iowrite16(val,X)		writew(val,X)
+#define iowrite16(val, x)		writew(val, x)
-#define iowrite32(val,X)		writel(val,X)
+#define iowrite32(val, x)		writel(val, x)
 #define mmiowb() wmb()
--- a/arch/blackfin/include/asm/ipipe.h
+++ b/arch/blackfin/include/asm/ipipe.h
@ -35,9 +35,9 @@
 #include <asm/atomic.h>
 #include <asm/traps.h>
-#define IPIPE_ARCH_STRING     "1.11-00"
+#define IPIPE_ARCH_STRING     "1.12-00"
 #define IPIPE_MAJOR_NUMBER    1
-#define IPIPE_MINOR_NUMBER    11
+#define IPIPE_MINOR_NUMBER    12
 #define IPIPE_PATCH_NUMBER    0
 #ifdef CONFIG_SMP
@ -124,16 +124,6 @@ static inline int __ipipe_check_tickdev(const char *devname)
 	return 1;
 }
 static inline void __ipipe_lock_root(void)
 {
 	set_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status));
 }
 static inline void __ipipe_unlock_root(void)
 {
 	clear_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status));
 }
 void __ipipe_enable_pipeline(void);
 #define __ipipe_hook_critical_ipi(ipd) do { } while (0)
--- a/arch/blackfin/include/asm/ipipe_base.h
+++ b/arch/blackfin/include/asm/ipipe_base.h
@ -51,23 +51,15 @@
 extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */
-#define __ipipe_stall_root()						\
+void __ipipe_stall_root(void);
 	do {								\
 		volatile unsigned long *p = &__ipipe_root_status;	\
 		set_bit(0, p);						\
 	} while (0)
-#define __ipipe_test_and_stall_root()					\
+unsigned long __ipipe_test_and_stall_root(void);
 	({								\
 		volatile unsigned long *p = &__ipipe_root_status;	\
 		test_and_set_bit(0, p);					\
 	})
-#define __ipipe_test_root()					\
+unsigned long __ipipe_test_root(void);
-	({							\
+
-		const unsigned long *p = &__ipipe_root_status;	\
+void __ipipe_lock_root(void);
-		test_bit(0, p);					\
+
-	})
+void __ipipe_unlock_root(void);
 #endif /* !__ASSEMBLY__ */
--- a/arch/blackfin/include/asm/irqflags.h
+++ b/arch/blackfin/include/asm/irqflags.h
@ -33,6 +33,7 @@ static inline unsigned long bfin_cli(void)
 #ifdef CONFIG_IPIPE
 #include <linux/compiler.h>
 #include <linux/ipipe_base.h>
 #include <linux/ipipe_trace.h>
@ -49,12 +50,12 @@ static inline unsigned long bfin_cli(void)
 		barrier();				\
 	} while (0)
-static inline void raw_local_irq_enable(void)
+#define raw_local_irq_enable()				\
-{
+	do {						\
-	barrier();
+		barrier();				\
-	ipipe_check_context(ipipe_root_domain);
+		ipipe_check_context(ipipe_root_domain);	\
-	__ipipe_unstall_root();
+		__ipipe_unstall_root();			\
-}
+	} while (0)
 #define raw_local_save_flags_ptr(x)					\
 	do {								\
--- a/arch/blackfin/include/asm/kgdb.h
+++ b/arch/blackfin/include/asm/kgdb.h
@ -10,9 +10,6 @@
 #include <linux/ptrace.h>
 /* gdb locks */
 #define KGDB_MAX_NO_CPUS 8
 /*
 * BUFMAX defines the maximum number of characters in inbound/outbound buffers.
 * At least NUMREGBYTES*2 are needed for register packets.
--- a/arch/blackfin/include/asm/mem_init.h
+++ b/arch/blackfin/include/asm/mem_init.h
@ -295,156 +295,3 @@
 #else
 #define PLL_BYPASS       0
 #endif
 /***************************************Currently Not Being Used *********************************/
 #if defined(CONFIG_FLASH_SPEED_BWAT) && \
 defined(CONFIG_FLASH_SPEED_BRAT) && \
 defined(CONFIG_FLASH_SPEED_BHT) && \
 defined(CONFIG_FLASH_SPEED_BST) && \
 defined(CONFIG_FLASH_SPEED_BTT)
 #define flash_EBIU_AMBCTL_WAT  ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
 #define flash_EBIU_AMBCTL_RAT  ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
 #define flash_EBIU_AMBCTL_HT   ((CONFIG_FLASH_SPEED_BHT  * 4) / (4000000000 / CONFIG_SCLK_HZ))
 #define flash_EBIU_AMBCTL_ST   ((CONFIG_FLASH_SPEED_BST  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
 #define flash_EBIU_AMBCTL_TT   ((CONFIG_FLASH_SPEED_BTT  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
 #if (flash_EBIU_AMBCTL_TT > 3)
 #define flash_EBIU_AMBCTL0_TT   B0TT_4
 #endif
 #if (flash_EBIU_AMBCTL_TT == 3)
 #define flash_EBIU_AMBCTL0_TT   B0TT_3
 #endif
 #if (flash_EBIU_AMBCTL_TT == 2)
 #define flash_EBIU_AMBCTL0_TT   B0TT_2
 #endif
 #if (flash_EBIU_AMBCTL_TT < 2)
 #define flash_EBIU_AMBCTL0_TT   B0TT_1
 #endif
 #if (flash_EBIU_AMBCTL_ST > 3)
 #define flash_EBIU_AMBCTL0_ST   B0ST_4
 #endif
 #if (flash_EBIU_AMBCTL_ST == 3)
 #define flash_EBIU_AMBCTL0_ST   B0ST_3
 #endif
 #if (flash_EBIU_AMBCTL_ST == 2)
 #define flash_EBIU_AMBCTL0_ST   B0ST_2
 #endif
 #if (flash_EBIU_AMBCTL_ST < 2)
 #define flash_EBIU_AMBCTL0_ST   B0ST_1
 #endif
 #if (flash_EBIU_AMBCTL_HT > 2)
 #define flash_EBIU_AMBCTL0_HT   B0HT_3
 #endif
 #if (flash_EBIU_AMBCTL_HT == 2)
 #define flash_EBIU_AMBCTL0_HT   B0HT_2
 #endif
 #if (flash_EBIU_AMBCTL_HT == 1)
 #define flash_EBIU_AMBCTL0_HT   B0HT_1
 #endif
 #if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
 #define flash_EBIU_AMBCTL0_HT   B0HT_0
 #endif
 #if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
 #define flash_EBIU_AMBCTL0_HT   B0HT_1
 #endif
 #if (flash_EBIU_AMBCTL_WAT > 14)
 #define flash_EBIU_AMBCTL0_WAT  B0WAT_15
 #endif
 #if (flash_EBIU_AMBCTL_WAT == 14)
 #define flash_EBIU_AMBCTL0_WAT  B0WAT_14
 #endif
 #if (flash_EBIU_AMBCTL_WAT == 13)
 #define flash_EBIU_AMBCTL0_WAT  B0WAT_13
 #endif
 #if (flash_EBIU_AMBCTL_WAT == 12)
 #define flash_EBIU_AMBCTL0_WAT  B0WAT_12
 #endif
 #if (flash_EBIU_AMBCTL_WAT == 11)
 #define flash_EBIU_AMBCTL0_WAT  B0WAT_11
 #endif
 #if (flash_EBIU_AMBCTL_WAT == 10)
 #define flash_EBIU_AMBCTL0_WAT  B0WAT_10
 #endif
 #if (flash_EBIU_AMBCTL_WAT == 9)
 #define flash_EBIU_AMBCTL0_WAT  B0WAT_9
 #endif
 #if (flash_EBIU_AMBCTL_WAT == 8)
 #define flash_EBIU_AMBCTL0_WAT  B0WAT_8
 #endif
 #if (flash_EBIU_AMBCTL_WAT == 7)
 #define flash_EBIU_AMBCTL0_WAT  B0WAT_7
 #endif
 #if (flash_EBIU_AMBCTL_WAT == 6)
 #define flash_EBIU_AMBCTL0_WAT  B0WAT_6
 #endif
 #if (flash_EBIU_AMBCTL_WAT == 5)
 #define flash_EBIU_AMBCTL0_WAT  B0WAT_5
 #endif
 #if (flash_EBIU_AMBCTL_WAT == 4)
 #define flash_EBIU_AMBCTL0_WAT  B0WAT_4
 #endif
 #if (flash_EBIU_AMBCTL_WAT == 3)
 #define flash_EBIU_AMBCTL0_WAT  B0WAT_3
 #endif
 #if (flash_EBIU_AMBCTL_WAT == 2)
 #define flash_EBIU_AMBCTL0_WAT  B0WAT_2
 #endif
 #if (flash_EBIU_AMBCTL_WAT == 1)
 #define flash_EBIU_AMBCTL0_WAT  B0WAT_1
 #endif
 #if (flash_EBIU_AMBCTL_RAT > 14)
 #define flash_EBIU_AMBCTL0_RAT  B0RAT_15
 #endif
 #if (flash_EBIU_AMBCTL_RAT == 14)
 #define flash_EBIU_AMBCTL0_RAT  B0RAT_14
 #endif
 #if (flash_EBIU_AMBCTL_RAT == 13)
 #define flash_EBIU_AMBCTL0_RAT  B0RAT_13
 #endif
 #if (flash_EBIU_AMBCTL_RAT == 12)
 #define flash_EBIU_AMBCTL0_RAT  B0RAT_12
 #endif
 #if (flash_EBIU_AMBCTL_RAT == 11)
 #define flash_EBIU_AMBCTL0_RAT  B0RAT_11
 #endif
 #if (flash_EBIU_AMBCTL_RAT == 10)
 #define flash_EBIU_AMBCTL0_RAT  B0RAT_10
 #endif
 #if (flash_EBIU_AMBCTL_RAT == 9)
 #define flash_EBIU_AMBCTL0_RAT  B0RAT_9
 #endif
 #if (flash_EBIU_AMBCTL_RAT == 8)
 #define flash_EBIU_AMBCTL0_RAT  B0RAT_8
 #endif
 #if (flash_EBIU_AMBCTL_RAT == 7)
 #define flash_EBIU_AMBCTL0_RAT  B0RAT_7
 #endif
 #if (flash_EBIU_AMBCTL_RAT == 6)
 #define flash_EBIU_AMBCTL0_RAT  B0RAT_6
 #endif
 #if (flash_EBIU_AMBCTL_RAT == 5)
 #define flash_EBIU_AMBCTL0_RAT  B0RAT_5
 #endif
 #if (flash_EBIU_AMBCTL_RAT == 4)
 #define flash_EBIU_AMBCTL0_RAT  B0RAT_4
 #endif
 #if (flash_EBIU_AMBCTL_RAT == 3)
 #define flash_EBIU_AMBCTL0_RAT  B0RAT_3
 #endif
 #if (flash_EBIU_AMBCTL_RAT == 2)
 #define flash_EBIU_AMBCTL0_RAT  B0RAT_2
 #endif
 #if (flash_EBIU_AMBCTL_RAT == 1)
 #define flash_EBIU_AMBCTL0_RAT  B0RAT_1
 #endif
 #define flash_EBIU_AMBCTL0  \
 	(flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
 	 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
 #endif
--- a/arch/blackfin/include/asm/mmu_context.h
+++ b/arch/blackfin/include/asm/mmu_context.h
@ -66,8 +66,8 @@ activate_l1stack(struct mm_struct *mm, unsigned long sp_base)
 #define activate_mm(prev, next) switch_mm(prev, next, NULL)
-static inline void switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm,
+static inline void __switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm,
-			     struct task_struct *tsk)
+			       struct task_struct *tsk)
 {
 #ifdef CONFIG_MPU
 	unsigned int cpu = smp_processor_id();
@ -95,7 +95,24 @@ static inline void switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_m
 #endif
 }
 #ifdef CONFIG_IPIPE
 #define lock_mm_switch(flags)	local_irq_save_hw_cond(flags)
 #define unlock_mm_switch(flags)	local_irq_restore_hw_cond(flags)
 #else
 #define lock_mm_switch(flags)	do { (void)(flags); } while (0)
 #define unlock_mm_switch(flags)	do { (void)(flags); } while (0)
 #endif /* CONFIG_IPIPE */
 #ifdef CONFIG_MPU
 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
 			     struct task_struct *tsk)
 {
 	unsigned long flags;
 	lock_mm_switch(flags);
 	__switch_mm(prev, next, tsk);
 	unlock_mm_switch(flags);
 }
 static inline void protect_page(struct mm_struct *mm, unsigned long addr,
 				unsigned long flags)
 {
@ -128,6 +145,12 @@ static inline void update_protections(struct mm_struct *mm)
 		set_mask_dcplbs(mm->context.page_rwx_mask, cpu);
 	}
 }
 #else /* !CONFIG_MPU */
 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
 			     struct task_struct *tsk)
 {
 	__switch_mm(prev, next, tsk);
 }
 #endif
 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
@ -173,4 +196,10 @@ static inline void destroy_context(struct mm_struct *mm)
 #endif
 }
 #define ipipe_mm_switch_protect(flags)		\
 	local_irq_save_hw_cond(flags)
 #define ipipe_mm_switch_unprotect(flags)	\
 	local_irq_restore_hw_cond(flags)
 #endif
--- a/arch/blackfin/include/asm/pci.h
+++ b/arch/blackfin/include/asm/pci.h
@ -4,145 +4,19 @@
 #define _ASM_BFIN_PCI_H
 #include <asm/scatterlist.h>
 #include <asm-generic/pci-dma-compat.h>
 #include <asm-generic/pci.h>
 /*
 *
 * Written by Wout Klaren.
 */
 /* Added by Chang Junxiao */
 #define PCIBIOS_MIN_IO 0x00001000
 #define PCIBIOS_MIN_MEM 0x10000000
 #define PCI_DMA_BUS_IS_PHYS       (1)
 struct pci_ops;
 /*
 * Structure with hardware dependent information and functions of the
 * PCI bus.
 */
 struct pci_bus_info {
 	/*
 	 * Resources of the PCI bus.
 	 */
 	struct resource mem_space;
 	struct resource io_space;
 	/*
 	 * System dependent functions.
 	 */
 	struct pci_ops *bfin_pci_ops;
 	void (*fixup) (int pci_modify);
 	void (*conf_device) (unsigned char bus, unsigned char device_fn);
 };
 #define pcibios_assign_all_busses()	0
 static inline void pcibios_set_master(struct pci_dev *dev)
 {
 	/* No special bus mastering setup handling */
 }
 static inline void pcibios_penalize_isa_irq(int irq)
 {
 	/* We don't do dynamic PCI IRQ allocation */
 }
 static inline dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr,
 					size_t size, int direction)
 {
 	if (direction == PCI_DMA_NONE)
 		BUG();
 	 /* return virt_to_bus(ptr); */
 	return (dma_addr_t) ptr;
 }
 /* Unmap a single streaming mode DMA translation.  The dma_addr and size
 * must match what was provided for in a previous pci_map_single call.  All
 * other usages are undefined.
 *
 * After this call, reads by the cpu to the buffer are guarenteed to see
 * whatever the device wrote there.
 */
 static inline void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr,
 				    size_t size, int direction)
 {
 	if (direction == PCI_DMA_NONE)
 		BUG();
 	/* Nothing to do */
 }
 /* Map a set of buffers described by scatterlist in streaming
 * mode for DMA.  This is the scather-gather version of the
 * above pci_map_single interface.  Here the scatter gather list
 * elements are each tagged with the appropriate dma address
 * and length.  They are obtained via sg_dma_{address,length}(SG).
 *
 * NOTE: An implementation may be able to use a smaller number of
 *       DMA address/length pairs than there are SG table elements.
 *       (for example via virtual mapping capabilities)
 *       The routine returns the number of addr/length pairs actually
 *       used, at most nents.
 *
 * Device ownership issues as mentioned above for pci_map_single are
 * the same here.
 */
 static inline int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg,
 			     int nents, int direction)
 {
 	if (direction == PCI_DMA_NONE)
 		BUG();
 	return nents;
 }
 /* Unmap a set of streaming mode DMA translations.
 * Again, cpu read rules concerning calls here are the same as for
 * pci_unmap_single() above.
 */
 static inline void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg,
 				int nents, int direction)
 {
 	if (direction == PCI_DMA_NONE)
 		BUG();
 	/* Nothing to do */
 }
 /* Make physical memory consistent for a single
 * streaming mode DMA translation after a transfer.
 *
 * If you perform a pci_map_single() but wish to interrogate the
 * buffer using the cpu, yet do not wish to teardown the PCI dma
 * mapping, you must call this function before doing so.  At the
 * next point you give the PCI dma address back to the card, the
 * device again owns the buffer.
 */
 static inline void pci_dma_sync_single(struct pci_dev *hwdev,
 				       dma_addr_t dma_handle, size_t size,
 				       int direction)
 {
 	if (direction == PCI_DMA_NONE)
 		BUG();
 	/* Nothing to do */
 }
 /* Make physical memory consistent for a set of streaming
 * mode DMA translations after a transfer.
 *
 * The same as pci_dma_sync_single but for a scatter-gather list,
 * same rules and usage.
 */
 static inline void pci_dma_sync_sg(struct pci_dev *hwdev,
 				   struct scatterlist *sg, int nelems,
 				   int direction)
 {
 	if (direction == PCI_DMA_NONE)
 		BUG();
 	/* Nothing to do */
 }
 #endif				/* _ASM_BFIN_PCI_H */
--- a/arch/blackfin/include/asm/ptrace.h
+++ b/arch/blackfin/include/asm/ptrace.h
@ -89,9 +89,9 @@ struct pt_regs {
 #define PTRACE_GETREGS            12
 #define PTRACE_SETREGS            13	/* ptrace signal  */
-#define PTRACE_GETFDPIC           31
+#define PTRACE_GETFDPIC           31	/* get the ELF fdpic loadmap address */
-#define PTRACE_GETFDPIC_EXEC      0
+#define PTRACE_GETFDPIC_EXEC       0	/* [addr] request the executable loadmap */
-#define PTRACE_GETFDPIC_INTERP    1
+#define PTRACE_GETFDPIC_INTERP     1	/* [addr] request the interpreter loadmap */
 #define PS_S  (0x0002)
--- a/arch/blackfin/include/asm/sections.h
+++ b/arch/blackfin/include/asm/sections.h
@ -13,10 +13,18 @@ extern unsigned long memory_mtd_start, memory_mtd_end, mtd_size;
 extern unsigned long _ramstart, _ramend, _rambase;
 extern unsigned long memory_start, memory_end, physical_mem_end;
-extern char _stext_l1[], _etext_l1[], _sdata_l1[], _edata_l1[], _sbss_l1[],
+/*
-	_ebss_l1[], _l1_lma_start[], _sdata_b_l1[], _sbss_b_l1[], _ebss_b_l1[],
+ * The weak markings on the lengths might seem weird, but this is required
-	_stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[], _sbss_l2[],
+ * in order to make gcc accept the fact that these may actually have a value
-	_ebss_l2[], _l2_lma_start[];
+ * of 0 (since they aren't actually addresses, but sizes of sections).
 */
 extern char _stext_l1[], _etext_l1[], _text_l1_lma[], __weak _text_l1_len[];
 extern char _sdata_l1[], _edata_l1[], _sbss_l1[], _ebss_l1[],
 	_data_l1_lma[], __weak _data_l1_len[];
 extern char _sdata_b_l1[], _edata_b_l1[], _sbss_b_l1[], _ebss_b_l1[],
 	_data_b_l1_lma[], __weak _data_b_l1_len[];
 extern char _stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[],
 	_sbss_l2[], _ebss_l2[], _l2_lma[], __weak _l2_len[];
 #include <asm/mem_map.h>
--- a/arch/blackfin/include/asm/thread_info.h
+++ b/arch/blackfin/include/asm/thread_info.h
@ -103,11 +103,13 @@ static inline struct thread_info *current_thread_info(void)
 #define TIF_RESTORE_SIGMASK	5	/* restore signal mask in do_signal() */
 #define TIF_FREEZE              6       /* is freezing for suspend */
 #define TIF_IRQ_SYNC            7       /* sync pipeline stage */
 #define TIF_NOTIFY_RESUME       8       /* callback before returning to user */
 /* as above, but as bit values */
 #define _TIF_SYSCALL_TRACE	(1<<TIF_SYSCALL_TRACE)
 #define _TIF_SIGPENDING		(1<<TIF_SIGPENDING)
 #define _TIF_NEED_RESCHED	(1<<TIF_NEED_RESCHED)
 #define _TIF_NOTIFY_RESUME	(1<<TIF_NOTIFY_RESUME)
 #define _TIF_POLLING_NRFLAG	(1<<TIF_POLLING_NRFLAG)
 #define _TIF_RESTORE_SIGMASK	(1<<TIF_RESTORE_SIGMASK)
 #define _TIF_FREEZE             (1<<TIF_FREEZE)
--- a/arch/blackfin/include/asm/trace.h
+++ b/arch/blackfin/include/asm/trace.h
@ -28,6 +28,8 @@ extern unsigned long software_trace_buff[];
 #ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
 #define trace_buffer_init() bfin_write_TBUFCTL(BFIN_TRACE_INIT)
 #define trace_buffer_save(x) \
 	do { \
 		(x) = bfin_read_TBUFCTL(); \
--- a/arch/blackfin/include/asm/uaccess.h
+++ b/arch/blackfin/include/asm/uaccess.h
@ -17,9 +17,7 @@
 #include <linux/string.h>
 #include <asm/segment.h>
-#ifdef CONFIG_ACCESS_CHECK
+#include <asm/sections.h>
 # include <asm/bfin-global.h>
 #endif
 #define get_ds()        (KERNEL_DS)
 #define get_fs()        (current_thread_info()->addr_limit)
--- a/arch/blackfin/include/asm/unistd.h
+++ b/arch/blackfin/include/asm/unistd.h
@ -388,8 +388,9 @@
 #define __NR_pwritev		367
 #define __NR_rt_tgsigqueueinfo	368
 #define __NR_perf_event_open	369
 #define __NR_recvmmsg		370
-#define __NR_syscall		370
+#define __NR_syscall		371
 #define NR_syscalls		__NR_syscall
 /* Old optional stuff no one actually uses */
--- a/arch/blackfin/kernel/bfin_dma_5xx.c
+++ b/arch/blackfin/kernel/bfin_dma_5xx.c
@ -37,9 +37,8 @@ static int __init blackfin_dma_init(void)
 	printk(KERN_INFO "Blackfin DMA Controller\n");
 	for (i = 0; i < MAX_DMA_CHANNELS; i++) {
-		dma_ch[i].chan_status = DMA_CHANNEL_FREE;
+		atomic_set(&dma_ch[i].chan_status, 0);
 		dma_ch[i].regs = dma_io_base_addr[i];
 		mutex_init(&(dma_ch[i].dmalock));
 	}
 	/* Mark MEMDMA Channel 0 as requested since we're using it internally */
 	request_dma(CH_MEM_STREAM0_DEST, "Blackfin dma_memcpy");
@ -60,7 +59,7 @@ static int proc_dma_show(struct seq_file *m, void *v)
 	int i;
 	for (i = 0; i < MAX_DMA_CHANNELS; ++i)
-		if (dma_ch[i].chan_status != DMA_CHANNEL_FREE)
+		if (dma_channel_active(i))
 			seq_printf(m, "%2d: %s\n", i, dma_ch[i].device_id);
 	return 0;
@ -107,20 +106,11 @@ int request_dma(unsigned int channel, const char *device_id)
 	}
 #endif
-	mutex_lock(&(dma_ch[channel].dmalock));
+	if (atomic_cmpxchg(&dma_ch[channel].chan_status, 0, 1)) {
 	if ((dma_ch[channel].chan_status == DMA_CHANNEL_REQUESTED)
 	    || (dma_ch[channel].chan_status == DMA_CHANNEL_ENABLED)) {
 		mutex_unlock(&(dma_ch[channel].dmalock));
 		pr_debug("DMA CHANNEL IN USE  \n");
 		return -EBUSY;
 	} else {
 		dma_ch[channel].chan_status = DMA_CHANNEL_REQUESTED;
 		pr_debug("DMA CHANNEL IS ALLOCATED  \n");
 	}
 	mutex_unlock(&(dma_ch[channel].dmalock));
 #ifdef CONFIG_BF54x
 	if (channel >= CH_UART2_RX && channel <= CH_UART3_TX) {
 		unsigned int per_map;
@ -148,21 +138,20 @@ EXPORT_SYMBOL(request_dma);
 int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data)
 {
-	BUG_ON(channel >= MAX_DMA_CHANNELS ||
+	int ret;
-			dma_ch[channel].chan_status == DMA_CHANNEL_FREE);
+	unsigned int irq;
-	if (callback != NULL) {
+	BUG_ON(channel >= MAX_DMA_CHANNELS || !callback ||
-		int ret;
+			!atomic_read(&dma_ch[channel].chan_status));
 		unsigned int irq = channel2irq(channel);
-		ret = request_irq(irq, callback, IRQF_DISABLED,
+	irq = channel2irq(channel);
-			dma_ch[channel].device_id, data);
+	ret = request_irq(irq, callback, 0, dma_ch[channel].device_id, data);
-		if (ret)
+	if (ret)
-			return ret;
+		return ret;
 	dma_ch[channel].irq = irq;
 	dma_ch[channel].data = data;
 		dma_ch[channel].irq = irq;
 		dma_ch[channel].data = data;
 	}
 	return 0;
 }
 EXPORT_SYMBOL(set_dma_callback);
@ -184,7 +173,7 @@ void free_dma(unsigned int channel)
 {
 	pr_debug("freedma() : BEGIN \n");
 	BUG_ON(channel >= MAX_DMA_CHANNELS ||
-			dma_ch[channel].chan_status == DMA_CHANNEL_FREE);
+			!atomic_read(&dma_ch[channel].chan_status));
 	/* Halt the DMA */
 	disable_dma(channel);
@ -194,9 +183,7 @@ void free_dma(unsigned int channel)
 		free_irq(dma_ch[channel].irq, dma_ch[channel].data);
 	/* Clear the DMA Variable in the Channel */
-	mutex_lock(&(dma_ch[channel].dmalock));
+	atomic_set(&dma_ch[channel].chan_status, 0);
 	dma_ch[channel].chan_status = DMA_CHANNEL_FREE;
 	mutex_unlock(&(dma_ch[channel].dmalock));
 	pr_debug("freedma() : END \n");
 }
@ -210,13 +197,14 @@ int blackfin_dma_suspend(void)
 {
 	int i;
-	for (i = 0; i < MAX_DMA_SUSPEND_CHANNELS; ++i) {
+	for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
-		if (dma_ch[i].chan_status == DMA_CHANNEL_ENABLED) {
+		if (dma_ch[i].regs->cfg & DMAEN) {
 			printk(KERN_ERR "DMA Channel %d failed to suspend\n", i);
 			return -EBUSY;
 		}
-		dma_ch[i].saved_peripheral_map = dma_ch[i].regs->peripheral_map;
+		if (i < MAX_DMA_SUSPEND_CHANNELS)
 			dma_ch[i].saved_peripheral_map = dma_ch[i].regs->peripheral_map;
 	}
 	return 0;
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@ -100,6 +100,12 @@ u8 pmux_offset[][16] = {
 };
 # endif
 #elif defined(BF538_FAMILY)
 static unsigned short * const port_fer[] = {
 	(unsigned short *) PORTCIO_FER,
 	(unsigned short *) PORTDIO_FER,
 	(unsigned short *) PORTEIO_FER,
 };
 #endif
 static unsigned short reserved_gpio_map[GPIO_BANK_NUM];
@ -163,6 +169,27 @@ static int cmp_label(unsigned short ident, const char *label)
 static void port_setup(unsigned gpio, unsigned short usage)
 {
 #if defined(BF538_FAMILY)
 	/*
 	 * BF538/9 Port C,D and E are special.
 	 * Inverted PORT_FER polarity on CDE and no PORF_FER on F
 	 * Regular PORT F GPIOs are handled here, CDE are exclusively
 	 * managed by GPIOLIB
 	 */
 	if (gpio < MAX_BLACKFIN_GPIOS || gpio >= MAX_RESOURCES)
 		return;
 	gpio -= MAX_BLACKFIN_GPIOS;
 	if (usage == GPIO_USAGE)
 		*port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
 	else
 		*port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
 	SSYNC();
 	return;
 #endif
 	if (check_gpio(gpio))
 		return;
@ -762,6 +789,8 @@ int peripheral_request(unsigned short per, const char *label)
 	if (!(per & P_DEFINED))
 		return -ENODEV;
 	BUG_ON(ident >= MAX_RESOURCES);
 	local_irq_save_hw(flags);
 	/* If a pin can be muxed as either GPIO or peripheral, make
@ -979,6 +1008,76 @@ void bfin_gpio_free(unsigned gpio)
 }
 EXPORT_SYMBOL(bfin_gpio_free);
 #ifdef BFIN_SPECIAL_GPIO_BANKS
 static unsigned short reserved_special_gpio_map[gpio_bank(MAX_RESOURCES)];
 int bfin_special_gpio_request(unsigned gpio, const char *label)
 {
 	unsigned long flags;
 	local_irq_save_hw(flags);
 	/*
 	 * Allow that the identical GPIO can
 	 * be requested from the same driver twice
 	 * Do nothing and return -
 	 */
 	if (cmp_label(gpio, label) == 0) {
 		local_irq_restore_hw(flags);
 		return 0;
 	}
 	if (unlikely(reserved_special_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
 		local_irq_restore_hw(flags);
 		printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n",
 		       gpio, get_label(gpio));
 		return -EBUSY;
 	}
 	if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
 		local_irq_restore_hw(flags);
 		printk(KERN_ERR
 		       "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
 		       gpio, get_label(gpio));
 		return -EBUSY;
 	}
 	reserved_special_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio);
 	reserved_peri_map[gpio_bank(gpio)] |= gpio_bit(gpio);
 	set_label(gpio, label);
 	local_irq_restore_hw(flags);
 	port_setup(gpio, GPIO_USAGE);
 	return 0;
 }
 EXPORT_SYMBOL(bfin_special_gpio_request);
 void bfin_special_gpio_free(unsigned gpio)
 {
 	unsigned long flags;
 	might_sleep();
 	local_irq_save_hw(flags);
 	if (unlikely(!(reserved_special_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
 		gpio_error(gpio);
 		local_irq_restore_hw(flags);
 		return;
 	}
 	reserved_special_gpio_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
 	reserved_peri_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
 	set_label(gpio, "free");
 	local_irq_restore_hw(flags);
 }
 EXPORT_SYMBOL(bfin_special_gpio_free);
 #endif
 int bfin_gpio_irq_request(unsigned gpio, const char *label)
 {
 	unsigned long flags;
--- a/arch/blackfin/kernel/cplb-mpu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-mpu/cplbinit.c
@ -92,6 +92,6 @@ void __init generate_cplb_tables_cpu(unsigned int cpu)
 		icplb_tbl[cpu][i_i++].data = 0;
 }
-void generate_cplb_tables_all(void)
+void __init generate_cplb_tables_all(void)
 {
 }
--- a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
+++ b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
@ -113,11 +113,11 @@ static noinline int dcplb_miss(unsigned int cpu)
 		addr = L2_START;
 		d_data = L2_DMEMORY;
 	} else if (addr >= physical_mem_end) {
-		if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE
+		if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
-		    && (status & FAULT_USERSUPV)) {
+			addr &= ~(4 * 1024 * 1024 - 1);
 			addr &= ~0x3fffff;
 			d_data &= ~PAGE_SIZE_4KB;
 			d_data |= PAGE_SIZE_4MB;
 			d_data |= CPLB_USER_RD | CPLB_USER_WR;
 		} else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
 		    && (status & (FAULT_RW | FAULT_USERSUPV)) == FAULT_USERSUPV) {
 			addr &= ~(1 * 1024 * 1024 - 1);
@ -203,7 +203,12 @@ static noinline int icplb_miss(unsigned int cpu)
 		addr = L2_START;
 		i_data = L2_IMEMORY;
 	} else if (addr >= physical_mem_end) {
-		if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
+		if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
 			addr &= ~(4 * 1024 * 1024 - 1);
 			i_data &= ~PAGE_SIZE_4KB;
 			i_data |= PAGE_SIZE_4MB;
 			i_data |= CPLB_USER_RD;
 		} else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
 		    && (status & FAULT_USERSUPV)) {
 			addr &= ~(1 * 1024 * 1024 - 1);
 			i_data &= ~PAGE_SIZE_4KB;
--- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
@ -89,15 +89,25 @@ void __init generate_cplb_tables_cpu(unsigned int cpu)
 void __init generate_cplb_tables_all(void)
 {
 	unsigned long uncached_end;
 	int i_d, i_i;
 	i_d = 0;
 	/* Normal RAM, including MTD FS.  */
 #ifdef CONFIG_MTD_UCLINUX
-	dcplb_bounds[i_d].eaddr = memory_mtd_start + mtd_size;
+	uncached_end = memory_mtd_start + mtd_size;
 #else
-	dcplb_bounds[i_d].eaddr = memory_end;
+	uncached_end = memory_end;
 #endif
 	/*
 	 * if DMA uncached is less than 1MB, mark the 1MB chunk as uncached
 	 * so that we don't have to use 4kB pages and cause CPLB thrashing
 	 */
 	if ((DMA_UNCACHED_REGION >= 1 * 1024 * 1024) || !DMA_UNCACHED_REGION ||
 	    ((_ramend - uncached_end) >= 1 * 1024 * 1024))
 		dcplb_bounds[i_d].eaddr = uncached_end;
 	else
 		dcplb_bounds[i_d].eaddr = uncached_end & ~(1 * 1024 * 1024);
 	dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
 	/* DMA uncached region.  */
 	if (DMA_UNCACHED_REGION) {
@ -135,18 +145,15 @@ void __init generate_cplb_tables_all(void)
 	i_i = 0;
 	/* Normal RAM, including MTD FS.  */
-#ifdef CONFIG_MTD_UCLINUX
+	icplb_bounds[i_i].eaddr = uncached_end;
 	icplb_bounds[i_i].eaddr = memory_mtd_start + mtd_size;
 #else
 	icplb_bounds[i_i].eaddr = memory_end;
 #endif
 	icplb_bounds[i_i++].data = SDRAM_IGENERIC;
 	/* DMA uncached region.  */
 	if (DMA_UNCACHED_REGION) {
 		icplb_bounds[i_i].eaddr = _ramend;
 		icplb_bounds[i_i++].data = 0;
 	}
 	if (_ramend != physical_mem_end) {
 		/* DMA uncached region.  */
 		if (DMA_UNCACHED_REGION) {
 			/* Normally this hole is caught by the async below.  */
 			icplb_bounds[i_i].eaddr = _ramend;
 			icplb_bounds[i_i++].data = 0;
 		}
 		/* Reserved memory.  */
 		icplb_bounds[i_i].eaddr = physical_mem_end;
 		icplb_bounds[i_i++].data = (reserved_mem_icache_on ?
--- a/arch/blackfin/kernel/dma-mapping.c
+++ b/arch/blackfin/kernel/dma-mapping.c
@ -7,30 +7,25 @@
 */
 #include <linux/types.h>
-#include <linux/mm.h>
+#include <linux/gfp.h>
 #include <linux/string.h>
 #include <linux/bootmem.h>
 #include <linux/spinlock.h>
 #include <linux/device.h>
 #include <linux/dma-mapping.h>
 #include <linux/io.h>
 #include <linux/scatterlist.h>
 #include <asm/cacheflush.h>
 #include <asm/bfin-global.h>
 static spinlock_t dma_page_lock;
-static unsigned int *dma_page;
+static unsigned long *dma_page;
 static unsigned int dma_pages;
 static unsigned long dma_base;
 static unsigned long dma_size;
 static unsigned int dma_initialized;
-void dma_alloc_init(unsigned long start, unsigned long end)
+static void dma_alloc_init(unsigned long start, unsigned long end)
 {
 	spin_lock_init(&dma_page_lock);
 	dma_initialized = 0;
-	dma_page = (unsigned int *)__get_free_page(GFP_KERNEL);
+	dma_page = (unsigned long *)__get_free_page(GFP_KERNEL);
 	memset(dma_page, 0, PAGE_SIZE);
 	dma_base = PAGE_ALIGN(start);
 	dma_size = PAGE_ALIGN(end) - PAGE_ALIGN(start);
@ -58,10 +53,11 @@ static unsigned long __alloc_dma_pages(unsigned int pages)
 	spin_lock_irqsave(&dma_page_lock, flags);
 	for (i = 0; i < dma_pages;) {
-		if (dma_page[i++] == 0) {
+		if (test_bit(i++, dma_page) == 0) {
 			if (++count == pages) {
 				while (count--)
-					dma_page[--i] = 1;
+					__set_bit(--i, dma_page);
 				ret = dma_base + (i << PAGE_SHIFT);
 				break;
 			}
@ -84,14 +80,14 @@ static void __free_dma_pages(unsigned long addr, unsigned int pages)
 	}
 	spin_lock_irqsave(&dma_page_lock, flags);
-	for (i = page; i < page + pages; i++) {
+	for (i = page; i < page + pages; i++)
-		dma_page[i] = 0;
+		__clear_bit(i, dma_page);
-	}
+
 	spin_unlock_irqrestore(&dma_page_lock, flags);
 }
 void *dma_alloc_coherent(struct device *dev, size_t size,
-			 dma_addr_t * dma_handle, gfp_t gfp)
+			 dma_addr_t *dma_handle, gfp_t gfp)
 {
 	void *ret;
@ -115,21 +111,14 @@ dma_free_coherent(struct device *dev, size_t size, void *vaddr,
 EXPORT_SYMBOL(dma_free_coherent);
 /*
- * Dummy functions defined for some existing drivers
+ * Streaming DMA mappings
 */
-
+void __dma_sync(dma_addr_t addr, size_t size,
-dma_addr_t
+		enum dma_data_direction dir)
 dma_map_single(struct device *dev, void *ptr, size_t size,
 	       enum dma_data_direction direction)
 {
-	BUG_ON(direction == DMA_NONE);
+	_dma_sync(addr, size, dir);
 	invalidate_dcache_range((unsigned long)ptr,
 			(unsigned long)ptr + size);
 	return (dma_addr_t) ptr;
 }
-EXPORT_SYMBOL(dma_map_single);
+EXPORT_SYMBOL(__dma_sync);
 int
 dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
@ -137,30 +126,23 @@ dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
 {
 	int i;
 	BUG_ON(direction == DMA_NONE);
 	for (i = 0; i < nents; i++, sg++) {
 		sg->dma_address = (dma_addr_t) sg_virt(sg);
-
+		__dma_sync(sg_dma_address(sg), sg_dma_len(sg), direction);
 		invalidate_dcache_range(sg_dma_address(sg),
 					sg_dma_address(sg) +
 					sg_dma_len(sg));
 	}
 	return nents;
 }
 EXPORT_SYMBOL(dma_map_sg);
-void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
+void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
-		enum dma_data_direction direction)
+			    int nelems, enum dma_data_direction direction)
 {
-	BUG_ON(direction == DMA_NONE);
+	int i;
 }
 EXPORT_SYMBOL(dma_unmap_single);
-void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
+	for (i = 0; i < nelems; i++, sg++) {
-		int nhwentries, enum dma_data_direction direction)
+		sg->dma_address = (dma_addr_t) sg_virt(sg);
-{
+		__dma_sync(sg_dma_address(sg), sg_dma_len(sg), direction);
-	BUG_ON(direction == DMA_NONE);
+	}
 }
-EXPORT_SYMBOL(dma_unmap_sg);
+EXPORT_SYMBOL(dma_sync_sg_for_device);
--- a/arch/blackfin/kernel/gptimers.c
+++ b/arch/blackfin/kernel/gptimers.c
@ -137,7 +137,7 @@ static uint32_t const timil_mask[MAX_BLACKFIN_GPTIMERS] =
 #endif
 };
-void set_gptimer_pwidth(int timer_id, uint32_t value)
+void set_gptimer_pwidth(unsigned int timer_id, uint32_t value)
 {
 	tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
 	timer_regs[timer_id]->width = value;
@ -145,14 +145,14 @@ void set_gptimer_pwidth(int timer_id, uint32_t value)
 }
 EXPORT_SYMBOL(set_gptimer_pwidth);
-uint32_t get_gptimer_pwidth(int timer_id)
+uint32_t get_gptimer_pwidth(unsigned int timer_id)
 {
 	tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
 	return timer_regs[timer_id]->width;
 }
 EXPORT_SYMBOL(get_gptimer_pwidth);
-void set_gptimer_period(int timer_id, uint32_t period)
+void set_gptimer_period(unsigned int timer_id, uint32_t period)
 {
 	tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
 	timer_regs[timer_id]->period = period;
@ -160,28 +160,28 @@ void set_gptimer_period(int timer_id, uint32_t period)
 }
 EXPORT_SYMBOL(set_gptimer_period);
-uint32_t get_gptimer_period(int timer_id)
+uint32_t get_gptimer_period(unsigned int timer_id)
 {
 	tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
 	return timer_regs[timer_id]->period;
 }
 EXPORT_SYMBOL(get_gptimer_period);
-uint32_t get_gptimer_count(int timer_id)
+uint32_t get_gptimer_count(unsigned int timer_id)
 {
 	tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
 	return timer_regs[timer_id]->counter;
 }
 EXPORT_SYMBOL(get_gptimer_count);
-uint32_t get_gptimer_status(int group)
+uint32_t get_gptimer_status(unsigned int group)
 {
 	tassert(group < BFIN_TIMER_NUM_GROUP);
 	return group_regs[group]->status;
 }
 EXPORT_SYMBOL(get_gptimer_status);
-void set_gptimer_status(int group, uint32_t value)
+void set_gptimer_status(unsigned int group, uint32_t value)
 {
 	tassert(group < BFIN_TIMER_NUM_GROUP);
 	group_regs[group]->status = value;
@ -189,42 +189,42 @@ void set_gptimer_status(int group, uint32_t value)
 }
 EXPORT_SYMBOL(set_gptimer_status);
-int get_gptimer_intr(int timer_id)
+int get_gptimer_intr(unsigned int timer_id)
 {
 	tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
 	return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & timil_mask[timer_id]);
 }
 EXPORT_SYMBOL(get_gptimer_intr);
-void clear_gptimer_intr(int timer_id)
+void clear_gptimer_intr(unsigned int timer_id)
 {
 	tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
 	group_regs[BFIN_TIMER_OCTET(timer_id)]->status = timil_mask[timer_id];
 }
 EXPORT_SYMBOL(clear_gptimer_intr);
-int get_gptimer_over(int timer_id)
+int get_gptimer_over(unsigned int timer_id)
 {
 	tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
 	return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & tovf_mask[timer_id]);
 }
 EXPORT_SYMBOL(get_gptimer_over);
-void clear_gptimer_over(int timer_id)
+void clear_gptimer_over(unsigned int timer_id)
 {
 	tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
 	group_regs[BFIN_TIMER_OCTET(timer_id)]->status = tovf_mask[timer_id];
 }
 EXPORT_SYMBOL(clear_gptimer_over);
-int get_gptimer_run(int timer_id)
+int get_gptimer_run(unsigned int timer_id)
 {
 	tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
 	return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & trun_mask[timer_id]);
 }
 EXPORT_SYMBOL(get_gptimer_run);
-void set_gptimer_config(int timer_id, uint16_t config)
+void set_gptimer_config(unsigned int timer_id, uint16_t config)
 {
 	tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
 	timer_regs[timer_id]->config = config;
@ -232,7 +232,7 @@ void set_gptimer_config(int timer_id, uint16_t config)
 }
 EXPORT_SYMBOL(set_gptimer_config);
-uint16_t get_gptimer_config(int timer_id)
+uint16_t get_gptimer_config(unsigned int timer_id)
 {
 	tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
 	return timer_regs[timer_id]->config;
@ -280,7 +280,7 @@ void disable_gptimers_sync(uint16_t mask)
 }
 EXPORT_SYMBOL(disable_gptimers_sync);
-void set_gptimer_pulse_hi(int timer_id)
+void set_gptimer_pulse_hi(unsigned int timer_id)
 {
 	tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
 	timer_regs[timer_id]->config |= TIMER_PULSE_HI;
@ -288,7 +288,7 @@ void set_gptimer_pulse_hi(int timer_id)
 }
 EXPORT_SYMBOL(set_gptimer_pulse_hi);
-void clear_gptimer_pulse_hi(int timer_id)
+void clear_gptimer_pulse_hi(unsigned int timer_id)
 {
 	tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
 	timer_regs[timer_id]->config &= ~TIMER_PULSE_HI;
--- a/arch/blackfin/kernel/ipipe.c
+++ b/arch/blackfin/kernel/ipipe.c
@ -335,3 +335,70 @@ void __ipipe_enable_root_irqs_hw(void)
 	__clear_bit(IPIPE_STALL_FLAG, &ipipe_root_cpudom_var(status));
 	bfin_sti(bfin_irq_flags);
 }
 /*
 * We could use standard atomic bitops in the following root status
 * manipulation routines, but let's prepare for SMP support in the
 * same move, preventing CPU migration as required.
 */
 void __ipipe_stall_root(void)
 {
 	unsigned long *p, flags;
 	local_irq_save_hw(flags);
 	p = &__ipipe_root_status;
 	__set_bit(IPIPE_STALL_FLAG, p);
 	local_irq_restore_hw(flags);
 }
 EXPORT_SYMBOL(__ipipe_stall_root);
 unsigned long __ipipe_test_and_stall_root(void)
 {
 	unsigned long *p, flags;
 	int x;
 	local_irq_save_hw(flags);
 	p = &__ipipe_root_status;
 	x = __test_and_set_bit(IPIPE_STALL_FLAG, p);
 	local_irq_restore_hw(flags);
 	return x;
 }
 EXPORT_SYMBOL(__ipipe_test_and_stall_root);
 unsigned long __ipipe_test_root(void)
 {
 	const unsigned long *p;
 	unsigned long flags;
 	int x;
 	local_irq_save_hw_smp(flags);
 	p = &__ipipe_root_status;
 	x = test_bit(IPIPE_STALL_FLAG, p);
 	local_irq_restore_hw_smp(flags);
 	return x;
 }
 EXPORT_SYMBOL(__ipipe_test_root);
 void __ipipe_lock_root(void)
 {
 	unsigned long *p, flags;
 	local_irq_save_hw(flags);
 	p = &__ipipe_root_status;
 	__set_bit(IPIPE_SYNCDEFER_FLAG, p);
 	local_irq_restore_hw(flags);
 }
 EXPORT_SYMBOL(__ipipe_lock_root);
 void __ipipe_unlock_root(void)
 {
 	unsigned long *p, flags;
 	local_irq_save_hw(flags);
 	p = &__ipipe_root_status;
 	__clear_bit(IPIPE_SYNCDEFER_FLAG, p);
 	local_irq_restore_hw(flags);
 }
 EXPORT_SYMBOL(__ipipe_unlock_root);
--- a/arch/blackfin/kernel/kgdb.c
+++ b/arch/blackfin/kernel/kgdb.c
@ -24,16 +24,6 @@
 #include <asm/blackfin.h>
 #include <asm/dma.h>
 /* Put the error code here just in case the user cares.  */
 int gdb_bfin_errcode;
 /* Likewise, the vector number here (since GDB only gets the signal
   number through the usual means, and that's not very specific).  */
 int gdb_bfin_vector = -1;
 #if KGDB_MAX_NO_CPUS != 8
 #error change the definition of slavecpulocks
 #endif
 void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
 {
 	gdb_regs[BFIN_R0] = regs->r0;
@ -369,13 +359,6 @@ void kgdb_roundup_cpu(int cpu, unsigned long flags)
 }
 #endif
 void kgdb_post_primary_code(struct pt_regs *regs, int eVector, int err_code)
 {
 	/* Master processor is completely in the debugger */
 	gdb_bfin_vector = eVector;
 	gdb_bfin_errcode = err_code;
 }
 int kgdb_arch_handle_exception(int vector, int signo,
 			       int err_code, char *remcom_in_buffer,
 			       char *remcom_out_buffer,
--- a/arch/blackfin/kernel/kgdb_test.c
+++ b/arch/blackfin/kernel/kgdb_test.c
@ -17,8 +17,9 @@
 #include <asm/blackfin.h>
 /* Symbols are here for kgdb test to poke directly */
 static char cmdline[256];
-static unsigned long len;
+static size_t len;
 #ifndef CONFIG_SMP
 static int num1 __attribute__((l1_data));
@ -27,11 +28,10 @@ void kgdb_l1_test(void) __attribute__((l1_text));
 void kgdb_l1_test(void)
 {
-	printk(KERN_ALERT "L1(before change) : data variable addr = 0x%p, data value is %d\n", &num1, num1);
+	pr_alert("L1(before change) : data variable addr = 0x%p, data value is %d\n", &num1, num1);
-	printk(KERN_ALERT "L1 : code function addr = 0x%p\n", kgdb_l1_test);
+	pr_alert("L1 : code function addr = 0x%p\n", kgdb_l1_test);
-	num1 = num1 + 10 ;
+	num1 = num1 + 10;
-	printk(KERN_ALERT "L1(after change) : data variable addr = 0x%p, data value is %d\n", &num1, num1);
+	pr_alert("L1(after change) : data variable addr = 0x%p, data value is %d\n", &num1, num1);
 	return ;
 }
 #endif
@ -42,11 +42,10 @@ void kgdb_l2_test(void) __attribute__((l2));
 void kgdb_l2_test(void)
 {
-	printk(KERN_ALERT "L2(before change) : data variable addr = 0x%p, data value is %d\n", &num2, num2);
+	pr_alert("L2(before change) : data variable addr = 0x%p, data value is %d\n", &num2, num2);
-	printk(KERN_ALERT "L2 : code function addr = 0x%p\n", kgdb_l2_test);
+	pr_alert("L2 : code function addr = 0x%p\n", kgdb_l2_test);
-	num2 = num2 + 20 ;
+	num2 = num2 + 20;
-	printk(KERN_ALERT "L2(after change) : data variable addr = 0x%p, data value is %d\n", &num2, num2);
+	pr_alert("L2(after change) : data variable addr = 0x%p, data value is %d\n", &num2, num2);
 	return ;
 }
 #endif
@ -54,12 +53,14 @@ void kgdb_l2_test(void)
 int kgdb_test(char *name, int len, int count, int z)
 {
-	printk(KERN_ALERT "kgdb name(%d): %s, %d, %d\n", len, name, count, z);
+	pr_alert("kgdb name(%d): %s, %d, %d\n", len, name, count, z);
 	count = z;
 	return count;
 }
-static int test_proc_output(char *buf)
+static ssize_t
 kgdb_test_proc_read(struct file *file, char __user *buf,
                    size_t count, loff_t *ppos)
 {
 	kgdb_test("hello world!", 12, 0x55, 0x10);
 #ifndef CONFIG_SMP
@ -72,49 +73,31 @@ static int test_proc_output(char *buf)
 	return 0;
 }
-static int test_read_proc(char *page, char **start, off_t off,
+static ssize_t
-				 int count, int *eof, void *data)
+kgdb_test_proc_write(struct file *file, const char __user *buffer,
                     size_t count, loff_t *pos)
 {
-	int len;
+	len = min_t(size_t, 255, count);
 	len = test_proc_output(page);
 	if (len <= off+count)
 		*eof = 1;
 	*start = page + off;
 	len -= off;
 	if (len > count)
 		len = count;
 	if (len < 0)
 		len = 0;
 	return len;
 }
 static int test_write_proc(struct file *file, const char *buffer,
 				 unsigned long count, void *data)
 {
 	if (count >= 256)
 		len = 255;
 	else
 		len = count;
 	memcpy(cmdline, buffer, count);
 	cmdline[len] = 0;
 	return len;
 }
 static const struct file_operations kgdb_test_proc_fops = {
 	.owner = THIS_MODULE,
 	.read  = kgdb_test_proc_read,
 	.write = kgdb_test_proc_write,
 };
 static int __init kgdbtest_init(void)
 {
 	struct proc_dir_entry *entry;
-	entry = create_proc_entry("kgdbtest", 0, NULL);
+	entry = proc_create("kgdbtest", 0, NULL, &kgdb_test_proc_fops);
 	if (entry == NULL)
 		return -ENOMEM;
 	entry->read_proc = test_read_proc;
 	entry->write_proc = test_write_proc;
 	entry->data = NULL;
 	return 0;
 }
--- a/arch/blackfin/kernel/process.c
+++ b/arch/blackfin/kernel/process.c
@ -258,9 +258,12 @@ void finish_atomic_sections (struct pt_regs *regs)
 	int __user *up0 = (int __user *)regs->p0;
 	switch (regs->pc) {
 	default:
 		/* not in middle of an atomic step, so resume like normal */
 		return;
 	case ATOMIC_XCHG32 + 2:
 		put_user(regs->r1, up0);
 		regs->pc = ATOMIC_XCHG32 + 4;
 		break;
 	case ATOMIC_CAS32 + 2:
@ -268,7 +271,6 @@ void finish_atomic_sections (struct pt_regs *regs)
 		if (regs->r0 == regs->r1)
 	case ATOMIC_CAS32 + 6:
 			put_user(regs->r2, up0);
 		regs->pc = ATOMIC_CAS32 + 8;
 		break;
 	case ATOMIC_ADD32 + 2:
@ -276,7 +278,6 @@ void finish_atomic_sections (struct pt_regs *regs)
 		/* fall through */
 	case ATOMIC_ADD32 + 4:
 		put_user(regs->r0, up0);
 		regs->pc = ATOMIC_ADD32 + 6;
 		break;
 	case ATOMIC_SUB32 + 2:
@ -284,7 +285,6 @@ void finish_atomic_sections (struct pt_regs *regs)
 		/* fall through */
 	case ATOMIC_SUB32 + 4:
 		put_user(regs->r0, up0);
 		regs->pc = ATOMIC_SUB32 + 6;
 		break;
 	case ATOMIC_IOR32 + 2:
@ -292,7 +292,6 @@ void finish_atomic_sections (struct pt_regs *regs)
 		/* fall through */
 	case ATOMIC_IOR32 + 4:
 		put_user(regs->r0, up0);
 		regs->pc = ATOMIC_IOR32 + 6;
 		break;
 	case ATOMIC_AND32 + 2:
@ -300,7 +299,6 @@ void finish_atomic_sections (struct pt_regs *regs)
 		/* fall through */
 	case ATOMIC_AND32 + 4:
 		put_user(regs->r0, up0);
 		regs->pc = ATOMIC_AND32 + 6;
 		break;
 	case ATOMIC_XOR32 + 2:
@ -308,9 +306,15 @@ void finish_atomic_sections (struct pt_regs *regs)
 		/* fall through */
 	case ATOMIC_XOR32 + 4:
 		put_user(regs->r0, up0);
 		regs->pc = ATOMIC_XOR32 + 6;
 		break;
 	}
 	/*
 	 * We've finished the atomic section, and the only thing left for
 	 * userspace is to do a RTS, so we might as well handle that too
 	 * since we need to update the PC anyways.
 	 */
 	regs->pc = regs->rets;
 }
 static inline
@ -332,12 +336,58 @@ int in_mem_const(unsigned long addr, unsigned long size,
 {
 	return in_mem_const_off(addr, size, 0, const_addr, const_size);
 }
-#define IN_ASYNC(bnum, bctlnum) \
+#define ASYNC_ENABLED(bnum, bctlnum) \
 ({ \
-	(bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? -EFAULT : \
+	(bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? 0 : \
-	bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? -EFAULT : \
+	bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? 0 : \
-	BFIN_MEM_ACCESS_CORE; \
+	1; \
 })
 /*
 * We can't read EBIU banks that aren't enabled or we end up hanging
 * on the access to the async space.  Make sure we validate accesses
 * that cross async banks too.
 *	0 - found, but unusable
 *	1 - found & usable
 *	2 - not found
 */
 static
 int in_async(unsigned long addr, unsigned long size)
 {
 	if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE) {
 		if (!ASYNC_ENABLED(0, 0))
 			return 0;
 		if (addr + size <= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE)
 			return 1;
 		size -= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE - addr;
 		addr = ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE;
 	}
 	if (addr >= ASYNC_BANK1_BASE && addr < ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE) {
 		if (!ASYNC_ENABLED(1, 0))
 			return 0;
 		if (addr + size <= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE)
 			return 1;
 		size -= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE - addr;
 		addr = ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE;
 	}
 	if (addr >= ASYNC_BANK2_BASE && addr < ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE) {
 		if (!ASYNC_ENABLED(2, 1))
 			return 0;
 		if (addr + size <= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE)
 			return 1;
 		size -= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE - addr;
 		addr = ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE;
 	}
 	if (addr >= ASYNC_BANK3_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
 		if (ASYNC_ENABLED(3, 1))
 			return 0;
 		if (addr + size <= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE)
 			return 1;
 		return 0;
 	}
 	/* not within async bounds */
 	return 2;
 }
 int bfin_mem_access_type(unsigned long addr, unsigned long size)
 {
@ -374,17 +424,11 @@ int bfin_mem_access_type(unsigned long addr, unsigned long size)
 	if (addr >= SYSMMR_BASE)
 		return BFIN_MEM_ACCESS_CORE_ONLY;
-	/* We can't read EBIU banks that aren't enabled or we end up hanging
+	switch (in_async(addr, size)) {
-	 * on the access to the async space.
+	case 0: return -EFAULT;
-	 */
+	case 1: return BFIN_MEM_ACCESS_CORE;
-	if (in_mem_const(addr, size, ASYNC_BANK0_BASE, ASYNC_BANK0_SIZE))
+	case 2: /* fall through */;
-		return IN_ASYNC(0, 0);
+	}
 	if (in_mem_const(addr, size, ASYNC_BANK1_BASE, ASYNC_BANK1_SIZE))
 		return IN_ASYNC(1, 0);
 	if (in_mem_const(addr, size, ASYNC_BANK2_BASE, ASYNC_BANK2_SIZE))
 		return IN_ASYNC(2, 1);
 	if (in_mem_const(addr, size, ASYNC_BANK3_BASE, ASYNC_BANK3_SIZE))
 		return IN_ASYNC(3, 1);
 	if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
 		return BFIN_MEM_ACCESS_CORE;
@ -401,6 +445,8 @@ __attribute__((l1_text))
 /* Return 1 if access to memory range is OK, 0 otherwise */
 int _access_ok(unsigned long addr, unsigned long size)
 {
 	int aret;
 	if (size == 0)
 		return 1;
 	/* Check that things do not wrap around */
@ -450,6 +496,11 @@ int _access_ok(unsigned long addr, unsigned long size)
 	if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
 		return 1;
 #endif
 	aret = in_async(addr, size);
 	if (aret < 2)
 		return aret;
 	if (in_mem_const_off(addr, size, _ebss_l2 - _stext_l2, L2_START, L2_LENGTH))
 		return 1;
--- a/arch/blackfin/kernel/ptrace.c
+++ b/arch/blackfin/kernel/ptrace.c
@ -316,19 +316,6 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
 			case BFIN_MEM_ACCESS_CORE_ONLY:
 				copied = access_process_vm(child, addr, &data,
 				                           to_copy, 1);
 				if (copied)
 					break;
 				/* hrm, why didn't that work ... maybe no mapping */
 				if (addr >= FIXED_CODE_START &&
 				    addr + to_copy <= FIXED_CODE_END) {
 					copy_to_user_page(0, 0, 0, paddr, &data, to_copy);
 					copied = to_copy;
 				} else if (addr >= BOOT_ROM_START) {
 					memcpy(paddr, &data, to_copy);
 					copied = to_copy;
 				}
 				break;
 			case BFIN_MEM_ACCESS_DMA:
 				if (safe_dma_memcpy(paddr, &data, to_copy))
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@ -178,10 +178,10 @@ void __init bfin_cache_init(void)
 void __init bfin_relocate_l1_mem(void)
 {
-	unsigned long l1_code_length;
+	unsigned long text_l1_len = (unsigned long)_text_l1_len;
-	unsigned long l1_data_a_length;
+	unsigned long data_l1_len = (unsigned long)_data_l1_len;
-	unsigned long l1_data_b_length;
+	unsigned long data_b_l1_len = (unsigned long)_data_b_l1_len;
-	unsigned long l2_length;
+	unsigned long l2_len = (unsigned long)_l2_len;
 	early_shadow_stamp();
@ -201,30 +201,23 @@ void __init bfin_relocate_l1_mem(void)
 	blackfin_dma_early_init();
-	/* if necessary, copy _stext_l1 to _etext_l1 to L1 instruction SRAM */
+	/* if necessary, copy L1 text to L1 instruction SRAM */
-	l1_code_length = _etext_l1 - _stext_l1;
+	if (L1_CODE_LENGTH && text_l1_len)
-	if (l1_code_length)
+		early_dma_memcpy(_stext_l1, _text_l1_lma, text_l1_len);
 		early_dma_memcpy(_stext_l1, _l1_lma_start, l1_code_length);
-	/* if necessary, copy _sdata_l1 to _sbss_l1 to L1 data bank A SRAM */
+	/* if necessary, copy L1 data to L1 data bank A SRAM */
-	l1_data_a_length = _sbss_l1 - _sdata_l1;
+	if (L1_DATA_A_LENGTH && data_l1_len)
-	if (l1_data_a_length)
+		early_dma_memcpy(_sdata_l1, _data_l1_lma, data_l1_len);
 		early_dma_memcpy(_sdata_l1, _l1_lma_start + l1_code_length, l1_data_a_length);
-	/* if necessary, copy _sdata_b_l1 to _sbss_b_l1 to L1 data bank B SRAM */
+	/* if necessary, copy L1 data B to L1 data bank B SRAM */
-	l1_data_b_length = _sbss_b_l1 - _sdata_b_l1;
+	if (L1_DATA_B_LENGTH && data_b_l1_len)
-	if (l1_data_b_length)
+		early_dma_memcpy(_sdata_b_l1, _data_b_l1_lma, data_b_l1_len);
 		early_dma_memcpy(_sdata_b_l1, _l1_lma_start + l1_code_length +
 			l1_data_a_length, l1_data_b_length);
 	early_dma_memcpy_done();
-	/* if necessary, copy _stext_l2 to _edata_l2 to L2 SRAM */
+	/* if necessary, copy L2 text/data to L2 SRAM */
-	if (L2_LENGTH != 0) {
+	if (L2_LENGTH && l2_len)
-		l2_length = _sbss_l2 - _stext_l2;
+		memcpy(_stext_l2, _l2_lma, l2_len);
 		if (l2_length)
 			memcpy(_stext_l2, _l2_lma_start, l2_length);
 	}
 }
 /* add_memory_region to memmap */
@ -608,11 +601,6 @@ static __init void memory_setup(void)
 	page_mask_order = get_order(3 * page_mask_nelts * sizeof(long));
 #endif
 #if !defined(CONFIG_MTD_UCLINUX)
 	/*In case there is no valid CPLB behind memory_end make sure we don't get to close*/
 	memory_end -= SIZE_4K;
 #endif
 	init_mm.start_code = (unsigned long)_stext;
 	init_mm.end_code = (unsigned long)_etext;
 	init_mm.end_data = (unsigned long)_edata;
@ -917,7 +905,7 @@ void __init setup_arch(char **cmdline_p)
 	printk(KERN_INFO "Blackfin support (C) 2004-2009 Analog Devices, Inc.\n");
 	if (bfin_compiled_revid() == 0xffff)
-		printk(KERN_INFO "Compiled for ADSP-%s Rev any\n", CPU);
+		printk(KERN_INFO "Compiled for ADSP-%s Rev any, running on 0.%d\n", CPU, bfin_revid());
 	else if (bfin_compiled_revid() == -1)
 		printk(KERN_INFO "Compiled for ADSP-%s Rev none\n", CPU);
 	else
--- a/arch/blackfin/kernel/signal.c
+++ b/arch/blackfin/kernel/signal.c
@ -12,6 +12,7 @@
 #include <linux/binfmts.h>
 #include <linux/freezer.h>
 #include <linux/uaccess.h>
 #include <linux/tracehook.h>
 #include <asm/cacheflush.h>
 #include <asm/ucontext.h>
@ -332,3 +333,20 @@ asmlinkage void do_signal(struct pt_regs *regs)
 		sigprocmask(SIG_SETMASK, &current->saved_sigmask, NULL);
 	}
 }
 /*
 * notification of userspace execution resumption
 */
 asmlinkage void do_notify_resume(struct pt_regs *regs)
 {
 	if (test_thread_flag(TIF_SIGPENDING) || test_thread_flag(TIF_RESTORE_SIGMASK))
 		do_signal(regs);
 	if (test_thread_flag(TIF_NOTIFY_RESUME)) {
 		clear_thread_flag(TIF_NOTIFY_RESUME);
 		tracehook_notify_resume(regs);
 		if (current->replacement_session_keyring)
 			key_replace_session_keyring();
 	}
 }
--- a/arch/blackfin/kernel/time-ts.c
+++ b/arch/blackfin/kernel/time-ts.c
@ -22,8 +22,6 @@
 #include <asm/time.h>
 #include <asm/gptimers.h>
 #if defined(CONFIG_CYCLES_CLOCKSOURCE)
 /* Accelerators for sched_clock()
 * convert from cycles(64bits) => nanoseconds (64bits)
 *  basic equation:
@ -46,20 +44,11 @@
 *			-johnstul@us.ibm.com "math is hard, lets go shopping!"
 */
 static unsigned long cyc2ns_scale;
 #define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
-static inline void set_cyc2ns_scale(unsigned long cpu_khz)
+#if defined(CONFIG_CYCLES_CLOCKSOURCE)
 {
 	cyc2ns_scale = (1000000 << CYC2NS_SCALE_FACTOR) / cpu_khz;
 }
-static inline unsigned long long cycles_2_ns(cycle_t cyc)
+static notrace cycle_t bfin_read_cycles(struct clocksource *cs)
 {
 	return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR;
 }
 static cycle_t bfin_read_cycles(struct clocksource *cs)
 {
 	return __bfin_cycles_off + (get_cycles() << __bfin_cycles_mod);
 }
@ -69,19 +58,18 @@ static struct clocksource bfin_cs_cycles = {
 	.rating		= 400,
 	.read		= bfin_read_cycles,
 	.mask		= CLOCKSOURCE_MASK(64),
-	.shift		= 22,
+	.shift		= CYC2NS_SCALE_FACTOR,
 	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
 };
-unsigned long long sched_clock(void)
+static inline unsigned long long bfin_cs_cycles_sched_clock(void)
 {
-	return cycles_2_ns(bfin_read_cycles(&bfin_cs_cycles));
+	return clocksource_cyc2ns(bfin_read_cycles(&bfin_cs_cycles),
 		bfin_cs_cycles.mult, bfin_cs_cycles.shift);
 }
 static int __init bfin_cs_cycles_init(void)
 {
 	set_cyc2ns_scale(get_cclk() / 1000);
 	bfin_cs_cycles.mult = \
 		clocksource_hz2mult(get_cclk(), bfin_cs_cycles.shift);
@ -108,7 +96,7 @@ void __init setup_gptimer0(void)
 	enable_gptimers(TIMER0bit);
 }
-static cycle_t bfin_read_gptimer0(void)
+static cycle_t bfin_read_gptimer0(struct clocksource *cs)
 {
 	return bfin_read_TIMER0_COUNTER();
 }
@ -118,10 +106,16 @@ static struct clocksource bfin_cs_gptimer0 = {
 	.rating		= 350,
 	.read		= bfin_read_gptimer0,
 	.mask		= CLOCKSOURCE_MASK(32),
-	.shift		= 22,
+	.shift		= CYC2NS_SCALE_FACTOR,
 	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
 };
 static inline unsigned long long bfin_cs_gptimer0_sched_clock(void)
 {
 	return clocksource_cyc2ns(bfin_read_TIMER0_COUNTER(),
 		bfin_cs_gptimer0.mult, bfin_cs_gptimer0.shift);
 }
 static int __init bfin_cs_gptimer0_init(void)
 {
 	setup_gptimer0();
@ -138,6 +132,19 @@ static int __init bfin_cs_gptimer0_init(void)
 # define bfin_cs_gptimer0_init()
 #endif
 #if defined(CONFIG_GPTMR0_CLOCKSOURCE) || defined(CONFIG_CYCLES_CLOCKSOURCE)
 /* prefer to use cycles since it has higher rating */
 notrace unsigned long long sched_clock(void)
 {
 #if defined(CONFIG_CYCLES_CLOCKSOURCE)
 	return bfin_cs_cycles_sched_clock();
 #else
 	return bfin_cs_gptimer0_sched_clock();
 #endif
 }
 #endif
 #ifdef CONFIG_CORE_TIMER_IRQ_L1
 __attribute__((l1_text))
 #endif
--- a/arch/blackfin/kernel/time.c
+++ b/arch/blackfin/kernel/time.c
@ -184,11 +184,3 @@ void __init time_init(void)
 	time_sched_init(timer_interrupt);
 }
 /*
 * Scheduler clock - returns current time in nanosec units.
 */
 unsigned long long sched_clock(void)
 {
 	return (unsigned long long)jiffies *(NSEC_PER_SEC / HZ);
 }
--- a/arch/blackfin/kernel/traps.c
+++ b/arch/blackfin/kernel/traps.c
@ -119,6 +119,15 @@ static void decode_address(char *buf, unsigned long address)
 		return;
 	}
 	/*
 	 * Don't walk any of the vmas if we are oopsing, it has been known
 	 * to cause problems - corrupt vmas (kernel crashes) cause double faults
 	 */
 	if (oops_in_progress) {
 		strcat(buf, "/* kernel dynamic memory (maybe user-space) */");
 		return;
 	}
 	/* looks like we're off in user-land, so let's walk all the
 	 * mappings of all our processes and see if we can't be a whee
 	 * bit more specific
@ -515,6 +524,36 @@ asmlinkage notrace void trap_c(struct pt_regs *fp)
 			break;
 		/* External Memory Addressing Error */
 		case (SEQSTAT_HWERRCAUSE_EXTERN_ADDR):
 			if (ANOMALY_05000310) {
 				static unsigned long anomaly_rets;
 				if ((fp->pc >= (L1_CODE_START + L1_CODE_LENGTH - 512)) &&
 				    (fp->pc < (L1_CODE_START + L1_CODE_LENGTH))) {
 					/*
 					 * A false hardware error will happen while fetching at
 					 * the L1 instruction SRAM boundary.  Ignore it.
 					 */
 					anomaly_rets = fp->rets;
 					goto traps_done;
 				} else if (fp->rets == anomaly_rets) {
 					/*
 					 * While boundary code returns to a function, at the ret
 					 * point, a new false hardware error might occur too based
 					 * on tests.  Ignore it too.
 					 */
 					goto traps_done;
 				} else if ((fp->rets >= (L1_CODE_START + L1_CODE_LENGTH - 512)) &&
 				           (fp->rets < (L1_CODE_START + L1_CODE_LENGTH))) {
 					/*
 					 * If boundary code calls a function, at the entry point,
 					 * a new false hardware error maybe happen based on tests.
 					 * Ignore it too.
 					 */
 					goto traps_done;
 				} else
 					anomaly_rets = 0;
 			}
 			info.si_code = BUS_ADRERR;
 			sig = SIGBUS;
 			strerror = KERN_NOTICE HWC_x3(KERN_NOTICE);
@ -976,12 +1015,12 @@ void dump_bfin_process(struct pt_regs *fp)
 	    !((unsigned long)current & 0x3) && current->pid) {
 		verbose_printk(KERN_NOTICE "CURRENT PROCESS:\n");
 		if (current->comm >= (char *)FIXED_CODE_START)
-			verbose_printk(KERN_NOTICE "COMM=%s PID=%d\n",
+			verbose_printk(KERN_NOTICE "COMM=%s PID=%d",
 				current->comm, current->pid);
 		else
-			verbose_printk(KERN_NOTICE "COMM= invalid\n");
+			verbose_printk(KERN_NOTICE "COMM= invalid");
-		printk(KERN_NOTICE "CPU = %d\n", current_thread_info()->cpu);
+		printk(KERN_CONT " CPU=%d\n", current_thread_info()->cpu);
 		if (!((unsigned long)current->mm & 0x3) && (unsigned long)current->mm >= FIXED_CODE_START)
 			verbose_printk(KERN_NOTICE
 				"TEXT = 0x%p-0x%p        DATA = 0x%p-0x%p\n"
--- a/arch/blackfin/kernel/vmlinux.lds.S
+++ b/arch/blackfin/kernel/vmlinux.lds.S
@ -121,8 +121,6 @@ SECTIONS
 		EXIT_DATA
 	}
 	__l1_lma_start = .;
 	.text_l1 L1_CODE_START : AT(LOADADDR(.exit.data) + SIZEOF(.exit.data))
 	{
 		. = ALIGN(4);
@ -134,9 +132,11 @@ SECTIONS
 		. = ALIGN(4);
 		__etext_l1 = .;
 	}
-	ASSERT (SIZEOF(.text_l1) <= L1_CODE_LENGTH, "L1 text overflow!")
+	__text_l1_lma = LOADADDR(.text_l1);
 	__text_l1_len = SIZEOF(.text_l1);
 	ASSERT (__text_l1_len <= L1_CODE_LENGTH, "L1 text overflow!")
-	.data_l1 L1_DATA_A_START : AT(LOADADDR(.text_l1) + SIZEOF(.text_l1))
+	.data_l1 L1_DATA_A_START : AT(__text_l1_lma + __text_l1_len)
 	{
 		. = ALIGN(4);
 		__sdata_l1 = .;
@ -152,9 +152,11 @@ SECTIONS
 		. = ALIGN(4);
 		__ebss_l1 = .;
 	}
-	ASSERT (SIZEOF(.data_l1) <= L1_DATA_A_LENGTH, "L1 data A overflow!")
+	__data_l1_lma = LOADADDR(.data_l1);
 	__data_l1_len = SIZEOF(.data_l1);
 	ASSERT (__data_l1_len <= L1_DATA_A_LENGTH, "L1 data A overflow!")
-	.data_b_l1 L1_DATA_B_START : AT(LOADADDR(.data_l1) + SIZEOF(.data_l1))
+	.data_b_l1 L1_DATA_B_START : AT(__data_l1_lma + __data_l1_len)
 	{
 		. = ALIGN(4);
 		__sdata_b_l1 = .;
@ -167,11 +169,11 @@ SECTIONS
 		. = ALIGN(4);
 		__ebss_b_l1 = .;
 	}
-	ASSERT (SIZEOF(.data_b_l1) <= L1_DATA_B_LENGTH, "L1 data B overflow!")
+	__data_b_l1_lma = LOADADDR(.data_b_l1);
 	__data_b_l1_len = SIZEOF(.data_b_l1);
 	ASSERT (__data_b_l1_len <= L1_DATA_B_LENGTH, "L1 data B overflow!")
-	__l2_lma_start = LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1);
+	.text_data_l2 L2_START : AT(__data_b_l1_lma + __data_b_l1_len)
 	.text_data_l2 L2_START : AT(LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1))
 	{
 		. = ALIGN(4);
 		__stext_l2 = .;
@ -193,12 +195,14 @@ SECTIONS
 		. = ALIGN(4);
 		__ebss_l2 = .;
 	}
-	ASSERT (SIZEOF(.text_data_l2) <= L2_LENGTH, "L2 overflow!")
+	__l2_lma = LOADADDR(.text_data_l2);
 	__l2_len = SIZEOF(.text_data_l2);
 	ASSERT (__l2_len <= L2_LENGTH, "L2 overflow!")
 	/* Force trailing alignment of our init section so that when we
 	 * free our init memory, we don't leave behind a partial page.
 	 */
-	. = LOADADDR(.text_data_l2) + SIZEOF(.text_data_l2);
+	. = __l2_lma + __l2_len;
 	. = ALIGN(PAGE_SIZE);
 	___init_end = .;
--- a/arch/blackfin/lib/Makefile
+++ b/arch/blackfin/lib/Makefile
@ -5,7 +5,7 @@
 lib-y := \
 	ashldi3.o ashrdi3.o lshrdi3.o \
 	muldi3.o divsi3.o udivsi3.o modsi3.o umodsi3.o \
-	checksum.o memcpy.o memset.o memcmp.o memchr.o memmove.o \
+	memcpy.o memset.o memcmp.o memchr.o memmove.o \
 	strcmp.o strcpy.o strncmp.o strncpy.o \
 	umulsi3_highpart.o smulsi3_highpart.o \
 	ins.o outs.o
--- a/arch/blackfin/lib/checksum.c
+++ b/arch/blackfin/lib/checksum.c
@ -1,125 +0,0 @@
 /*
 * Copyright 2004-2009 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
 *
 * An implementation of the TCP/IP protocol suite for the LINUX operating
 * system. INET is implemented using the BSD Socket interface as the
 * means of communication with the user level.
 *
 */
 #include <linux/module.h>
 #include <net/checksum.h>
 #include <asm/checksum.h>
 #ifdef CONFIG_IP_CHECKSUM_L1
 static unsigned short do_csum(const unsigned char *buff, int len)__attribute__((l1_text));
 #endif
 static unsigned short do_csum(const unsigned char *buff, int len)
 {
 	register unsigned long sum = 0;
 	int swappem = 0;
 	if (1 & (unsigned long)buff) {
 		sum = *buff << 8;
 		buff++;
 		len--;
 		++swappem;
 	}
 	while (len > 1) {
 		sum += *(unsigned short *)buff;
 		buff += 2;
 		len -= 2;
 	}
 	if (len > 0)
 		sum += *buff;
 	/*  Fold 32-bit sum to 16 bits */
 	while (sum >> 16)
 		sum = (sum & 0xffff) + (sum >> 16);
 	if (swappem)
 		sum = ((sum & 0xff00) >> 8) + ((sum & 0x00ff) << 8);
 	return sum;
 }
 /*
 *	This is a version of ip_compute_csum() optimized for IP headers,
 *	which always checksum on 4 octet boundaries.
 */
 __sum16 ip_fast_csum(unsigned char *iph, unsigned int ihl)
 {
 	return (__force __sum16)~do_csum(iph, ihl * 4);
 }
 EXPORT_SYMBOL(ip_fast_csum);
 /*
 * computes the checksum of a memory block at buff, length len,
 * and adds in "sum" (32-bit)
 *
 * returns a 32-bit number suitable for feeding into itself
 * or csum_tcpudp_magic
 *
 * this function must be called with even lengths, except
 * for the last fragment, which may be odd
 *
 * it's best to have buff aligned on a 32-bit boundary
 */
 __wsum csum_partial(const void *buff, int len, __wsum sum)
 {
 	/*
 	 * Just in case we get nasty checksum data...
 	 * Like 0xffff6ec3 in the case of our IPv6 multicast header.
 	 * We fold to begin with, as well as at the end.
 	 */
 	sum = (sum & 0xffff) + (sum >> 16);
 	sum += do_csum(buff, len);
 	sum = (sum & 0xffff) + (sum >> 16);
 	return sum;
 }
 EXPORT_SYMBOL(csum_partial);
 /*
 * this routine is used for miscellaneous IP-like checksums, mainly
 * in icmp.c
 */
 __sum16 ip_compute_csum(const void *buff, int len)
 {
 	return (__force __sum16)~do_csum(buff, len);
 }
 EXPORT_SYMBOL(ip_compute_csum);
 /*
 * copy from fs while checksumming, otherwise like csum_partial
 */
 __wsum
 csum_partial_copy_from_user(const void __user *src, void *dst,
 			    int len, __wsum sum, int *csum_err)
 {
 	if (csum_err)
 		*csum_err = 0;
 	memcpy(dst, (__force void *)src, len);
 	return csum_partial(dst, len, sum);
 }
 EXPORT_SYMBOL(csum_partial_copy_from_user);
 /*
 * copy from ds while checksumming, otherwise like csum_partial
 */
 __wsum csum_partial_copy(const void *src, void *dst, int len, __wsum sum)
 {
 	memcpy(dst, src, len);
 	return csum_partial(dst, len, sum);
 }
 EXPORT_SYMBOL(csum_partial_copy);
--- a/arch/blackfin/mach-bf518/Kconfig
+++ b/arch/blackfin/mach-bf518/Kconfig
@ -1,3 +1,7 @@
 config BF51x
 	def_bool y
 	depends on (BF512 || BF514 || BF516 || BF518)
 if (BF51x)
 source "arch/blackfin/mach-bf518/boards/Kconfig"
--- a/arch/blackfin/mach-bf518/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf518/include/mach/blackfin.h
@ -58,10 +58,4 @@
 #define OFFSET_SCR              0x1C	/* SCR Scratch Register                 */
 #define OFFSET_GCTL             0x24	/* Global Control Register              */
 /* PLL_DIV Masks													*/
 #define CCLK_DIV1 CSEL_DIV1	/*          CCLK = VCO / 1                                  */
 #define CCLK_DIV2 CSEL_DIV2	/*          CCLK = VCO / 2                                  */
 #define CCLK_DIV4 CSEL_DIV4	/*          CCLK = VCO / 4                                  */
 #define CCLK_DIV8 CSEL_DIV8	/*          CCLK = VCO / 8                                  */
 #endif
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
@ -1,7 +1,7 @@
 /*
 * Copyright 2008-2009 Analog Devices Inc.
 *
- * Licensed under the GPL-2 or later
+ * Licensed under the ADI BSD license or the GPL-2 (or later)
 */
 #ifndef _CDEF_BF514_H
@ -10,15 +10,8 @@
 /* include all Core registers and bit definitions */
 #include "defBF514.h"
-/* include core specific register pointer definitions */
+/* BF514 is BF512 + RSI */
-#include <asm/cdef_LPBlackfin.h>
+#include "cdefBF512.h"
 /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */
 /* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
 #include "cdefBF51x_base.h"
 /* The following are the #defines needed by ADSP-BF514 that are not in the common header */
 /* Removable Storage Interface Registers */
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
@ -1,7 +1,7 @@
 /*
 * Copyright 2008-2009 Analog Devices Inc.
 *
- * Licensed under the GPL-2 or later
+ * Licensed under the ADI BSD license or the GPL-2 (or later)
 */
 #ifndef _CDEF_BF516_H
@ -10,15 +10,8 @@
 /* include all Core registers and bit definitions */
 #include "defBF516.h"
-/* include core specific register pointer definitions */
+/* BF516 is BF514 + EMAC */
-#include <asm/cdef_LPBlackfin.h>
+#include "cdefBF514.h"
 /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF516 */
 /* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
 #include "cdefBF51x_base.h"
 /* The following are the #defines needed by ADSP-BF516 that are not in the common header */
 /* 10/100 Ethernet Controller	(0xFFC03000 - 0xFFC031FF) */
@ -185,71 +178,4 @@
 #define bfin_read_EMAC_TXC_ABORT()		bfin_read32(EMAC_TXC_ABORT)
 #define bfin_write_EMAC_TXC_ABORT(val)		bfin_write32(EMAC_TXC_ABORT, val)
 /* Removable Storage Interface Registers */
 #define bfin_read_RSI_PWR_CTL()        bfin_read16(RSI_PWR_CONTROL)
 #define bfin_write_RSI_PWR_CTL(val)    bfin_write16(RSI_PWR_CONTROL, val)
 #define bfin_read_RSI_CLK_CTL()	       bfin_read16(RSI_CLK_CONTROL)
 #define bfin_write_RSI_CLK_CTL(val)    bfin_write16(RSI_CLK_CONTROL, val)
 #define bfin_read_RSI_ARGUMENT()       bfin_read32(RSI_ARGUMENT)
 #define bfin_write_RSI_ARGUMENT(val)   bfin_write32(RSI_ARGUMENT, val)
 #define bfin_read_RSI_COMMAND()        bfin_read16(RSI_COMMAND)
 #define bfin_write_RSI_COMMAND(val)    bfin_write16(RSI_COMMAND, val)
 #define bfin_read_RSI_RESP_CMD()       bfin_read16(RSI_RESP_CMD)
 #define bfin_write_RSI_RESP_CMD(val)   bfin_write16(RSI_RESP_CMD, val)
 #define bfin_read_RSI_RESPONSE0()      bfin_read32(RSI_RESPONSE0)
 #define bfin_write_RSI_RESPONSE0(val)  bfin_write32(RSI_RESPONSE0, val)
 #define bfin_read_RSI_RESPONSE1()      bfin_read32(RSI_RESPONSE1)
 #define bfin_write_RSI_RESPONSE1(val)  bfin_write32(RSI_RESPONSE1, val)
 #define bfin_read_RSI_RESPONSE2()      bfin_read32(RSI_RESPONSE2)
 #define bfin_write_RSI_RESPONSE2(val)  bfin_write32(RSI_RESPONSE2, val)
 #define bfin_read_RSI_RESPONSE3()      bfin_read32(RSI_RESPONSE3)
 #define bfin_write_RSI_RESPONSE3(val)  bfin_write32(RSI_RESPONSE3, val)
 #define bfin_read_RSI_DATA_TIMER()     bfin_read32(RSI_DATA_TIMER)
 #define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
 #define bfin_read_RSI_DATA_LGTH()      bfin_read16(RSI_DATA_LGTH)
 #define bfin_write_RSI_DATA_LGTH(val)  bfin_write16(RSI_DATA_LGTH, val)
 #define bfin_read_RSI_DATA_CTL()       bfin_read16(RSI_DATA_CONTROL)
 #define bfin_write_RSI_DATA_CTL(val)   bfin_write16(RSI_DATA_CONTROL, val)
 #define bfin_read_RSI_DATA_CNT()       bfin_read16(RSI_DATA_CNT)
 #define bfin_write_RSI_DATA_CNT(val)   bfin_write16(RSI_DATA_CNT, val)
 #define bfin_read_RSI_STATUS()         bfin_read32(RSI_STATUS)
 #define bfin_write_RSI_STATUS(val)     bfin_write32(RSI_STATUS, val)
 #define bfin_read_RSI_STATUS_CLR()     bfin_read16(RSI_STATUSCL)
 #define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val)
 #define bfin_read_RSI_MASK0()          bfin_read32(RSI_MASK0)
 #define bfin_write_RSI_MASK0(val)      bfin_write32(RSI_MASK0, val)
 #define bfin_read_RSI_MASK1()          bfin_read32(RSI_MASK1)
 #define bfin_write_RSI_MASK1(val)      bfin_write32(RSI_MASK1, val)
 #define bfin_read_RSI_FIFO_CNT()       bfin_read16(RSI_FIFO_CNT)
 #define bfin_write_RSI_FIFO_CNT(val)   bfin_write16(RSI_FIFO_CNT, val)
 #define bfin_read_RSI_CEATA_CTL()      bfin_read16(RSI_CEATA_CONTROL)
 #define bfin_write_RSI_CEATA_CTL(val)  bfin_write16(RSI_CEATA_CONTROL, val)
 #define bfin_read_RSI_FIFO()           bfin_read32(RSI_FIFO)
 #define bfin_write_RSI_FIFO(val)       bfin_write32(RSI_FIFO, val)
 #define bfin_read_RSI_E_STATUS()       bfin_read16(RSI_ESTAT)
 #define bfin_write_RSI_E_STATUS(val)   bfin_write16(RSI_ESTAT, val)
 #define bfin_read_RSI_E_MASK()         bfin_read16(RSI_EMASK)
 #define bfin_write_RSI_E_MASK(val)     bfin_write16(RSI_EMASK, val)
 #define bfin_read_RSI_CFG()            bfin_read16(RSI_CONFIG)
 #define bfin_write_RSI_CFG(val)        bfin_write16(RSI_CONFIG, val)
 #define bfin_read_RSI_RD_WAIT_EN()     bfin_read16(RSI_RD_WAIT_EN)
 #define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
 #define bfin_read_RSI_PID0()           bfin_read16(RSI_PID0)
 #define bfin_write_RSI_PID0(val)       bfin_write16(RSI_PID0, val)
 #define bfin_read_RSI_PID1()           bfin_read16(RSI_PID1)
 #define bfin_write_RSI_PID1(val)       bfin_write16(RSI_PID1, val)
 #define bfin_read_RSI_PID2()           bfin_read16(RSI_PID2)
 #define bfin_write_RSI_PID2(val)       bfin_write16(RSI_PID2, val)
 #define bfin_read_RSI_PID3()           bfin_read16(RSI_PID3)
 #define bfin_write_RSI_PID3(val)       bfin_write16(RSI_PID3, val)
 #define bfin_read_RSI_PID4()           bfin_read16(RSI_PID4)
 #define bfin_write_RSI_PID4(val)       bfin_write16(RSI_PID4, val)
 #define bfin_read_RSI_PID5()           bfin_read16(RSI_PID5)
 #define bfin_write_RSI_PID5(val)       bfin_write16(RSI_PID5, val)
 #define bfin_read_RSI_PID6()           bfin_read16(RSI_PID6)
 #define bfin_write_RSI_PID6(val)       bfin_write16(RSI_PID6, val)
 #define bfin_read_RSI_PID7()           bfin_read16(RSI_PID7)
 #define bfin_write_RSI_PID7(val)       bfin_write16(RSI_PID7, val)
 #endif /* _CDEF_BF516_H */
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
@ -1,7 +1,7 @@
 /*
 * Copyright 2008-2009 Analog Devices Inc.
 *
- * Licensed under the GPL-2 or later
+ * Licensed under the ADI BSD license or the GPL-2 (or later)
 */
 #ifndef _CDEF_BF518_H
@ -10,181 +10,10 @@
 /* include all Core registers and bit definitions */
 #include "defBF518.h"
-/* include core specific register pointer definitions */
+/* BF518 is BF516 + IEEE-1588 */
-#include <asm/cdef_LPBlackfin.h>
+#include "cdefBF516.h"
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF518 */
+/* PTP TSYNC Registers */
 /* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
 #include "cdefBF51x_base.h"
 /* The following are the #defines needed by ADSP-BF518 that are not in the common header */
 /* 10/100 Ethernet Controller	(0xFFC03000 - 0xFFC031FF) */
 #define bfin_read_EMAC_OPMODE()			bfin_read32(EMAC_OPMODE)
 #define bfin_write_EMAC_OPMODE(val)		bfin_write32(EMAC_OPMODE, val)
 #define bfin_read_EMAC_ADDRLO()			bfin_read32(EMAC_ADDRLO)
 #define bfin_write_EMAC_ADDRLO(val)		bfin_write32(EMAC_ADDRLO, val)
 #define bfin_read_EMAC_ADDRHI()			bfin_read32(EMAC_ADDRHI)
 #define bfin_write_EMAC_ADDRHI(val)		bfin_write32(EMAC_ADDRHI, val)
 #define bfin_read_EMAC_HASHLO()			bfin_read32(EMAC_HASHLO)
 #define bfin_write_EMAC_HASHLO(val)		bfin_write32(EMAC_HASHLO, val)
 #define bfin_read_EMAC_HASHHI()			bfin_read32(EMAC_HASHHI)
 #define bfin_write_EMAC_HASHHI(val)		bfin_write32(EMAC_HASHHI, val)
 #define bfin_read_EMAC_STAADD()			bfin_read32(EMAC_STAADD)
 #define bfin_write_EMAC_STAADD(val)		bfin_write32(EMAC_STAADD, val)
 #define bfin_read_EMAC_STADAT()			bfin_read32(EMAC_STADAT)
 #define bfin_write_EMAC_STADAT(val)		bfin_write32(EMAC_STADAT, val)
 #define bfin_read_EMAC_FLC()			bfin_read32(EMAC_FLC)
 #define bfin_write_EMAC_FLC(val)		bfin_write32(EMAC_FLC, val)
 #define bfin_read_EMAC_VLAN1()			bfin_read32(EMAC_VLAN1)
 #define bfin_write_EMAC_VLAN1(val)		bfin_write32(EMAC_VLAN1, val)
 #define bfin_read_EMAC_VLAN2()			bfin_read32(EMAC_VLAN2)
 #define bfin_write_EMAC_VLAN2(val)		bfin_write32(EMAC_VLAN2, val)
 #define bfin_read_EMAC_WKUP_CTL()		bfin_read32(EMAC_WKUP_CTL)
 #define bfin_write_EMAC_WKUP_CTL(val)		bfin_write32(EMAC_WKUP_CTL, val)
 #define bfin_read_EMAC_WKUP_FFMSK0()		bfin_read32(EMAC_WKUP_FFMSK0)
 #define bfin_write_EMAC_WKUP_FFMSK0(val)	bfin_write32(EMAC_WKUP_FFMSK0, val)
 #define bfin_read_EMAC_WKUP_FFMSK1()		bfin_read32(EMAC_WKUP_FFMSK1)
 #define bfin_write_EMAC_WKUP_FFMSK1(val)	bfin_write32(EMAC_WKUP_FFMSK1, val)
 #define bfin_read_EMAC_WKUP_FFMSK2()		bfin_read32(EMAC_WKUP_FFMSK2)
 #define bfin_write_EMAC_WKUP_FFMSK2(val)	bfin_write32(EMAC_WKUP_FFMSK2, val)
 #define bfin_read_EMAC_WKUP_FFMSK3()		bfin_read32(EMAC_WKUP_FFMSK3)
 #define bfin_write_EMAC_WKUP_FFMSK3(val)	bfin_write32(EMAC_WKUP_FFMSK3, val)
 #define bfin_read_EMAC_WKUP_FFCMD()		bfin_read32(EMAC_WKUP_FFCMD)
 #define bfin_write_EMAC_WKUP_FFCMD(val)		bfin_write32(EMAC_WKUP_FFCMD, val)
 #define bfin_read_EMAC_WKUP_FFOFF()		bfin_read32(EMAC_WKUP_FFOFF)
 #define bfin_write_EMAC_WKUP_FFOFF(val)		bfin_write32(EMAC_WKUP_FFOFF, val)
 #define bfin_read_EMAC_WKUP_FFCRC0()		bfin_read32(EMAC_WKUP_FFCRC0)
 #define bfin_write_EMAC_WKUP_FFCRC0(val)	bfin_write32(EMAC_WKUP_FFCRC0, val)
 #define bfin_read_EMAC_WKUP_FFCRC1()		bfin_read32(EMAC_WKUP_FFCRC1)
 #define bfin_write_EMAC_WKUP_FFCRC1(val)	bfin_write32(EMAC_WKUP_FFCRC1, val)
 #define bfin_read_EMAC_SYSCTL()			bfin_read32(EMAC_SYSCTL)
 #define bfin_write_EMAC_SYSCTL(val)		bfin_write32(EMAC_SYSCTL, val)
 #define bfin_read_EMAC_SYSTAT()			bfin_read32(EMAC_SYSTAT)
 #define bfin_write_EMAC_SYSTAT(val)		bfin_write32(EMAC_SYSTAT, val)
 #define bfin_read_EMAC_RX_STAT()		bfin_read32(EMAC_RX_STAT)
 #define bfin_write_EMAC_RX_STAT(val)		bfin_write32(EMAC_RX_STAT, val)
 #define bfin_read_EMAC_RX_STKY()		bfin_read32(EMAC_RX_STKY)
 #define bfin_write_EMAC_RX_STKY(val)		bfin_write32(EMAC_RX_STKY, val)
 #define bfin_read_EMAC_RX_IRQE()		bfin_read32(EMAC_RX_IRQE)
 #define bfin_write_EMAC_RX_IRQE(val)		bfin_write32(EMAC_RX_IRQE, val)
 #define bfin_read_EMAC_TX_STAT()		bfin_read32(EMAC_TX_STAT)
 #define bfin_write_EMAC_TX_STAT(val)		bfin_write32(EMAC_TX_STAT, val)
 #define bfin_read_EMAC_TX_STKY()		bfin_read32(EMAC_TX_STKY)
 #define bfin_write_EMAC_TX_STKY(val)		bfin_write32(EMAC_TX_STKY, val)
 #define bfin_read_EMAC_TX_IRQE()		bfin_read32(EMAC_TX_IRQE)
 #define bfin_write_EMAC_TX_IRQE(val)		bfin_write32(EMAC_TX_IRQE, val)
 #define bfin_read_EMAC_MMC_CTL()		bfin_read32(EMAC_MMC_CTL)
 #define bfin_write_EMAC_MMC_CTL(val)		bfin_write32(EMAC_MMC_CTL, val)
 #define bfin_read_EMAC_MMC_RIRQS()		bfin_read32(EMAC_MMC_RIRQS)
 #define bfin_write_EMAC_MMC_RIRQS(val)		bfin_write32(EMAC_MMC_RIRQS, val)
 #define bfin_read_EMAC_MMC_RIRQE()		bfin_read32(EMAC_MMC_RIRQE)
 #define bfin_write_EMAC_MMC_RIRQE(val)		bfin_write32(EMAC_MMC_RIRQE, val)
 #define bfin_read_EMAC_MMC_TIRQS()		bfin_read32(EMAC_MMC_TIRQS)
 #define bfin_write_EMAC_MMC_TIRQS(val)		bfin_write32(EMAC_MMC_TIRQS, val)
 #define bfin_read_EMAC_MMC_TIRQE()		bfin_read32(EMAC_MMC_TIRQE)
 #define bfin_write_EMAC_MMC_TIRQE(val)		bfin_write32(EMAC_MMC_TIRQE, val)
 #define bfin_read_EMAC_RXC_OK()			bfin_read32(EMAC_RXC_OK)
 #define bfin_write_EMAC_RXC_OK(val)		bfin_write32(EMAC_RXC_OK, val)
 #define bfin_read_EMAC_RXC_FCS()		bfin_read32(EMAC_RXC_FCS)
 #define bfin_write_EMAC_RXC_FCS(val)		bfin_write32(EMAC_RXC_FCS, val)
 #define bfin_read_EMAC_RXC_ALIGN()		bfin_read32(EMAC_RXC_ALIGN)
 #define bfin_write_EMAC_RXC_ALIGN(val)		bfin_write32(EMAC_RXC_ALIGN, val)
 #define bfin_read_EMAC_RXC_OCTET()		bfin_read32(EMAC_RXC_OCTET)
 #define bfin_write_EMAC_RXC_OCTET(val)		bfin_write32(EMAC_RXC_OCTET, val)
 #define bfin_read_EMAC_RXC_DMAOVF()		bfin_read32(EMAC_RXC_DMAOVF)
 #define bfin_write_EMAC_RXC_DMAOVF(val)		bfin_write32(EMAC_RXC_DMAOVF, val)
 #define bfin_read_EMAC_RXC_UNICST()		bfin_read32(EMAC_RXC_UNICST)
 #define bfin_write_EMAC_RXC_UNICST(val)		bfin_write32(EMAC_RXC_UNICST, val)
 #define bfin_read_EMAC_RXC_MULTI()		bfin_read32(EMAC_RXC_MULTI)
 #define bfin_write_EMAC_RXC_MULTI(val)		bfin_write32(EMAC_RXC_MULTI, val)
 #define bfin_read_EMAC_RXC_BROAD()		bfin_read32(EMAC_RXC_BROAD)
 #define bfin_write_EMAC_RXC_BROAD(val)		bfin_write32(EMAC_RXC_BROAD, val)
 #define bfin_read_EMAC_RXC_LNERRI()		bfin_read32(EMAC_RXC_LNERRI)
 #define bfin_write_EMAC_RXC_LNERRI(val)		bfin_write32(EMAC_RXC_LNERRI, val)
 #define bfin_read_EMAC_RXC_LNERRO()		bfin_read32(EMAC_RXC_LNERRO)
 #define bfin_write_EMAC_RXC_LNERRO(val)		bfin_write32(EMAC_RXC_LNERRO, val)
 #define bfin_read_EMAC_RXC_LONG()		bfin_read32(EMAC_RXC_LONG)
 #define bfin_write_EMAC_RXC_LONG(val)		bfin_write32(EMAC_RXC_LONG, val)
 #define bfin_read_EMAC_RXC_MACCTL()		bfin_read32(EMAC_RXC_MACCTL)
 #define bfin_write_EMAC_RXC_MACCTL(val)		bfin_write32(EMAC_RXC_MACCTL, val)
 #define bfin_read_EMAC_RXC_OPCODE()		bfin_read32(EMAC_RXC_OPCODE)
 #define bfin_write_EMAC_RXC_OPCODE(val)		bfin_write32(EMAC_RXC_OPCODE, val)
 #define bfin_read_EMAC_RXC_PAUSE()		bfin_read32(EMAC_RXC_PAUSE)
 #define bfin_write_EMAC_RXC_PAUSE(val)		bfin_write32(EMAC_RXC_PAUSE, val)
 #define bfin_read_EMAC_RXC_ALLFRM()		bfin_read32(EMAC_RXC_ALLFRM)
 #define bfin_write_EMAC_RXC_ALLFRM(val)		bfin_write32(EMAC_RXC_ALLFRM, val)
 #define bfin_read_EMAC_RXC_ALLOCT()		bfin_read32(EMAC_RXC_ALLOCT)
 #define bfin_write_EMAC_RXC_ALLOCT(val)		bfin_write32(EMAC_RXC_ALLOCT, val)
 #define bfin_read_EMAC_RXC_TYPED()		bfin_read32(EMAC_RXC_TYPED)
 #define bfin_write_EMAC_RXC_TYPED(val)		bfin_write32(EMAC_RXC_TYPED, val)
 #define bfin_read_EMAC_RXC_SHORT()		bfin_read32(EMAC_RXC_SHORT)
 #define bfin_write_EMAC_RXC_SHORT(val)		bfin_write32(EMAC_RXC_SHORT, val)
 #define bfin_read_EMAC_RXC_EQ64()		bfin_read32(EMAC_RXC_EQ64)
 #define bfin_write_EMAC_RXC_EQ64(val)		bfin_write32(EMAC_RXC_EQ64, val)
 #define bfin_read_EMAC_RXC_LT128()		bfin_read32(EMAC_RXC_LT128)
 #define bfin_write_EMAC_RXC_LT128(val)		bfin_write32(EMAC_RXC_LT128, val)
 #define bfin_read_EMAC_RXC_LT256()		bfin_read32(EMAC_RXC_LT256)
 #define bfin_write_EMAC_RXC_LT256(val)		bfin_write32(EMAC_RXC_LT256, val)
 #define bfin_read_EMAC_RXC_LT512()		bfin_read32(EMAC_RXC_LT512)
 #define bfin_write_EMAC_RXC_LT512(val)		bfin_write32(EMAC_RXC_LT512, val)
 #define bfin_read_EMAC_RXC_LT1024()		bfin_read32(EMAC_RXC_LT1024)
 #define bfin_write_EMAC_RXC_LT1024(val)		bfin_write32(EMAC_RXC_LT1024, val)
 #define bfin_read_EMAC_RXC_GE1024()		bfin_read32(EMAC_RXC_GE1024)
 #define bfin_write_EMAC_RXC_GE1024(val)		bfin_write32(EMAC_RXC_GE1024, val)
 #define bfin_read_EMAC_TXC_OK()			bfin_read32(EMAC_TXC_OK)
 #define bfin_write_EMAC_TXC_OK(val)		bfin_write32(EMAC_TXC_OK, val)
 #define bfin_read_EMAC_TXC_1COL()		bfin_read32(EMAC_TXC_1COL)
 #define bfin_write_EMAC_TXC_1COL(val)		bfin_write32(EMAC_TXC_1COL, val)
 #define bfin_read_EMAC_TXC_GT1COL()		bfin_read32(EMAC_TXC_GT1COL)
 #define bfin_write_EMAC_TXC_GT1COL(val)		bfin_write32(EMAC_TXC_GT1COL, val)
 #define bfin_read_EMAC_TXC_OCTET()		bfin_read32(EMAC_TXC_OCTET)
 #define bfin_write_EMAC_TXC_OCTET(val)		bfin_write32(EMAC_TXC_OCTET, val)
 #define bfin_read_EMAC_TXC_DEFER()		bfin_read32(EMAC_TXC_DEFER)
 #define bfin_write_EMAC_TXC_DEFER(val)		bfin_write32(EMAC_TXC_DEFER, val)
 #define bfin_read_EMAC_TXC_LATECL()		bfin_read32(EMAC_TXC_LATECL)
 #define bfin_write_EMAC_TXC_LATECL(val)		bfin_write32(EMAC_TXC_LATECL, val)
 #define bfin_read_EMAC_TXC_XS_COL()		bfin_read32(EMAC_TXC_XS_COL)
 #define bfin_write_EMAC_TXC_XS_COL(val)		bfin_write32(EMAC_TXC_XS_COL, val)
 #define bfin_read_EMAC_TXC_DMAUND()		bfin_read32(EMAC_TXC_DMAUND)
 #define bfin_write_EMAC_TXC_DMAUND(val)		bfin_write32(EMAC_TXC_DMAUND, val)
 #define bfin_read_EMAC_TXC_CRSERR()		bfin_read32(EMAC_TXC_CRSERR)
 #define bfin_write_EMAC_TXC_CRSERR(val)		bfin_write32(EMAC_TXC_CRSERR, val)
 #define bfin_read_EMAC_TXC_UNICST()		bfin_read32(EMAC_TXC_UNICST)
 #define bfin_write_EMAC_TXC_UNICST(val)		bfin_write32(EMAC_TXC_UNICST, val)
 #define bfin_read_EMAC_TXC_MULTI()		bfin_read32(EMAC_TXC_MULTI)
 #define bfin_write_EMAC_TXC_MULTI(val)		bfin_write32(EMAC_TXC_MULTI, val)
 #define bfin_read_EMAC_TXC_BROAD()		bfin_read32(EMAC_TXC_BROAD)
 #define bfin_write_EMAC_TXC_BROAD(val)		bfin_write32(EMAC_TXC_BROAD, val)
 #define bfin_read_EMAC_TXC_XS_DFR()		bfin_read32(EMAC_TXC_XS_DFR)
 #define bfin_write_EMAC_TXC_XS_DFR(val)		bfin_write32(EMAC_TXC_XS_DFR, val)
 #define bfin_read_EMAC_TXC_MACCTL()		bfin_read32(EMAC_TXC_MACCTL)
 #define bfin_write_EMAC_TXC_MACCTL(val)		bfin_write32(EMAC_TXC_MACCTL, val)
 #define bfin_read_EMAC_TXC_ALLFRM()		bfin_read32(EMAC_TXC_ALLFRM)
 #define bfin_write_EMAC_TXC_ALLFRM(val)		bfin_write32(EMAC_TXC_ALLFRM, val)
 #define bfin_read_EMAC_TXC_ALLOCT()		bfin_read32(EMAC_TXC_ALLOCT)
 #define bfin_write_EMAC_TXC_ALLOCT(val)		bfin_write32(EMAC_TXC_ALLOCT, val)
 #define bfin_read_EMAC_TXC_EQ64()		bfin_read32(EMAC_TXC_EQ64)
 #define bfin_write_EMAC_TXC_EQ64(val)		bfin_write32(EMAC_TXC_EQ64, val)
 #define bfin_read_EMAC_TXC_LT128()		bfin_read32(EMAC_TXC_LT128)
 #define bfin_write_EMAC_TXC_LT128(val)		bfin_write32(EMAC_TXC_LT128, val)
 #define bfin_read_EMAC_TXC_LT256()		bfin_read32(EMAC_TXC_LT256)
 #define bfin_write_EMAC_TXC_LT256(val)		bfin_write32(EMAC_TXC_LT256, val)
 #define bfin_read_EMAC_TXC_LT512()		bfin_read32(EMAC_TXC_LT512)
 #define bfin_write_EMAC_TXC_LT512(val)		bfin_write32(EMAC_TXC_LT512, val)
 #define bfin_read_EMAC_TXC_LT1024()		bfin_read32(EMAC_TXC_LT1024)
 #define bfin_write_EMAC_TXC_LT1024(val)		bfin_write32(EMAC_TXC_LT1024, val)
 #define bfin_read_EMAC_TXC_GE1024()		bfin_read32(EMAC_TXC_GE1024)
 #define bfin_write_EMAC_TXC_GE1024(val)		bfin_write32(EMAC_TXC_GE1024, val)
 #define bfin_read_EMAC_TXC_ABORT()		bfin_read32(EMAC_TXC_ABORT)
 #define bfin_write_EMAC_TXC_ABORT(val)		bfin_write32(EMAC_TXC_ABORT, val)
 #define bfin_read_EMAC_PTP_CTL()                bfin_read16(EMAC_PTP_CTL)
 #define bfin_write_EMAC_PTP_CTL(val)            bfin_write16(EMAC_PTP_CTL, val)
@ -227,72 +56,4 @@
 #define bfin_read_EMAC_PTP_PPS_PERIOD()         bfin_read32(EMAC_PTP_PPS_PERIOD)
 #define bfin_write_EMAC_PTP_PPS_PERIOD(val)     bfin_write32(EMAC_PTP_PPS_PERIOD, val)
 /* Removable Storage Interface Registers */
 #define bfin_read_RSI_PWR_CTL()        bfin_read16(RSI_PWR_CONTROL)
 #define bfin_write_RSI_PWR_CTL(val)    bfin_write16(RSI_PWR_CONTROL, val)
 #define bfin_read_RSI_CLK_CTL()	       bfin_read16(RSI_CLK_CONTROL)
 #define bfin_write_RSI_CLK_CTL(val)    bfin_write16(RSI_CLK_CONTROL, val)
 #define bfin_read_RSI_ARGUMENT()       bfin_read32(RSI_ARGUMENT)
 #define bfin_write_RSI_ARGUMENT(val)   bfin_write32(RSI_ARGUMENT, val)
 #define bfin_read_RSI_COMMAND()        bfin_read16(RSI_COMMAND)
 #define bfin_write_RSI_COMMAND(val)    bfin_write16(RSI_COMMAND, val)
 #define bfin_read_RSI_RESP_CMD()       bfin_read16(RSI_RESP_CMD)
 #define bfin_write_RSI_RESP_CMD(val)   bfin_write16(RSI_RESP_CMD, val)
 #define bfin_read_RSI_RESPONSE0()      bfin_read32(RSI_RESPONSE0)
 #define bfin_write_RSI_RESPONSE0(val)  bfin_write32(RSI_RESPONSE0, val)
 #define bfin_read_RSI_RESPONSE1()      bfin_read32(RSI_RESPONSE1)
 #define bfin_write_RSI_RESPONSE1(val)  bfin_write32(RSI_RESPONSE1, val)
 #define bfin_read_RSI_RESPONSE2()      bfin_read32(RSI_RESPONSE2)
 #define bfin_write_RSI_RESPONSE2(val)  bfin_write32(RSI_RESPONSE2, val)
 #define bfin_read_RSI_RESPONSE3()      bfin_read32(RSI_RESPONSE3)
 #define bfin_write_RSI_RESPONSE3(val)  bfin_write32(RSI_RESPONSE3, val)
 #define bfin_read_RSI_DATA_TIMER()     bfin_read32(RSI_DATA_TIMER)
 #define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
 #define bfin_read_RSI_DATA_LGTH()      bfin_read16(RSI_DATA_LGTH)
 #define bfin_write_RSI_DATA_LGTH(val)  bfin_write16(RSI_DATA_LGTH, val)
 #define bfin_read_RSI_DATA_CTL()       bfin_read16(RSI_DATA_CONTROL)
 #define bfin_write_RSI_DATA_CTL(val)   bfin_write16(RSI_DATA_CONTROL, val)
 #define bfin_read_RSI_DATA_CNT()       bfin_read16(RSI_DATA_CNT)
 #define bfin_write_RSI_DATA_CNT(val)   bfin_write16(RSI_DATA_CNT, val)
 #define bfin_read_RSI_STATUS()         bfin_read32(RSI_STATUS)
 #define bfin_write_RSI_STATUS(val)     bfin_write32(RSI_STATUS, val)
 #define bfin_read_RSI_STATUS_CLR()     bfin_read16(RSI_STATUSCL)
 #define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val)
 #define bfin_read_RSI_MASK0()          bfin_read32(RSI_MASK0)
 #define bfin_write_RSI_MASK0(val)      bfin_write32(RSI_MASK0, val)
 #define bfin_read_RSI_MASK1()          bfin_read32(RSI_MASK1)
 #define bfin_write_RSI_MASK1(val)      bfin_write32(RSI_MASK1, val)
 #define bfin_read_RSI_FIFO_CNT()       bfin_read16(RSI_FIFO_CNT)
 #define bfin_write_RSI_FIFO_CNT(val)   bfin_write16(RSI_FIFO_CNT, val)
 #define bfin_read_RSI_CEATA_CTL()      bfin_read16(RSI_CEATA_CONTROL)
 #define bfin_write_RSI_CEATA_CTL(val)  bfin_write16(RSI_CEATA_CONTROL, val)
 #define bfin_read_RSI_FIFO()           bfin_read32(RSI_FIFO)
 #define bfin_write_RSI_FIFO(val)       bfin_write32(RSI_FIFO, val)
 #define bfin_read_RSI_E_STATUS()       bfin_read16(RSI_ESTAT)
 #define bfin_write_RSI_E_STATUS(val)   bfin_write16(RSI_ESTAT, val)
 #define bfin_read_RSI_E_MASK()         bfin_read16(RSI_EMASK)
 #define bfin_write_RSI_E_MASK(val)     bfin_write16(RSI_EMASK, val)
 #define bfin_read_RSI_CFG()            bfin_read16(RSI_CONFIG)
 #define bfin_write_RSI_CFG(val)        bfin_write16(RSI_CONFIG, val)
 #define bfin_read_RSI_RD_WAIT_EN()     bfin_read16(RSI_RD_WAIT_EN)
 #define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
 #define bfin_read_RSI_PID0()           bfin_read16(RSI_PID0)
 #define bfin_write_RSI_PID0(val)       bfin_write16(RSI_PID0, val)
 #define bfin_read_RSI_PID1()           bfin_read16(RSI_PID1)
 #define bfin_write_RSI_PID1(val)       bfin_write16(RSI_PID1, val)
 #define bfin_read_RSI_PID2()           bfin_read16(RSI_PID2)
 #define bfin_write_RSI_PID2(val)       bfin_write16(RSI_PID2, val)
 #define bfin_read_RSI_PID3()           bfin_read16(RSI_PID3)
 #define bfin_write_RSI_PID3(val)       bfin_write16(RSI_PID3, val)
 #define bfin_read_RSI_PID4()           bfin_read16(RSI_PID4)
 #define bfin_write_RSI_PID4(val)       bfin_write16(RSI_PID4, val)
 #define bfin_read_RSI_PID5()           bfin_read16(RSI_PID5)
 #define bfin_write_RSI_PID5(val)       bfin_write16(RSI_PID5, val)
 #define bfin_read_RSI_PID6()           bfin_read16(RSI_PID6)
 #define bfin_write_RSI_PID6(val)       bfin_write16(RSI_PID6, val)
 #define bfin_read_RSI_PID7()           bfin_read16(RSI_PID7)
 #define bfin_write_RSI_PID7(val)       bfin_write16(RSI_PID7, val)
 #endif /* _CDEF_BF518_H */
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
@ -131,23 +131,6 @@
 #define bfin_write_UART0_GCTL(val)		bfin_write16(UART0_GCTL, val)
 /* SPI Controller		(0xFFC00500 - 0xFFC005FF)									*/
 #define bfin_read_SPI_CTL()			bfin_read16(SPI_CTL)
 #define bfin_write_SPI_CTL(val)			bfin_write16(SPI_CTL, val)
 #define bfin_read_SPI_FLG()			bfin_read16(SPI_FLG)
 #define bfin_write_SPI_FLG(val)			bfin_write16(SPI_FLG, val)
 #define bfin_read_SPI_STAT()			bfin_read16(SPI_STAT)
 #define bfin_write_SPI_STAT(val)		bfin_write16(SPI_STAT, val)
 #define bfin_read_SPI_TDBR()			bfin_read16(SPI_TDBR)
 #define bfin_write_SPI_TDBR(val)		bfin_write16(SPI_TDBR, val)
 #define bfin_read_SPI_RDBR()			bfin_read16(SPI_RDBR)
 #define bfin_write_SPI_RDBR(val)		bfin_write16(SPI_RDBR, val)
 #define bfin_read_SPI_BAUD()			bfin_read16(SPI_BAUD)
 #define bfin_write_SPI_BAUD(val)		bfin_write16(SPI_BAUD, val)
 #define bfin_read_SPI_SHADOW()			bfin_read16(SPI_SHADOW)
 #define bfin_write_SPI_SHADOW(val)		bfin_write16(SPI_SHADOW, val)
 /* TIMER0-7 Registers		(0xFFC00600 - 0xFFC006FF)								*/
 #define bfin_read_TIMER0_CONFIG()		bfin_read16(TIMER0_CONFIG)
 #define bfin_write_TIMER0_CONFIG(val)		bfin_write16(TIMER0_CONFIG, val)
@ -844,6 +827,7 @@
 #define bfin_write_PPI_CONTROL(val)		bfin_write16(PPI_CONTROL, val)
 #define bfin_read_PPI_STATUS()			bfin_read16(PPI_STATUS)
 #define bfin_write_PPI_STATUS(val)		bfin_write16(PPI_STATUS, val)
 #define bfin_clear_PPI_STATUS()			bfin_write_PPI_STATUS(0xFFFF)
 #define bfin_read_PPI_DELAY()			bfin_read16(PPI_DELAY)
 #define bfin_write_PPI_DELAY(val)		bfin_write16(PPI_DELAY, val)
 #define bfin_read_PPI_COUNT()			bfin_read16(PPI_COUNT)
@ -1062,17 +1046,6 @@
 #define bfin_read_CNT_MIN()			bfin_read32(CNT_MIN)
 #define bfin_write_CNT_MIN(val)			bfin_write32(CNT_MIN, val)
 /* OTP/FUSE Registers */
 #define bfin_read_OTP_CONTROL()			bfin_read16(OTP_CONTROL)
 #define bfin_write_OTP_CONTROL(val)		bfin_write16(OTP_CONTROL, val)
 #define bfin_read_OTP_BEN()			bfin_read16(OTP_BEN)
 #define bfin_write_OTP_BEN(val)			bfin_write16(OTP_BEN, val)
 #define bfin_read_OTP_STATUS()			bfin_read16(OTP_STATUS)
 #define bfin_write_OTP_STATUS(val)		bfin_write16(OTP_STATUS, val)
 #define bfin_read_OTP_TIMING()			bfin_read32(OTP_TIMING)
 #define bfin_write_OTP_TIMING(val)		bfin_write32(OTP_TIMING, val)
 /* Security Registers */
 #define bfin_read_SECURE_SYSSWT()		bfin_read32(SECURE_SYSSWT)
@ -1082,52 +1055,6 @@
 #define bfin_read_SECURE_STATUS()		bfin_read16(SECURE_STATUS)
 #define bfin_write_SECURE_STATUS(val)		bfin_write16(SECURE_STATUS, val)
 /* OTP Read/Write Data Buffer Registers */
 #define bfin_read_OTP_DATA0()			bfin_read32(OTP_DATA0)
 #define bfin_write_OTP_DATA0(val)		bfin_write32(OTP_DATA0, val)
 #define bfin_read_OTP_DATA1()			bfin_read32(OTP_DATA1)
 #define bfin_write_OTP_DATA1(val)		bfin_write32(OTP_DATA1, val)
 #define bfin_read_OTP_DATA2()			bfin_read32(OTP_DATA2)
 #define bfin_write_OTP_DATA2(val)		bfin_write32(OTP_DATA2, val)
 #define bfin_read_OTP_DATA3()			bfin_read32(OTP_DATA3)
 #define bfin_write_OTP_DATA3(val)		bfin_write32(OTP_DATA3, val)
 /* NFC Registers */
 #define bfin_read_NFC_CTL()			bfin_read16(NFC_CTL)
 #define bfin_write_NFC_CTL(val)			bfin_write16(NFC_CTL, val)
 #define bfin_read_NFC_STAT()			bfin_read16(NFC_STAT)
 #define bfin_write_NFC_STAT(val)		bfin_write16(NFC_STAT, val)
 #define bfin_read_NFC_IRQSTAT()			bfin_read16(NFC_IRQSTAT)
 #define bfin_write_NFC_IRQSTAT(val)		bfin_write16(NFC_IRQSTAT, val)
 #define bfin_read_NFC_IRQMASK()			bfin_read16(NFC_IRQMASK)
 #define bfin_write_NFC_IRQMASK(val)		bfin_write16(NFC_IRQMASK, val)
 #define bfin_read_NFC_ECC0()			bfin_read16(NFC_ECC0)
 #define bfin_write_NFC_ECC0(val)		bfin_write16(NFC_ECC0, val)
 #define bfin_read_NFC_ECC1()			bfin_read16(NFC_ECC1)
 #define bfin_write_NFC_ECC1(val)		bfin_write16(NFC_ECC1, val)
 #define bfin_read_NFC_ECC2()			bfin_read16(NFC_ECC2)
 #define bfin_write_NFC_ECC2(val)		bfin_write16(NFC_ECC2, val)
 #define bfin_read_NFC_ECC3()			bfin_read16(NFC_ECC3)
 #define bfin_write_NFC_ECC3(val)		bfin_write16(NFC_ECC3, val)
 #define bfin_read_NFC_COUNT()			bfin_read16(NFC_COUNT)
 #define bfin_write_NFC_COUNT(val)		bfin_write16(NFC_COUNT, val)
 #define bfin_read_NFC_RST()			bfin_read16(NFC_RST)
 #define bfin_write_NFC_RST(val)			bfin_write16(NFC_RST, val)
 #define bfin_read_NFC_PGCTL()			bfin_read16(NFC_PGCTL)
 #define bfin_write_NFC_PGCTL(val)		bfin_write16(NFC_PGCTL, val)
 #define bfin_read_NFC_READ()			bfin_read16(NFC_READ)
 #define bfin_write_NFC_READ(val)		bfin_write16(NFC_READ, val)
 #define bfin_read_NFC_ADDR()			bfin_read16(NFC_ADDR)
 #define bfin_write_NFC_ADDR(val)		bfin_write16(NFC_ADDR, val)
 #define bfin_read_NFC_CMD()			bfin_read16(NFC_CMD)
 #define bfin_write_NFC_CMD(val)			bfin_write16(NFC_CMD, val)
 #define bfin_read_NFC_DATA_WR()			bfin_read16(NFC_DATA_WR)
 #define bfin_write_NFC_DATA_WR(val)		bfin_write16(NFC_DATA_WR, val)
 #define bfin_read_NFC_DATA_RD()			bfin_read16(NFC_DATA_RD)
 #define bfin_write_NFC_DATA_RD(val)		bfin_write16(NFC_DATA_RD, val)
 /* These need to be last due to the cdef/linux inter-dependencies */
 #include <asm/irq.h>
--- a/arch/blackfin/mach-bf518/include/mach/defBF514.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF514.h
@ -7,49 +7,8 @@
 #ifndef _DEF_BF514_H
 #define _DEF_BF514_H
-/* Include all Core registers and bit definitions */
+/* BF514 is BF512 + RSI */
-#include <asm/def_LPBlackfin.h>
+#include "defBF512.h"
 /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */
 /* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
 #include "defBF51x_base.h"
 /* The following are the #defines needed by ADSP-BF514 that are not in the common header */
 /* SDH Registers */
 #define SDH_PWR_CTL                    0xFFC03900 /* SDH Power Control */
 #define SDH_CLK_CTL                    0xFFC03904 /* SDH Clock Control */
 #define SDH_ARGUMENT                   0xFFC03908 /* SDH Argument */
 #define SDH_COMMAND                    0xFFC0390C /* SDH Command */
 #define SDH_RESP_CMD                   0xFFC03910 /* SDH Response Command */
 #define SDH_RESPONSE0                  0xFFC03914 /* SDH Response0 */
 #define SDH_RESPONSE1                  0xFFC03918 /* SDH Response1 */
 #define SDH_RESPONSE2                  0xFFC0391C /* SDH Response2 */
 #define SDH_RESPONSE3                  0xFFC03920 /* SDH Response3 */
 #define SDH_DATA_TIMER                 0xFFC03924 /* SDH Data Timer */
 #define SDH_DATA_LGTH                  0xFFC03928 /* SDH Data Length */
 #define SDH_DATA_CTL                   0xFFC0392C /* SDH Data Control */
 #define SDH_DATA_CNT                   0xFFC03930 /* SDH Data Counter */
 #define SDH_STATUS                     0xFFC03934 /* SDH Status */
 #define SDH_STATUS_CLR                 0xFFC03938 /* SDH Status Clear */
 #define SDH_MASK0                      0xFFC0393C /* SDH Interrupt0 Mask */
 #define SDH_MASK1                      0xFFC03940 /* SDH Interrupt1 Mask */
 #define SDH_FIFO_CNT                   0xFFC03948 /* SDH FIFO Counter */
 #define SDH_FIFO                       0xFFC03980 /* SDH Data FIFO */
 #define SDH_E_STATUS                   0xFFC039C0 /* SDH Exception Status */
 #define SDH_E_MASK                     0xFFC039C4 /* SDH Exception Mask */
 #define SDH_CFG                        0xFFC039C8 /* SDH Configuration */
 #define SDH_RD_WAIT_EN                 0xFFC039CC /* SDH Read Wait Enable */
 #define SDH_PID0                       0xFFC039D0 /* SDH Peripheral Identification0 */
 #define SDH_PID1                       0xFFC039D4 /* SDH Peripheral Identification1 */
 #define SDH_PID2                       0xFFC039D8 /* SDH Peripheral Identification2 */
 #define SDH_PID3                       0xFFC039DC /* SDH Peripheral Identification3 */
 #define SDH_PID4                       0xFFC039E0 /* SDH Peripheral Identification4 */
 #define SDH_PID5                       0xFFC039E4 /* SDH Peripheral Identification5 */
 #define SDH_PID6                       0xFFC039E8 /* SDH Peripheral Identification6 */
 #define SDH_PID7                       0xFFC039EC /* SDH Peripheral Identification7 */
 /* Removable Storage Interface Registers */
--- a/arch/blackfin/mach-bf518/include/mach/defBF516.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF516.h
@ -7,13 +7,8 @@
 #ifndef _DEF_BF516_H
 #define _DEF_BF516_H
-/* Include all Core registers and bit definitions */
+/* BF516 is BF514 + EMAC */
-#include <asm/def_LPBlackfin.h>
+#include "defBF514.h"
 /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF516 */
 /* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
 #include "defBF51x_base.h"
 /* The following are the #defines needed by ADSP-BF516 that are not in the common header */
 /* 10/100 Ethernet Controller	(0xFFC03000 - 0xFFC031FF) */
@ -394,208 +389,4 @@
 #define	TX_GE1024_CNT     0x00200000    /* 1024-Max-Byte TX Frames Sent                           */
 #define	TX_ABORT_CNT      0x00400000    /* TX Frames Aborted                                      */
 /* SDH Registers */
 #define SDH_PWR_CTL                    0xFFC03900 /* SDH Power Control */
 #define SDH_CLK_CTL                    0xFFC03904 /* SDH Clock Control */
 #define SDH_ARGUMENT                   0xFFC03908 /* SDH Argument */
 #define SDH_COMMAND                    0xFFC0390C /* SDH Command */
 #define SDH_RESP_CMD                   0xFFC03910 /* SDH Response Command */
 #define SDH_RESPONSE0                  0xFFC03914 /* SDH Response0 */
 #define SDH_RESPONSE1                  0xFFC03918 /* SDH Response1 */
 #define SDH_RESPONSE2                  0xFFC0391C /* SDH Response2 */
 #define SDH_RESPONSE3                  0xFFC03920 /* SDH Response3 */
 #define SDH_DATA_TIMER                 0xFFC03924 /* SDH Data Timer */
 #define SDH_DATA_LGTH                  0xFFC03928 /* SDH Data Length */
 #define SDH_DATA_CTL                   0xFFC0392C /* SDH Data Control */
 #define SDH_DATA_CNT                   0xFFC03930 /* SDH Data Counter */
 #define SDH_STATUS                     0xFFC03934 /* SDH Status */
 #define SDH_STATUS_CLR                 0xFFC03938 /* SDH Status Clear */
 #define SDH_MASK0                      0xFFC0393C /* SDH Interrupt0 Mask */
 #define SDH_MASK1                      0xFFC03940 /* SDH Interrupt1 Mask */
 #define SDH_FIFO_CNT                   0xFFC03948 /* SDH FIFO Counter */
 #define SDH_FIFO                       0xFFC03980 /* SDH Data FIFO */
 #define SDH_E_STATUS                   0xFFC039C0 /* SDH Exception Status */
 #define SDH_E_MASK                     0xFFC039C4 /* SDH Exception Mask */
 #define SDH_CFG                        0xFFC039C8 /* SDH Configuration */
 #define SDH_RD_WAIT_EN                 0xFFC039CC /* SDH Read Wait Enable */
 #define SDH_PID0                       0xFFC039D0 /* SDH Peripheral Identification0 */
 #define SDH_PID1                       0xFFC039D4 /* SDH Peripheral Identification1 */
 #define SDH_PID2                       0xFFC039D8 /* SDH Peripheral Identification2 */
 #define SDH_PID3                       0xFFC039DC /* SDH Peripheral Identification3 */
 #define SDH_PID4                       0xFFC039E0 /* SDH Peripheral Identification4 */
 #define SDH_PID5                       0xFFC039E4 /* SDH Peripheral Identification5 */
 #define SDH_PID6                       0xFFC039E8 /* SDH Peripheral Identification6 */
 #define SDH_PID7                       0xFFC039EC /* SDH Peripheral Identification7 */
 /* Removable Storage Interface Registers */
 #define RSI_PWR_CONTROL                0xFFC03800 /* RSI Power Control Register */
 #define RSI_CLK_CONTROL                0xFFC03804 /* RSI Clock Control Register */
 #define RSI_ARGUMENT                   0xFFC03808 /* RSI Argument Register */
 #define RSI_COMMAND                    0xFFC0380C /* RSI Command Register */
 #define RSI_RESP_CMD                   0xFFC03810 /* RSI Response Command Register */
 #define RSI_RESPONSE0                  0xFFC03814 /* RSI Response Register */
 #define RSI_RESPONSE1                  0xFFC03818 /* RSI Response Register */
 #define RSI_RESPONSE2                  0xFFC0381C /* RSI Response Register */
 #define RSI_RESPONSE3                  0xFFC03820 /* RSI Response Register */
 #define RSI_DATA_TIMER                 0xFFC03824 /* RSI Data Timer Register */
 #define RSI_DATA_LGTH                  0xFFC03828 /* RSI Data Length Register */
 #define RSI_DATA_CONTROL               0xFFC0382C /* RSI Data Control Register */
 #define RSI_DATA_CNT                   0xFFC03830 /* RSI Data Counter Register */
 #define RSI_STATUS                     0xFFC03834 /* RSI Status Register */
 #define RSI_STATUSCL                   0xFFC03838 /* RSI Status Clear Register */
 #define RSI_MASK0                      0xFFC0383C /* RSI Interrupt 0 Mask Register */
 #define RSI_MASK1                      0xFFC03840 /* RSI Interrupt 1 Mask Register */
 #define RSI_FIFO_CNT                   0xFFC03848 /* RSI FIFO Counter Register */
 #define RSI_CEATA_CONTROL              0xFFC0384C /* RSI CEATA Register */
 #define RSI_FIFO                       0xFFC03880 /* RSI Data FIFO Register */
 #define RSI_ESTAT                      0xFFC038C0 /* RSI Exception Status Register */
 #define RSI_EMASK                      0xFFC038C4 /* RSI Exception Mask Register */
 #define RSI_CONFIG                     0xFFC038C8 /* RSI Configuration Register */
 #define RSI_RD_WAIT_EN                 0xFFC038CC /* RSI Read Wait Enable Register */
 #define RSI_PID0                       0xFFC03FE0 /* RSI Peripheral ID Register 0 */
 #define RSI_PID1                       0xFFC03FE4 /* RSI Peripheral ID Register 1 */
 #define RSI_PID2                       0xFFC03FE8 /* RSI Peripheral ID Register 2 */
 #define RSI_PID3                       0xFFC03FEC /* RSI Peripheral ID Register 3 */
 #define RSI_PID4                       0xFFC03FF0 /* RSI Peripheral ID Register 4 */
 #define RSI_PID5                       0xFFC03FF4 /* RSI Peripheral ID Register 5 */
 #define RSI_PID6                       0xFFC03FF8 /* RSI Peripheral ID Register 6 */
 #define RSI_PID7                       0xFFC03FFC /* RSI Peripheral ID Register 7 */
 /* ********************************************************** */
 /*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
 /*     and MULTI BIT READ MACROS                              */
 /* ********************************************************** */
 /* Bit masks for SDH_COMMAND */
 #define                   CMD_IDX  0x3f       /* Command Index */
 #define                   CMD_RSP  0x40       /* Response */
 #define                 CMD_L_RSP  0x80       /* Long Response */
 #define                 CMD_INT_E  0x100      /* Command Interrupt */
 #define                CMD_PEND_E  0x200      /* Command Pending */
 #define                     CMD_E  0x400      /* Command Enable */
 /* Bit masks for SDH_PWR_CTL */
 #define                    PWR_ON  0x3        /* Power On */
 #if 0
 #define                       TBD  0x3c       /* TBD */
 #endif
 #define                 SD_CMD_OD  0x40       /* Open Drain Output */
 #define                   ROD_CTL  0x80       /* Rod Control */
 /* Bit masks for SDH_CLK_CTL */
 #define                    CLKDIV  0xff       /* MC_CLK Divisor */
 #define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
 #define                  PWR_SV_E  0x200      /* Power Save Enable */
 #define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
 #define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */
 /* Bit masks for SDH_RESP_CMD */
 #define                  RESP_CMD  0x3f       /* Response Command */
 /* Bit masks for SDH_DATA_CTL */
 #define                     DTX_E  0x1        /* Data Transfer Enable */
 #define                   DTX_DIR  0x2        /* Data Transfer Direction */
 #define                  DTX_MODE  0x4        /* Data Transfer Mode */
 #define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
 #define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
 /* Bit masks for SDH_STATUS */
 #define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
 #define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
 #define               CMD_TIME_OUT  0x4        /* CMD Time Out */
 #define               DAT_TIME_OUT  0x8        /* Data Time Out */
 #define               TX_UNDERRUN  0x10       /* Transmit Underrun */
 #define                RX_OVERRUN  0x20       /* Receive Overrun */
 #define              CMD_RESP_END  0x40       /* CMD Response End */
 #define                  CMD_SENT  0x80       /* CMD Sent */
 #define                   DAT_END  0x100      /* Data End */
 #define             START_BIT_ERR  0x200      /* Start Bit Error */
 #define               DAT_BLK_END  0x400      /* Data Block End */
 #define                   CMD_ACT  0x800      /* CMD Active */
 #define                    TX_ACT  0x1000     /* Transmit Active */
 #define                    RX_ACT  0x2000     /* Receive Active */
 #define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
 #define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
 #define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
 #define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
 #define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
 #define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
 #define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
 #define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
 /* Bit masks for SDH_STATUS_CLR */
 #define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
 #define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
 #define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
 #define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
 #define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
 #define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
 #define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
 #define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
 #define              DAT_END_STAT  0x100      /* Data End Status */
 #define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
 #define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */
 /* Bit masks for SDH_MASK0 */
 #define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
 #define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
 #define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
 #define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
 #define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
 #define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
 #define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
 #define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
 #define              DAT_END_MASK  0x100      /* Data End Mask */
 #define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
 #define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
 #define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
 #define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
 #define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
 #define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
 #define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
 #define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
 #define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
 #define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
 #define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
 #define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
 #define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */
 /* Bit masks for SDH_FIFO_CNT */
 #define                FIFO_COUNT  0x7fff     /* FIFO Count */
 /* Bit masks for SDH_E_STATUS */
 #define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
 #define               SD_CARD_DET  0x10       /* SD Card Detect */
 /* Bit masks for SDH_E_MASK */
 #define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
 #define                   SCD_MSK  0x40       /* Mask Card Detect */
 /* Bit masks for SDH_CFG */
 #define                   CLKS_EN  0x1        /* Clocks Enable */
 #define                      SD4E  0x4        /* SDIO 4-Bit Enable */
 #define                       MWE  0x8        /* Moving Window Enable */
 #define                    SD_RST  0x10       /* SDMMC Reset */
 #define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
 #define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
 #define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */
 /* Bit masks for SDH_RD_WAIT_EN */
 #define                       RWR  0x1        /* Read Wait Request */
 #endif /* _DEF_BF516_H */
--- a/arch/blackfin/mach-bf518/include/mach/defBF518.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF518.h
@ -7,461 +7,8 @@
 #ifndef _DEF_BF518_H
 #define _DEF_BF518_H
-/* Include all Core registers and bit definitions */
+/* BF518 is BF516 + IEEE-1588 */
-#include <asm/def_LPBlackfin.h>
+#include "defBF516.h"
 /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF518 */
 /* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
 #include "defBF51x_base.h"
 /* The following are the #defines needed by ADSP-BF518 that are not in the common header */
 /* 10/100 Ethernet Controller	(0xFFC03000 - 0xFFC031FF) */
 #define EMAC_OPMODE             0xFFC03000       /* Operating Mode Register                              */
 #define EMAC_ADDRLO             0xFFC03004       /* Address Low (32 LSBs) Register                       */
 #define EMAC_ADDRHI             0xFFC03008       /* Address High (16 MSBs) Register                      */
 #define EMAC_HASHLO             0xFFC0300C       /* Multicast Hash Table Low (Bins 31-0) Register        */
 #define EMAC_HASHHI             0xFFC03010       /* Multicast Hash Table High (Bins 63-32) Register      */
 #define EMAC_STAADD             0xFFC03014       /* Station Management Address Register                  */
 #define EMAC_STADAT             0xFFC03018       /* Station Management Data Register                     */
 #define EMAC_FLC                0xFFC0301C       /* Flow Control Register                                */
 #define EMAC_VLAN1              0xFFC03020       /* VLAN1 Tag Register                                   */
 #define EMAC_VLAN2              0xFFC03024       /* VLAN2 Tag Register                                   */
 #define EMAC_WKUP_CTL           0xFFC0302C       /* Wake-Up Control/Status Register                      */
 #define EMAC_WKUP_FFMSK0        0xFFC03030       /* Wake-Up Frame Filter 0 Byte Mask Register            */
 #define EMAC_WKUP_FFMSK1        0xFFC03034       /* Wake-Up Frame Filter 1 Byte Mask Register            */
 #define EMAC_WKUP_FFMSK2        0xFFC03038       /* Wake-Up Frame Filter 2 Byte Mask Register            */
 #define EMAC_WKUP_FFMSK3        0xFFC0303C       /* Wake-Up Frame Filter 3 Byte Mask Register            */
 #define EMAC_WKUP_FFCMD         0xFFC03040       /* Wake-Up Frame Filter Commands Register               */
 #define EMAC_WKUP_FFOFF         0xFFC03044       /* Wake-Up Frame Filter Offsets Register                */
 #define EMAC_WKUP_FFCRC0        0xFFC03048       /* Wake-Up Frame Filter 0,1 CRC-16 Register             */
 #define EMAC_WKUP_FFCRC1        0xFFC0304C       /* Wake-Up Frame Filter 2,3 CRC-16 Register             */
 #define EMAC_SYSCTL             0xFFC03060       /* EMAC System Control Register                         */
 #define EMAC_SYSTAT             0xFFC03064       /* EMAC System Status Register                          */
 #define EMAC_RX_STAT            0xFFC03068       /* RX Current Frame Status Register                     */
 #define EMAC_RX_STKY            0xFFC0306C       /* RX Sticky Frame Status Register                      */
 #define EMAC_RX_IRQE            0xFFC03070       /* RX Frame Status Interrupt Enables Register           */
 #define EMAC_TX_STAT            0xFFC03074       /* TX Current Frame Status Register                     */
 #define EMAC_TX_STKY            0xFFC03078       /* TX Sticky Frame Status Register                      */
 #define EMAC_TX_IRQE            0xFFC0307C       /* TX Frame Status Interrupt Enables Register           */
 #define EMAC_MMC_CTL            0xFFC03080       /* MMC Counter Control Register                         */
 #define EMAC_MMC_RIRQS          0xFFC03084       /* MMC RX Interrupt Status Register                     */
 #define EMAC_MMC_RIRQE          0xFFC03088       /* MMC RX Interrupt Enables Register                    */
 #define EMAC_MMC_TIRQS          0xFFC0308C       /* MMC TX Interrupt Status Register                     */
 #define EMAC_MMC_TIRQE          0xFFC03090       /* MMC TX Interrupt Enables Register                    */
 #define EMAC_RXC_OK             0xFFC03100       /* RX Frame Successful Count                            */
 #define EMAC_RXC_FCS            0xFFC03104       /* RX Frame FCS Failure Count                           */
 #define EMAC_RXC_ALIGN          0xFFC03108       /* RX Alignment Error Count                             */
 #define EMAC_RXC_OCTET          0xFFC0310C       /* RX Octets Successfully Received Count                */
 #define EMAC_RXC_DMAOVF         0xFFC03110       /* Internal MAC Sublayer Error RX Frame Count           */
 #define EMAC_RXC_UNICST         0xFFC03114       /* Unicast RX Frame Count                               */
 #define EMAC_RXC_MULTI          0xFFC03118       /* Multicast RX Frame Count                             */
 #define EMAC_RXC_BROAD          0xFFC0311C       /* Broadcast RX Frame Count                             */
 #define EMAC_RXC_LNERRI         0xFFC03120       /* RX Frame In Range Error Count                        */
 #define EMAC_RXC_LNERRO         0xFFC03124       /* RX Frame Out Of Range Error Count                    */
 #define EMAC_RXC_LONG           0xFFC03128       /* RX Frame Too Long Count                              */
 #define EMAC_RXC_MACCTL         0xFFC0312C       /* MAC Control RX Frame Count                           */
 #define EMAC_RXC_OPCODE         0xFFC03130       /* Unsupported Op-Code RX Frame Count                   */
 #define EMAC_RXC_PAUSE          0xFFC03134       /* MAC Control Pause RX Frame Count                     */
 #define EMAC_RXC_ALLFRM         0xFFC03138       /* Overall RX Frame Count                               */
 #define EMAC_RXC_ALLOCT         0xFFC0313C       /* Overall RX Octet Count                               */
 #define EMAC_RXC_TYPED          0xFFC03140       /* Type/Length Consistent RX Frame Count                */
 #define EMAC_RXC_SHORT          0xFFC03144       /* RX Frame Fragment Count - Byte Count x < 64          */
 #define EMAC_RXC_EQ64           0xFFC03148       /* Good RX Frame Count - Byte Count x = 64              */
 #define EMAC_RXC_LT128          0xFFC0314C       /* Good RX Frame Count - Byte Count  64 < x < 128       */
 #define EMAC_RXC_LT256          0xFFC03150       /* Good RX Frame Count - Byte Count 128 <= x < 256      */
 #define EMAC_RXC_LT512          0xFFC03154       /* Good RX Frame Count - Byte Count 256 <= x < 512      */
 #define EMAC_RXC_LT1024         0xFFC03158       /* Good RX Frame Count - Byte Count 512 <= x < 1024     */
 #define EMAC_RXC_GE1024         0xFFC0315C       /* Good RX Frame Count - Byte Count x >= 1024           */
 #define EMAC_TXC_OK             0xFFC03180       /* TX Frame Successful Count                             */
 #define EMAC_TXC_1COL           0xFFC03184       /* TX Frames Successful After Single Collision Count     */
 #define EMAC_TXC_GT1COL         0xFFC03188       /* TX Frames Successful After Multiple Collisions Count  */
 #define EMAC_TXC_OCTET          0xFFC0318C       /* TX Octets Successfully Received Count                 */
 #define EMAC_TXC_DEFER          0xFFC03190       /* TX Frame Delayed Due To Busy Count                    */
 #define EMAC_TXC_LATECL         0xFFC03194       /* Late TX Collisions Count                              */
 #define EMAC_TXC_XS_COL         0xFFC03198       /* TX Frame Failed Due To Excessive Collisions Count     */
 #define EMAC_TXC_DMAUND         0xFFC0319C       /* Internal MAC Sublayer Error TX Frame Count            */
 #define EMAC_TXC_CRSERR         0xFFC031A0       /* Carrier Sense Deasserted During TX Frame Count        */
 #define EMAC_TXC_UNICST         0xFFC031A4       /* Unicast TX Frame Count                                */
 #define EMAC_TXC_MULTI          0xFFC031A8       /* Multicast TX Frame Count                              */
 #define EMAC_TXC_BROAD          0xFFC031AC       /* Broadcast TX Frame Count                              */
 #define EMAC_TXC_XS_DFR         0xFFC031B0       /* TX Frames With Excessive Deferral Count               */
 #define EMAC_TXC_MACCTL         0xFFC031B4       /* MAC Control TX Frame Count                            */
 #define EMAC_TXC_ALLFRM         0xFFC031B8       /* Overall TX Frame Count                                */
 #define EMAC_TXC_ALLOCT         0xFFC031BC       /* Overall TX Octet Count                                */
 #define EMAC_TXC_EQ64           0xFFC031C0       /* Good TX Frame Count - Byte Count x = 64               */
 #define EMAC_TXC_LT128          0xFFC031C4       /* Good TX Frame Count - Byte Count  64 < x < 128        */
 #define EMAC_TXC_LT256          0xFFC031C8       /* Good TX Frame Count - Byte Count 128 <= x < 256       */
 #define EMAC_TXC_LT512          0xFFC031CC       /* Good TX Frame Count - Byte Count 256 <= x < 512       */
 #define EMAC_TXC_LT1024         0xFFC031D0       /* Good TX Frame Count - Byte Count 512 <= x < 1024      */
 #define EMAC_TXC_GE1024         0xFFC031D4       /* Good TX Frame Count - Byte Count x >= 1024            */
 #define EMAC_TXC_ABORT          0xFFC031D8       /* Total TX Frames Aborted Count                         */
 /* Listing for IEEE-Supported Count Registers */
 #define FramesReceivedOK                EMAC_RXC_OK        /* RX Frame Successful Count                            */
 #define FrameCheckSequenceErrors        EMAC_RXC_FCS       /* RX Frame FCS Failure Count                           */
 #define AlignmentErrors                 EMAC_RXC_ALIGN     /* RX Alignment Error Count                             */
 #define OctetsReceivedOK                EMAC_RXC_OCTET     /* RX Octets Successfully Received Count                */
 #define FramesLostDueToIntMACRcvError   EMAC_RXC_DMAOVF    /* Internal MAC Sublayer Error RX Frame Count           */
 #define UnicastFramesReceivedOK         EMAC_RXC_UNICST    /* Unicast RX Frame Count                               */
 #define MulticastFramesReceivedOK       EMAC_RXC_MULTI     /* Multicast RX Frame Count                             */
 #define BroadcastFramesReceivedOK       EMAC_RXC_BROAD     /* Broadcast RX Frame Count                             */
 #define InRangeLengthErrors             EMAC_RXC_LNERRI    /* RX Frame In Range Error Count                        */
 #define OutOfRangeLengthField           EMAC_RXC_LNERRO    /* RX Frame Out Of Range Error Count                    */
 #define FrameTooLongErrors              EMAC_RXC_LONG      /* RX Frame Too Long Count                              */
 #define MACControlFramesReceived        EMAC_RXC_MACCTL    /* MAC Control RX Frame Count                           */
 #define UnsupportedOpcodesReceived      EMAC_RXC_OPCODE    /* Unsupported Op-Code RX Frame Count                   */
 #define PAUSEMACCtrlFramesReceived      EMAC_RXC_PAUSE     /* MAC Control Pause RX Frame Count                     */
 #define FramesReceivedAll               EMAC_RXC_ALLFRM    /* Overall RX Frame Count                               */
 #define OctetsReceivedAll               EMAC_RXC_ALLOCT    /* Overall RX Octet Count                               */
 #define TypedFramesReceived             EMAC_RXC_TYPED     /* Type/Length Consistent RX Frame Count                */
 #define FramesLenLt64Received           EMAC_RXC_SHORT     /* RX Frame Fragment Count - Byte Count x < 64          */
 #define FramesLenEq64Received           EMAC_RXC_EQ64      /* Good RX Frame Count - Byte Count x = 64              */
 #define FramesLen65_127Received         EMAC_RXC_LT128     /* Good RX Frame Count - Byte Count  64 < x < 128       */
 #define FramesLen128_255Received        EMAC_RXC_LT256     /* Good RX Frame Count - Byte Count 128 <= x < 256      */
 #define FramesLen256_511Received        EMAC_RXC_LT512     /* Good RX Frame Count - Byte Count 256 <= x < 512      */
 #define FramesLen512_1023Received       EMAC_RXC_LT1024    /* Good RX Frame Count - Byte Count 512 <= x < 1024     */
 #define FramesLen1024_MaxReceived       EMAC_RXC_GE1024    /* Good RX Frame Count - Byte Count x >= 1024           */
 #define FramesTransmittedOK             EMAC_TXC_OK        /* TX Frame Successful Count                            */
 #define SingleCollisionFrames           EMAC_TXC_1COL      /* TX Frames Successful After Single Collision Count    */
 #define MultipleCollisionFrames         EMAC_TXC_GT1COL    /* TX Frames Successful After Multiple Collisions Count */
 #define OctetsTransmittedOK             EMAC_TXC_OCTET     /* TX Octets Successfully Received Count                */
 #define FramesWithDeferredXmissions     EMAC_TXC_DEFER     /* TX Frame Delayed Due To Busy Count                   */
 #define LateCollisions                  EMAC_TXC_LATECL    /* Late TX Collisions Count                             */
 #define FramesAbortedDueToXSColls       EMAC_TXC_XS_COL    /* TX Frame Failed Due To Excessive Collisions Count    */
 #define FramesLostDueToIntMacXmitError  EMAC_TXC_DMAUND    /* Internal MAC Sublayer Error TX Frame Count           */
 #define CarrierSenseErrors              EMAC_TXC_CRSERR    /* Carrier Sense Deasserted During TX Frame Count       */
 #define UnicastFramesXmittedOK          EMAC_TXC_UNICST    /* Unicast TX Frame Count                               */
 #define MulticastFramesXmittedOK        EMAC_TXC_MULTI     /* Multicast TX Frame Count                             */
 #define BroadcastFramesXmittedOK        EMAC_TXC_BROAD     /* Broadcast TX Frame Count                             */
 #define FramesWithExcessiveDeferral     EMAC_TXC_XS_DFR    /* TX Frames With Excessive Deferral Count              */
 #define MACControlFramesTransmitted     EMAC_TXC_MACCTL    /* MAC Control TX Frame Count                           */
 #define FramesTransmittedAll            EMAC_TXC_ALLFRM    /* Overall TX Frame Count                               */
 #define OctetsTransmittedAll            EMAC_TXC_ALLOCT    /* Overall TX Octet Count                               */
 #define FramesLenEq64Transmitted        EMAC_TXC_EQ64      /* Good TX Frame Count - Byte Count x = 64              */
 #define FramesLen65_127Transmitted      EMAC_TXC_LT128     /* Good TX Frame Count - Byte Count  64 < x < 128       */
 #define FramesLen128_255Transmitted     EMAC_TXC_LT256     /* Good TX Frame Count - Byte Count 128 <= x < 256      */
 #define FramesLen256_511Transmitted     EMAC_TXC_LT512     /* Good TX Frame Count - Byte Count 256 <= x < 512      */
 #define FramesLen512_1023Transmitted    EMAC_TXC_LT1024    /* Good TX Frame Count - Byte Count 512 <= x < 1024     */
 #define FramesLen1024_MaxTransmitted    EMAC_TXC_GE1024    /* Good TX Frame Count - Byte Count x >= 1024           */
 #define TxAbortedFrames                 EMAC_TXC_ABORT     /* Total TX Frames Aborted Count                        */
 /***********************************************************************************
 ** System MMR Register Bits And Macros
 **
 ** Disclaimer:	All macros are intended to make C and Assembly code more readable.
 **				Use these macros carefully, as any that do left shifts for field
 **				depositing will result in the lower order bits being destroyed.  Any
 **				macro that shifts left to properly position the bit-field should be
 **				used as part of an OR to initialize a register and NOT as a dynamic
 **				modifier UNLESS the lower order bits are saved and ORed back in when
 **				the macro is used.
 *************************************************************************************/
 /************************  ETHERNET 10/100 CONTROLLER MASKS  ************************/
 /* EMAC_OPMODE Masks */
 #define	RE                 0x00000001     /* Receiver Enable                                    */
 #define	ASTP               0x00000002     /* Enable Automatic Pad Stripping On RX Frames        */
 #define	HU                 0x00000010     /* Hash Filter Unicast Address                        */
 #define	HM                 0x00000020     /* Hash Filter Multicast Address                      */
 #define	PAM                0x00000040     /* Pass-All-Multicast Mode Enable                     */
 #define	PR                 0x00000080     /* Promiscuous Mode Enable                            */
 #define	IFE                0x00000100     /* Inverse Filtering Enable                           */
 #define	DBF                0x00000200     /* Disable Broadcast Frame Reception                  */
 #define	PBF                0x00000400     /* Pass Bad Frames Enable                             */
 #define	PSF                0x00000800     /* Pass Short Frames Enable                           */
 #define	RAF                0x00001000     /* Receive-All Mode                                   */
 #define	TE                 0x00010000     /* Transmitter Enable                                 */
 #define	DTXPAD             0x00020000     /* Disable Automatic TX Padding                       */
 #define	DTXCRC             0x00040000     /* Disable Automatic TX CRC Generation                */
 #define	DC                 0x00080000     /* Deferral Check                                     */
 #define	BOLMT              0x00300000     /* Back-Off Limit                                     */
 #define	BOLMT_10           0x00000000     /*		10-bit range                            */
 #define	BOLMT_8            0x00100000     /*		8-bit range                             */
 #define	BOLMT_4            0x00200000     /*		4-bit range                             */
 #define	BOLMT_1            0x00300000     /*		1-bit range                             */
 #define	DRTY               0x00400000     /* Disable TX Retry On Collision                      */
 #define	LCTRE              0x00800000     /* Enable TX Retry On Late Collision                  */
 #define	RMII               0x01000000     /* RMII/MII* Mode                                     */
 #define	RMII_10            0x02000000     /* Speed Select for RMII Port (10MBit/100MBit*)       */
 #define	FDMODE             0x04000000     /* Duplex Mode Enable (Full/Half*)                    */
 #define	LB                 0x08000000     /* Internal Loopback Enable                           */
 #define	DRO                0x10000000     /* Disable Receive Own Frames (Half-Duplex Mode)      */
 /* EMAC_STAADD Masks */
 #define	STABUSY            0x00000001     /* Initiate Station Mgt Reg Access / STA Busy Stat    */
 #define	STAOP              0x00000002     /* Station Management Operation Code (Write/Read*)    */
 #define	STADISPRE          0x00000004     /* Disable Preamble Generation                        */
 #define	STAIE              0x00000008     /* Station Mgt. Transfer Done Interrupt Enable        */
 #define	REGAD              0x000007C0     /* STA Register Address                               */
 #define	PHYAD              0x0000F800     /* PHY Device Address                                 */
 #define	SET_REGAD(x) (((x)&0x1F)<<  6 )   /* Set STA Register Address                           */
 #define	SET_PHYAD(x) (((x)&0x1F)<< 11 )   /* Set PHY Device Address                             */
 /* EMAC_STADAT Mask */
 #define	STADATA            0x0000FFFF     /* Station Management Data                            */
 /* EMAC_FLC Masks */
 #define	FLCBUSY            0x00000001     /* Send Flow Ctrl Frame / Flow Ctrl Busy Status       */
 #define	FLCE               0x00000002     /* Flow Control Enable                                */
 #define	PCF                0x00000004     /* Pass Control Frames                                */
 #define	BKPRSEN            0x00000008     /* Enable Backpressure                                */
 #define	FLCPAUSE           0xFFFF0000     /* Pause Time                                         */
 #define	SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time                                   */
 /* EMAC_WKUP_CTL Masks */
 #define	CAPWKFRM           0x00000001    /* Capture Wake-Up Frames                              */
 #define	MPKE               0x00000002    /* Magic Packet Enable                                 */
 #define	RWKE               0x00000004    /* Remote Wake-Up Frame Enable                         */
 #define	GUWKE              0x00000008    /* Global Unicast Wake Enable                          */
 #define	MPKS               0x00000020    /* Magic Packet Received Status                        */
 #define	RWKS               0x00000F00    /* Wake-Up Frame Received Status, Filters 3:0          */
 /* EMAC_WKUP_FFCMD Masks */
 #define	WF0_E              0x00000001    /* Enable Wake-Up Filter 0                              */
 #define	WF0_T              0x00000008    /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*)      */
 #define	WF1_E              0x00000100    /* Enable Wake-Up Filter 1                              */
 #define	WF1_T              0x00000800    /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*)      */
 #define	WF2_E              0x00010000    /* Enable Wake-Up Filter 2                              */
 #define	WF2_T              0x00080000    /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*)      */
 #define	WF3_E              0x01000000    /* Enable Wake-Up Filter 3                              */
 #define	WF3_T              0x08000000    /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*)      */
 /* EMAC_WKUP_FFOFF Masks */
 #define	WF0_OFF            0x000000FF    /* Wake-Up Filter 0 Pattern Offset                      */
 #define	WF1_OFF            0x0000FF00    /* Wake-Up Filter 1 Pattern Offset                      */
 #define	WF2_OFF            0x00FF0000    /* Wake-Up Filter 2 Pattern Offset                      */
 #define	WF3_OFF            0xFF000000    /* Wake-Up Filter 3 Pattern Offset                      */
 #define	SET_WF0_OFF(x) (((x)&0xFF)<<  0 ) /* Set Wake-Up Filter 0 Byte Offset                    */
 #define	SET_WF1_OFF(x) (((x)&0xFF)<<  8 ) /* Set Wake-Up Filter 1 Byte Offset                    */
 #define	SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset                    */
 #define	SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset                    */
 /* Set ALL Offsets */
 #define	SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
 /* EMAC_WKUP_FFCRC0 Masks */
 #define	WF0_CRC           0x0000FFFF    /* Wake-Up Filter 0 Pattern CRC                           */
 #define	WF1_CRC           0xFFFF0000    /* Wake-Up Filter 1 Pattern CRC                           */
 #define	SET_WF0_CRC(x) (((x)&0xFFFF)<<   0 ) /* Set Wake-Up Filter 0 Target CRC                   */
 #define	SET_WF1_CRC(x) (((x)&0xFFFF)<<  16 ) /* Set Wake-Up Filter 1 Target CRC                   */
 /* EMAC_WKUP_FFCRC1 Masks */
 #define	WF2_CRC           0x0000FFFF    /* Wake-Up Filter 2 Pattern CRC                           */
 #define	WF3_CRC           0xFFFF0000    /* Wake-Up Filter 3 Pattern CRC                           */
 #define	SET_WF2_CRC(x) (((x)&0xFFFF)<<   0 ) /* Set Wake-Up Filter 2 Target CRC                   */
 #define	SET_WF3_CRC(x) (((x)&0xFFFF)<<  16 ) /* Set Wake-Up Filter 3 Target CRC                   */
 /* EMAC_SYSCTL Masks */
 #define	PHYIE             0x00000001    /* PHY_INT Interrupt Enable                               */
 #define	RXDWA             0x00000002    /* Receive Frame DMA Word Alignment (Odd/Even*)           */
 #define	RXCKS             0x00000004    /* Enable RX Frame TCP/UDP Checksum Computation           */
 #define	TXDWA             0x00000010    /* Transmit Frame DMA Word Alignment (Odd/Even*)          */
 #define	MDCDIV            0x00003F00    /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))]            */
 #define	SET_MDCDIV(x) (((x)&0x3F)<< 8)   /* Set MDC Clock Divisor                                 */
 /* EMAC_SYSTAT Masks */
 #define	PHYINT            0x00000001    /* PHY_INT Interrupt Status                               */
 #define	MMCINT            0x00000002    /* MMC Counter Interrupt Status                           */
 #define	RXFSINT           0x00000004    /* RX Frame-Status Interrupt Status                       */
 #define	TXFSINT           0x00000008    /* TX Frame-Status Interrupt Status                       */
 #define	WAKEDET           0x00000010    /* Wake-Up Detected Status                                */
 #define	RXDMAERR          0x00000020    /* RX DMA Direction Error Status                          */
 #define	TXDMAERR          0x00000040    /* TX DMA Direction Error Status                          */
 #define	STMDONE           0x00000080    /* Station Mgt. Transfer Done Interrupt Status            */
 /* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
 #define	RX_FRLEN          0x000007FF    /* Frame Length In Bytes                                  */
 #define	RX_COMP           0x00001000    /* RX Frame Complete                                      */
 #define	RX_OK             0x00002000    /* RX Frame Received With No Errors                       */
 #define	RX_LONG           0x00004000    /* RX Frame Too Long Error                                */
 #define	RX_ALIGN          0x00008000    /* RX Frame Alignment Error                               */
 #define	RX_CRC            0x00010000    /* RX Frame CRC Error                                     */
 #define	RX_LEN            0x00020000    /* RX Frame Length Error                                  */
 #define	RX_FRAG           0x00040000    /* RX Frame Fragment Error                                */
 #define	RX_ADDR           0x00080000    /* RX Frame Address Filter Failed Error                   */
 #define	RX_DMAO           0x00100000    /* RX Frame DMA Overrun Error                             */
 #define	RX_PHY            0x00200000    /* RX Frame PHY Error                                     */
 #define	RX_LATE           0x00400000    /* RX Frame Late Collision Error                          */
 #define	RX_RANGE          0x00800000    /* RX Frame Length Field Out of Range Error               */
 #define	RX_MULTI          0x01000000    /* RX Multicast Frame Indicator                           */
 #define	RX_BROAD          0x02000000    /* RX Broadcast Frame Indicator                           */
 #define	RX_CTL            0x04000000    /* RX Control Frame Indicator                             */
 #define	RX_UCTL           0x08000000    /* Unsupported RX Control Frame Indicator                 */
 #define	RX_TYPE           0x10000000    /* RX Typed Frame Indicator                               */
 #define	RX_VLAN1          0x20000000    /* RX VLAN1 Frame Indicator                               */
 #define	RX_VLAN2          0x40000000    /* RX VLAN2 Frame Indicator                               */
 #define	RX_ACCEPT         0x80000000    /* RX Frame Accepted Indicator                            */
 /*  EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks  */
 #define	TX_COMP           0x00000001    /* TX Frame Complete                                      */
 #define	TX_OK             0x00000002    /* TX Frame Sent With No Errors                           */
 #define	TX_ECOLL          0x00000004    /* TX Frame Excessive Collision Error                     */
 #define	TX_LATE           0x00000008    /* TX Frame Late Collision Error                          */
 #define	TX_DMAU           0x00000010    /* TX Frame DMA Underrun Error (STAT)                     */
 #define	TX_MACE           0x00000010    /* Internal MAC Error Detected (STKY and IRQE)            */
 #define	TX_EDEFER         0x00000020    /* TX Frame Excessive Deferral Error                      */
 #define	TX_BROAD          0x00000040    /* TX Broadcast Frame Indicator                           */
 #define	TX_MULTI          0x00000080    /* TX Multicast Frame Indicator                           */
 #define	TX_CCNT           0x00000F00    /* TX Frame Collision Count                               */
 #define	TX_DEFER          0x00001000    /* TX Frame Deferred Indicator                            */
 #define	TX_CRS            0x00002000    /* TX Frame Carrier Sense Not Asserted Error              */
 #define	TX_LOSS           0x00004000    /* TX Frame Carrier Lost During TX Error                  */
 #define	TX_RETRY          0x00008000    /* TX Frame Successful After Retry                        */
 #define	TX_FRLEN          0x07FF0000    /* TX Frame Length (Bytes)                                */
 /* EMAC_MMC_CTL Masks */
 #define	RSTC              0x00000001    /* Reset All Counters                                     */
 #define	CROLL             0x00000002    /* Counter Roll-Over Enable                               */
 #define	CCOR              0x00000004    /* Counter Clear-On-Read Mode Enable                      */
 #define	MMCE              0x00000008    /* Enable MMC Counter Operation                           */
 /* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
 #define	RX_OK_CNT         0x00000001    /* RX Frames Received With No Errors                      */
 #define	RX_FCS_CNT        0x00000002    /* RX Frames W/Frame Check Sequence Errors                */
 #define	RX_ALIGN_CNT      0x00000004    /* RX Frames With Alignment Errors                        */
 #define	RX_OCTET_CNT      0x00000008    /* RX Octets Received OK                                  */
 #define	RX_LOST_CNT       0x00000010    /* RX Frames Lost Due To Internal MAC RX Error            */
 #define	RX_UNI_CNT        0x00000020    /* Unicast RX Frames Received OK                          */
 #define	RX_MULTI_CNT      0x00000040    /* Multicast RX Frames Received OK                        */
 #define	RX_BROAD_CNT      0x00000080    /* Broadcast RX Frames Received OK                        */
 #define	RX_IRL_CNT        0x00000100    /* RX Frames With In-Range Length Errors                  */
 #define	RX_ORL_CNT        0x00000200    /* RX Frames With Out-Of-Range Length Errors              */
 #define	RX_LONG_CNT       0x00000400    /* RX Frames With Frame Too Long Errors                   */
 #define	RX_MACCTL_CNT     0x00000800    /* MAC Control RX Frames Received                         */
 #define	RX_OPCODE_CTL     0x00001000    /* Unsupported Op-Code RX Frames Received                 */
 #define	RX_PAUSE_CNT      0x00002000    /* PAUSEMAC Control RX Frames Received                    */
 #define	RX_ALLF_CNT       0x00004000    /* All RX Frames Received                                 */
 #define	RX_ALLO_CNT       0x00008000    /* All RX Octets Received                                 */
 #define	RX_TYPED_CNT      0x00010000    /* Typed RX Frames Received                               */
 #define	RX_SHORT_CNT      0x00020000    /* RX Frame Fragments (< 64 Bytes) Received               */
 #define	RX_EQ64_CNT       0x00040000    /* 64-Byte RX Frames Received                             */
 #define	RX_LT128_CNT      0x00080000    /* 65-127-Byte RX Frames Received                         */
 #define	RX_LT256_CNT      0x00100000    /* 128-255-Byte RX Frames Received                        */
 #define	RX_LT512_CNT      0x00200000    /* 256-511-Byte RX Frames Received                        */
 #define	RX_LT1024_CNT     0x00400000    /* 512-1023-Byte RX Frames Received                       */
 #define	RX_GE1024_CNT     0x00800000    /* 1024-Max-Byte RX Frames Received                       */
 /* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks  */
 #define	TX_OK_CNT         0x00000001    /* TX Frames Sent OK                                      */
 #define	TX_SCOLL_CNT      0x00000002    /* TX Frames With Single Collisions                       */
 #define	TX_MCOLL_CNT      0x00000004    /* TX Frames With Multiple Collisions                     */
 #define	TX_OCTET_CNT      0x00000008    /* TX Octets Sent OK                                      */
 #define	TX_DEFER_CNT      0x00000010    /* TX Frames With Deferred Transmission                   */
 #define	TX_LATE_CNT       0x00000020    /* TX Frames With Late Collisions                         */
 #define	TX_ABORTC_CNT     0x00000040    /* TX Frames Aborted Due To Excess Collisions             */
 #define	TX_LOST_CNT       0x00000080    /* TX Frames Lost Due To Internal MAC TX Error            */
 #define	TX_CRS_CNT        0x00000100    /* TX Frames With Carrier Sense Errors                    */
 #define	TX_UNI_CNT        0x00000200    /* Unicast TX Frames Sent                                 */
 #define	TX_MULTI_CNT      0x00000400    /* Multicast TX Frames Sent                               */
 #define	TX_BROAD_CNT      0x00000800    /* Broadcast TX Frames Sent                               */
 #define	TX_EXDEF_CTL      0x00001000    /* TX Frames With Excessive Deferral                      */
 #define	TX_MACCTL_CNT     0x00002000    /* MAC Control TX Frames Sent                             */
 #define	TX_ALLF_CNT       0x00004000    /* All TX Frames Sent                                     */
 #define	TX_ALLO_CNT       0x00008000    /* All TX Octets Sent                                     */
 #define	TX_EQ64_CNT       0x00010000    /* 64-Byte TX Frames Sent                                 */
 #define	TX_LT128_CNT      0x00020000    /* 65-127-Byte TX Frames Sent                             */
 #define	TX_LT256_CNT      0x00040000    /* 128-255-Byte TX Frames Sent                            */
 #define	TX_LT512_CNT      0x00080000    /* 256-511-Byte TX Frames Sent                            */
 #define	TX_LT1024_CNT     0x00100000    /* 512-1023-Byte TX Frames Sent                           */
 #define	TX_GE1024_CNT     0x00200000    /* 1024-Max-Byte TX Frames Sent                           */
 #define	TX_ABORT_CNT      0x00400000    /* TX Frames Aborted                                      */
 /* SDH Registers */
 #define SDH_PWR_CTL                    0xFFC03900 /* SDH Power Control */
 #define SDH_CLK_CTL                    0xFFC03904 /* SDH Clock Control */
 #define SDH_ARGUMENT                   0xFFC03908 /* SDH Argument */
 #define SDH_COMMAND                    0xFFC0390C /* SDH Command */
 #define SDH_RESP_CMD                   0xFFC03910 /* SDH Response Command */
 #define SDH_RESPONSE0                  0xFFC03914 /* SDH Response0 */
 #define SDH_RESPONSE1                  0xFFC03918 /* SDH Response1 */
 #define SDH_RESPONSE2                  0xFFC0391C /* SDH Response2 */
 #define SDH_RESPONSE3                  0xFFC03920 /* SDH Response3 */
 #define SDH_DATA_TIMER                 0xFFC03924 /* SDH Data Timer */
 #define SDH_DATA_LGTH                  0xFFC03928 /* SDH Data Length */
 #define SDH_DATA_CTL                   0xFFC0392C /* SDH Data Control */
 #define SDH_DATA_CNT                   0xFFC03930 /* SDH Data Counter */
 #define SDH_STATUS                     0xFFC03934 /* SDH Status */
 #define SDH_STATUS_CLR                 0xFFC03938 /* SDH Status Clear */
 #define SDH_MASK0                      0xFFC0393C /* SDH Interrupt0 Mask */
 #define SDH_MASK1                      0xFFC03940 /* SDH Interrupt1 Mask */
 #define SDH_FIFO_CNT                   0xFFC03948 /* SDH FIFO Counter */
 #define SDH_FIFO                       0xFFC03980 /* SDH Data FIFO */
 #define SDH_E_STATUS                   0xFFC039C0 /* SDH Exception Status */
 #define SDH_E_MASK                     0xFFC039C4 /* SDH Exception Mask */
 #define SDH_CFG                        0xFFC039C8 /* SDH Configuration */
 #define SDH_RD_WAIT_EN                 0xFFC039CC /* SDH Read Wait Enable */
 #define SDH_PID0                       0xFFC039D0 /* SDH Peripheral Identification0 */
 #define SDH_PID1                       0xFFC039D4 /* SDH Peripheral Identification1 */
 #define SDH_PID2                       0xFFC039D8 /* SDH Peripheral Identification2 */
 #define SDH_PID3                       0xFFC039DC /* SDH Peripheral Identification3 */
 #define SDH_PID4                       0xFFC039E0 /* SDH Peripheral Identification4 */
 #define SDH_PID5                       0xFFC039E4 /* SDH Peripheral Identification5 */
 #define SDH_PID6                       0xFFC039E8 /* SDH Peripheral Identification6 */
 #define SDH_PID7                       0xFFC039EC /* SDH Peripheral Identification7 */
 /* Removable Storage Interface Registers */
 #define RSI_PWR_CONTROL                0xFFC03800 /* RSI Power Control Register */
 #define RSI_CLK_CONTROL                0xFFC03804 /* RSI Clock Control Register */
 #define RSI_ARGUMENT                   0xFFC03808 /* RSI Argument Register */
 #define RSI_COMMAND                    0xFFC0380C /* RSI Command Register */
 #define RSI_RESP_CMD                   0xFFC03810 /* RSI Response Command Register */
 #define RSI_RESPONSE0                  0xFFC03814 /* RSI Response Register */
 #define RSI_RESPONSE1                  0xFFC03818 /* RSI Response Register */
 #define RSI_RESPONSE2                  0xFFC0381C /* RSI Response Register */
 #define RSI_RESPONSE3                  0xFFC03820 /* RSI Response Register */
 #define RSI_DATA_TIMER                 0xFFC03824 /* RSI Data Timer Register */
 #define RSI_DATA_LGTH                  0xFFC03828 /* RSI Data Length Register */
 #define RSI_DATA_CONTROL               0xFFC0382C /* RSI Data Control Register */
 #define RSI_DATA_CNT                   0xFFC03830 /* RSI Data Counter Register */
 #define RSI_STATUS                     0xFFC03834 /* RSI Status Register */
 #define RSI_STATUSCL                   0xFFC03838 /* RSI Status Clear Register */
 #define RSI_MASK0                      0xFFC0383C /* RSI Interrupt 0 Mask Register */
 #define RSI_MASK1                      0xFFC03840 /* RSI Interrupt 1 Mask Register */
 #define RSI_FIFO_CNT                   0xFFC03848 /* RSI FIFO Counter Register */
 #define RSI_CEATA_CONTROL              0xFFC0384C /* RSI CEATA Register */
 #define RSI_FIFO                       0xFFC03880 /* RSI Data FIFO Register */
 #define RSI_ESTAT                      0xFFC038C0 /* RSI Exception Status Register */
 #define RSI_EMASK                      0xFFC038C4 /* RSI Exception Mask Register */
 #define RSI_CONFIG                     0xFFC038C8 /* RSI Configuration Register */
 #define RSI_RD_WAIT_EN                 0xFFC038CC /* RSI Read Wait Enable Register */
 #define RSI_PID0                       0xFFC03FE0 /* RSI Peripheral ID Register 0 */
 #define RSI_PID1                       0xFFC03FE4 /* RSI Peripheral ID Register 1 */
 #define RSI_PID2                       0xFFC03FE8 /* RSI Peripheral ID Register 2 */
 #define RSI_PID3                       0xFFC03FEC /* RSI Peripheral ID Register 3 */
 #define RSI_PID4                       0xFFC03FF0 /* RSI Peripheral ID Register 4 */
 #define RSI_PID5                       0xFFC03FF4 /* RSI Peripheral ID Register 5 */
 #define RSI_PID6                       0xFFC03FF8 /* RSI Peripheral ID Register 6 */
 #define RSI_PID7                       0xFFC03FFC /* RSI Peripheral ID Register 7 */
 /* PTP TSYNC Registers */
@ -489,141 +36,6 @@
 #define EMAC_PTP_PPS_STARTHI           0xFFC030F4 /* PPS Start Time High */
 #define EMAC_PTP_PPS_PERIOD            0xFFC030F8 /* PPS Count Register */
 /* ********************************************************** */
 /*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
 /*     and MULTI BIT READ MACROS                              */
 /* ********************************************************** */
 /* Bit masks for SDH_COMMAND */
 #define                   CMD_IDX  0x3f       /* Command Index */
 #define                   CMD_RSP  0x40       /* Response */
 #define                 CMD_L_RSP  0x80       /* Long Response */
 #define                 CMD_INT_E  0x100      /* Command Interrupt */
 #define                CMD_PEND_E  0x200      /* Command Pending */
 #define                     CMD_E  0x400      /* Command Enable */
 /* Bit masks for SDH_PWR_CTL */
 #define                    PWR_ON  0x3        /* Power On */
 #if 0
 #define                       TBD  0x3c       /* TBD */
 #endif
 #define                 SD_CMD_OD  0x40       /* Open Drain Output */
 #define                   ROD_CTL  0x80       /* Rod Control */
 /* Bit masks for SDH_CLK_CTL */
 #define                    CLKDIV  0xff       /* MC_CLK Divisor */
 #define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
 #define                  PWR_SV_E  0x200      /* Power Save Enable */
 #define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
 #define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */
 /* Bit masks for SDH_RESP_CMD */
 #define                  RESP_CMD  0x3f       /* Response Command */
 /* Bit masks for SDH_DATA_CTL */
 #define                     DTX_E  0x1        /* Data Transfer Enable */
 #define                   DTX_DIR  0x2        /* Data Transfer Direction */
 #define                  DTX_MODE  0x4        /* Data Transfer Mode */
 #define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
 #define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
 /* Bit masks for SDH_STATUS */
 #define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
 #define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
 #define               CMD_TIME_OUT  0x4        /* CMD Time Out */
 #define               DAT_TIME_OUT  0x8        /* Data Time Out */
 #define               TX_UNDERRUN  0x10       /* Transmit Underrun */
 #define                RX_OVERRUN  0x20       /* Receive Overrun */
 #define              CMD_RESP_END  0x40       /* CMD Response End */
 #define                  CMD_SENT  0x80       /* CMD Sent */
 #define                   DAT_END  0x100      /* Data End */
 #define             START_BIT_ERR  0x200      /* Start Bit Error */
 #define               DAT_BLK_END  0x400      /* Data Block End */
 #define                   CMD_ACT  0x800      /* CMD Active */
 #define                    TX_ACT  0x1000     /* Transmit Active */
 #define                    RX_ACT  0x2000     /* Receive Active */
 #define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
 #define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
 #define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
 #define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
 #define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
 #define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
 #define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
 #define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
 /* Bit masks for SDH_STATUS_CLR */
 #define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
 #define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
 #define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
 #define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
 #define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
 #define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
 #define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
 #define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
 #define              DAT_END_STAT  0x100      /* Data End Status */
 #define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
 #define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */
 /* Bit masks for SDH_MASK0 */
 #define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
 #define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
 #define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
 #define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
 #define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
 #define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
 #define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
 #define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
 #define              DAT_END_MASK  0x100      /* Data End Mask */
 #define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
 #define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
 #define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
 #define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
 #define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
 #define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
 #define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
 #define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
 #define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
 #define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
 #define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
 #define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
 #define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */
 /* Bit masks for SDH_FIFO_CNT */
 #define                FIFO_COUNT  0x7fff     /* FIFO Count */
 /* Bit masks for SDH_E_STATUS */
 #define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
 #define               SD_CARD_DET  0x10       /* SD Card Detect */
 /* Bit masks for SDH_E_MASK */
 #define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
 #define                   SCD_MSK  0x40       /* Mask Card Detect */
 /* Bit masks for SDH_CFG */
 #define                   CLKS_EN  0x1        /* Clocks Enable */
 #define                      SD4E  0x4        /* SDIO 4-Bit Enable */
 #define                       MWE  0x8        /* Moving Window Enable */
 #define                    SD_RST  0x10       /* SDMMC Reset */
 #define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
 #define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
 #define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */
 /* Bit masks for SDH_RD_WAIT_EN */
 #define                       RWR  0x1        /* Read Wait Request */
 /* Bit masks for EMAC_PTP_CTL */
 #define                    PTP_EN  0x1        /* Enable the PTP_TSYNC module */
--- a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
@ -585,58 +585,6 @@
 **				modifier UNLESS the lower order bits are saved and ORed back in when
 **				the macro is used.
 *************************************************************************************/
 /*
 ** ********************* PLL AND RESET MASKS ****************************************/
 /* PLL_CTL Masks																	*/
 #define DF				0x0001	/* 0: PLL = CLKIN, 1: PLL = CLKIN/2					*/
 #define PLL_OFF			0x0002	/* PLL Not Powered									*/
 #define STOPCK			0x0008	/* Core Clock Off									*/
 #define PDWN			0x0020	/* Enter Deep Sleep Mode							*/
 #define	IN_DELAY		0x0040	/* Add 200ps Delay To EBIU Input Latches			*/
 #define	OUT_DELAY		0x0080	/* Add 200ps Delay To EBIU Output Signals			*/
 #define BYPASS			0x0100	/* Bypass the PLL									*/
 #define	MSEL			0x7E00	/* Multiplier Select For CCLK/VCO Factors			*/
 /* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits)			*/
 #define	SET_MSEL(x)		(((x)&0x3F) << 0x9)	/* Set MSEL = 0-63 --> VCO = CLKIN*MSEL		*/
 /* PLL_DIV Masks														*/
 #define SSEL			0x000F	/* System Select						*/
 #define	CSEL			0x0030	/* Core Select							*/
 #define CSEL_DIV1		0x0000	/* 		CCLK = VCO / 1					*/
 #define CSEL_DIV2		0x0010	/* 		CCLK = VCO / 2					*/
 #define	CSEL_DIV4		0x0020	/* 		CCLK = VCO / 4					*/
 #define	CSEL_DIV8		0x0030	/* 		CCLK = VCO / 8					*/
 /* PLL_DIV Macros														*/
 #define SET_SSEL(x)		((x)&0xF)		/* Set SSEL = 0-15 --> SCLK = VCO/SSEL	*/
 /* VR_CTL Masks	*/
 #define	FREQ			0x3000	/* Switching Oscillator Frequency For Regulator	*/
 #define	HIBERNATE		0x0000	/* 		Powerdown/Bypass On-Board Regulation	*/
 #define	VLEV			0x00F0	/* Internal Voltage Level					*/
 #define	VLEV_085 		0x0060	/* 		VLEV = 0.85 V (-5% - +10% Accuracy)	*/
 #define	VLEV_090		0x0070	/* 		VLEV = 0.90 V (-5% - +10% Accuracy)	*/
 #define	VLEV_095		0x0080	/* 		VLEV = 0.95 V (-5% - +10% Accuracy)	*/
 #define	VLEV_100		0x0090	/* 		VLEV = 1.00 V (-5% - +10% Accuracy)	*/
 #define	VLEV_105		0x00A0	/* 		VLEV = 1.05 V (-5% - +10% Accuracy)	*/
 #define	VLEV_110		0x00B0	/* 		VLEV = 1.10 V (-5% - +10% Accuracy)	*/
 #define	VLEV_115		0x00C0	/* 		VLEV = 1.15 V (-5% - +10% Accuracy)	*/
 #define	VLEV_120		0x00D0	/* 		VLEV = 1.20 V (-5% - +10% Accuracy)	*/
 #define	VLEV_125		0x00E0	/* 		VLEV = 1.25 V (-5% - +10% Accuracy)	*/
 #define	VLEV_130		0x00F0	/* 		VLEV = 1.30 V (-5% - +10% Accuracy)	*/
 #define	WAKE			0x0100	/* Enable RTC/Reset Wakeup From Hibernate	*/
 #define	USBWE			0x0200	/* Enable USB Wakeup From Hibernate			*/
 #define	PHYWE			0x0400	/* Enable PHY Wakeup From Hibernate			*/
 #define	CLKBUFOE		0x4000	/* CLKIN Buffer Output Enable */
 #define	PHYCLKOE		CLKBUFOE	/* Alternative legacy name for the above */
 #define	SCKELOW		0x8000	/* Enable Drive CKE Low During Reset		*/
 /* PLL_STAT Masks																	*/
 #define ACTIVE_PLLENABLED	0x0001	/* Processor In Active Mode With PLL Enabled	*/
 #define	FULL_ON				0x0002	/* Processor In Full On Mode					*/
 #define ACTIVE_PLLDISABLED	0x0004	/* Processor In Active Mode With PLL Disabled	*/
 #define	PLL_LOCKED			0x0020	/* PLL_LOCKCNT Has Been Reached					*/
 /* CHIPID Masks */
 #define CHIPID_VERSION         0xF0000000
@ -756,66 +704,6 @@
 #define IWR_DISABLE(x)	(0xFFFFFFFF ^ (1 << ((x)&0x1F))) 	/* Wakeup Disable Peripheral #x		*/
 /* ********* WATCHDOG TIMER MASKS ******************** */
 /* Watchdog Timer WDOG_CTL Register Masks */
 #define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
 #define WDEV_RESET 0x0000 /* generate reset event on roll over */
 #define WDEV_NMI 0x0002 /* generate NMI event on roll over */
 #define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
 #define WDEV_NONE 0x0006 /* no event on roll over */
 #define WDEN 0x0FF0 /* enable watchdog */
 #define WDDIS 0x0AD0 /* disable watchdog */
 #define WDRO 0x8000 /* watchdog rolled over latch */
 /* depreciated WDOG_CTL Register Masks for legacy code */
 #define ICTL WDEV
 #define ENABLE_RESET WDEV_RESET
 #define WDOG_RESET WDEV_RESET
 #define ENABLE_NMI WDEV_NMI
 #define WDOG_NMI WDEV_NMI
 #define ENABLE_GPI WDEV_GPI
 #define WDOG_GPI WDEV_GPI
 #define DISABLE_EVT WDEV_NONE
 #define WDOG_NONE WDEV_NONE
 #define TMR_EN WDEN
 #define TMR_DIS WDDIS
 #define TRO WDRO
 #define ICTL_P0 0x01
 #define ICTL_P1 0x02
 #define TRO_P 0x0F
 /* ***************  REAL TIME CLOCK MASKS  **************************/
 /* RTC_STAT and RTC_ALARM Masks										*/
 #define	RTC_SEC				0x0000003F	/* Real-Time Clock Seconds	*/
 #define	RTC_MIN				0x00000FC0	/* Real-Time Clock Minutes	*/
 #define	RTC_HR				0x0001F000	/* Real-Time Clock Hours	*/
 #define	RTC_DAY				0xFFFE0000	/* Real-Time Clock Days		*/
 /* RTC_ALARM Macro			z=day		y=hr	x=min	w=sec		*/
 #define SET_ALARM(z,y,x,w)	((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
 /* RTC_ICTL and RTC_ISTAT Masks																		*/
 #define	STOPWATCH			0x0001		/* Stopwatch Interrupt Enable								*/
 #define	ALARM				0x0002		/* Alarm Interrupt Enable									*/
 #define	SECOND				0x0004		/* Seconds (1 Hz) Interrupt Enable							*/
 #define	MINUTE				0x0008		/* Minutes Interrupt Enable									*/
 #define	HOUR				0x0010		/* Hours Interrupt Enable									*/
 #define	DAY					0x0020		/* 24 Hours (Days) Interrupt Enable							*/
 #define	DAY_ALARM			0x0040		/* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable	*/
 #define	WRITE_PENDING		0x4000		/* Write Pending Status										*/
 #define	WRITE_COMPLETE		0x8000		/* Write Complete Interrupt Enable							*/
 /* RTC_FAST / RTC_PREN Mask												*/
 #define PREN				0x0001	/* Enable Prescaler, RTC Runs @1 Hz	*/
 /* ************** UART CONTROLLER MASKS *************************/
 /* UARTx_LCR Masks												*/
 #define WLS(x)		(((x)-5) & 0x03)	/* Word Length Select */
@ -1372,33 +1260,6 @@
 /* **************************  DMA CONTROLLER MASKS  ********************************/
 /* DMAx_CONFIG, MDMA_yy_CONFIG Masks												*/
 #define DMAEN			0x0001		/* DMA Channel Enable							*/
 #define WNR				0x0002		/* Channel Direction (W/R*)						*/
 #define WDSIZE_8		0x0000		/* Transfer Word Size = 8						*/
 #define WDSIZE_16		0x0004		/* Transfer Word Size = 16						*/
 #define WDSIZE_32		0x0008		/* Transfer Word Size = 32						*/
 #define DMA2D			0x0010		/* DMA Mode (2D/1D*)							*/
 #define RESTART			0x0020		/* DMA Buffer Clear								*/
 #define DI_SEL			0x0040		/* Data Interrupt Timing Select					*/
 #define DI_EN			0x0080		/* Data Interrupt Enable						*/
 #define NDSIZE_0		0x0000		/* Next Descriptor Size = 0 (Stop/Autobuffer)	*/
 #define NDSIZE_1		0x0100		/* Next Descriptor Size = 1						*/
 #define NDSIZE_2		0x0200		/* Next Descriptor Size = 2						*/
 #define NDSIZE_3		0x0300		/* Next Descriptor Size = 3						*/
 #define NDSIZE_4		0x0400		/* Next Descriptor Size = 4						*/
 #define NDSIZE_5		0x0500		/* Next Descriptor Size = 5						*/
 #define NDSIZE_6		0x0600		/* Next Descriptor Size = 6						*/
 #define NDSIZE_7		0x0700		/* Next Descriptor Size = 7						*/
 #define NDSIZE_8		0x0800		/* Next Descriptor Size = 8						*/
 #define NDSIZE_9		0x0900		/* Next Descriptor Size = 9						*/
 #define NDSIZE	        	0x0900	/* Next Descriptor Size */
 #define DMAFLOW	        	0x7000	/* Flow Control */
 #define DMAFLOW_STOP		0x0000		/* Stop Mode									*/
 #define DMAFLOW_AUTO		0x1000		/* Autobuffer Mode								*/
 #define DMAFLOW_ARRAY		0x4000		/* Descriptor Array Mode						*/
 #define DMAFLOW_SMALL		0x6000		/* Small Model Descriptor List Mode				*/
 #define DMAFLOW_LARGE		0x7000		/* Large Model Descriptor List Mode				*/
 /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks								*/
 #define CTYPE			0x0040	/* DMA Channel Type Indicator (Memory/Peripheral*)	*/
@ -1416,13 +1277,6 @@
 #define	PMAP_UART1RX	0xA000	/* 		UART1 Port Receive DMA						*/
 #define	PMAP_UART1TX	0xB000	/* 		UART1 Port Transmit DMA						*/
 /* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks						*/
 #define DMA_DONE		0x0001	/* DMA Completion Interrupt Status	*/
 #define DMA_ERR			0x0002	/* DMA Error Interrupt Status		*/
 #define DFETCH			0x0004	/* DMA Descriptor Fetch Indicator	*/
 #define DMA_RUN			0x0008	/* DMA Channel Running Indicator	*/
 /*  ************  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
 /*  PPI_CONTROL Masks													*/
 #define PORT_EN			0x0001		/* PPI Port Enable					*/
@ -1830,46 +1684,6 @@
 #define BNDMODE_CAPT     0x2000  /* boundary capture mode */
 #define BNDMODE_AEXT     0x3000  /* boundary auto-extend mode */
 /* Bit masks for OTP_CONTROL */
 #define                FUSE_FADDR  0x1ff      /* OTP/Fuse Address */
 #define                      FIEN  0x800      /* OTP/Fuse Interrupt Enable */
 #define                     nFIEN  0x0
 #define                  FTESTDEC  0x1000     /* OTP/Fuse Test Decoder */
 #define                 nFTESTDEC  0x0
 #define                   FWRTEST  0x2000     /* OTP/Fuse Write Test */
 #define                  nFWRTEST  0x0
 #define                     FRDEN  0x4000     /* OTP/Fuse Read Enable */
 #define                    nFRDEN  0x0
 #define                     FWREN  0x8000     /* OTP/Fuse Write Enable */
 #define                    nFWREN  0x0
 /* Bit masks for OTP_BEN */
 #define                      FBEN  0xffff     /* OTP/Fuse Byte Enable */
 /* Bit masks for OTP_STATUS */
 #define                     FCOMP  0x1        /* OTP/Fuse Access Complete */
 #define                    nFCOMP  0x0
 #define                    FERROR  0x2        /* OTP/Fuse Access Error */
 #define                   nFERROR  0x0
 #define                  MMRGLOAD  0x10       /* Memory Mapped Register Gasket Load */
 #define                 nMMRGLOAD  0x0
 #define                  MMRGLOCK  0x20       /* Memory Mapped Register Gasket Lock */
 #define                 nMMRGLOCK  0x0
 #define                    FPGMEN  0x40       /* OTP/Fuse Program Enable */
 #define                   nFPGMEN  0x0
 /* Bit masks for OTP_TIMING */
 #define                   USECDIV  0xff       /* Micro Second Divider */
 #define                   READACC  0x7f00     /* Read Access Time */
 #define                   CPUMPRL  0x38000    /* Charge Pump Release Time */
 #define                   CPUMPSU  0xc0000    /* Charge Pump Setup Time */
 #define                   CPUMPHD  0xf00000   /* Charge Pump Hold Time */
 #define                   PGMTIME  0xff000000 /* Program Time */
 /* Bit masks for SECURE_SYSSWT */
 #define                   EMUDABL  0x1        /* Emulation Disable. */
--- a/arch/blackfin/mach-bf527/Kconfig
+++ b/arch/blackfin/mach-bf527/Kconfig
@ -1,3 +1,7 @@
 config BF52x
 	def_bool y
 	depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
 if (BF52x)
 source "arch/blackfin/mach-bf527/boards/Kconfig"
--- a/arch/blackfin/mach-bf527/boards/cm_bf527.c
+++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c
@ -15,9 +15,6 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 #include <linux/etherdevice.h>
 #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
 #include <linux/usb/isp1362.h>
 #endif
 #include <linux/i2c.h>
 #include <linux/irq.h>
 #include <linux/interrupt.h>
@ -65,7 +62,7 @@ static struct isp1760_platform_data isp1760_priv = {
 };
 static struct platform_device bfin_isp1760_device = {
-	.name           = "isp1760-hcd",
+	.name           = "isp1760",
 	.id             = 0,
 	.dev = {
 		.platform_data = &isp1760_priv,
@ -317,45 +314,6 @@ static struct platform_device sl811_hcd_device = {
 };
 #endif
 #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
 static struct resource isp1362_hcd_resources[] = {
 	{
 		.start = 0x20360000,
 		.end = 0x20360000,
 		.flags = IORESOURCE_MEM,
 	}, {
 		.start = 0x20360004,
 		.end = 0x20360004,
 		.flags = IORESOURCE_MEM,
 	}, {
 		.start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
 		.end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
 		.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
 	},
 };
 static struct isp1362_platform_data isp1362_priv = {
 	.sel15Kres = 1,
 	.clknotstop = 0,
 	.oc_enable = 0,
 	.int_act_high = 0,
 	.int_edge_triggered = 0,
 	.remote_wakeup_connected = 0,
 	.no_power_switching = 1,
 	.power_switching_mode = 0,
 };
 static struct platform_device isp1362_hcd_device = {
 	.name = "isp1362-hcd",
 	.id = 0,
 	.dev = {
 		.platform_data = &isp1362_priv,
 	},
 	.num_resources = ARRAY_SIZE(isp1362_hcd_resources),
 	.resource = isp1362_hcd_resources,
 };
 #endif
 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
 static struct platform_device bfin_mii_bus = {
 	.name = "bfin_mii_bus",
@ -841,10 +799,6 @@ static struct platform_device *cmbf527_devices[] __initdata = {
 	&sl811_hcd_device,
 #endif
 #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
 	&isp1362_hcd_device,
 #endif
 #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
 	&bfin_isp1760_device,
 #endif
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@ -13,9 +13,6 @@
 #include <linux/mtd/physmap.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
 #include <linux/usb/isp1362.h>
 #endif
 #include <linux/i2c.h>
 #include <linux/irq.h>
 #include <linux/interrupt.h>
@ -63,7 +60,7 @@ static struct isp1760_platform_data isp1760_priv = {
 };
 static struct platform_device bfin_isp1760_device = {
-	.name           = "isp1760-hcd",
+	.name           = "isp1760",
 	.id             = 0,
 	.dev = {
 		.platform_data = &isp1760_priv,
@ -373,45 +370,6 @@ static struct platform_device sl811_hcd_device = {
 };
 #endif
 #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
 static struct resource isp1362_hcd_resources[] = {
 	{
 		.start = 0x20360000,
 		.end = 0x20360000,
 		.flags = IORESOURCE_MEM,
 	}, {
 		.start = 0x20360004,
 		.end = 0x20360004,
 		.flags = IORESOURCE_MEM,
 	}, {
 		.start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
 		.end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
 		.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
 	},
 };
 static struct isp1362_platform_data isp1362_priv = {
 	.sel15Kres = 1,
 	.clknotstop = 0,
 	.oc_enable = 0,
 	.int_act_high = 0,
 	.int_edge_triggered = 0,
 	.remote_wakeup_connected = 0,
 	.no_power_switching = 1,
 	.power_switching_mode = 0,
 };
 static struct platform_device isp1362_hcd_device = {
 	.name = "isp1362-hcd",
 	.id = 0,
 	.dev = {
 		.platform_data = &isp1362_priv,
 	},
 	.num_resources = ARRAY_SIZE(isp1362_hcd_resources),
 	.resource = isp1362_hcd_resources,
 };
 #endif
 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
 static struct platform_device bfin_mii_bus = {
 	.name = "bfin_mii_bus",
@ -688,12 +646,6 @@ static struct platform_device bfin_spi0_device = {
 };
 #endif  /* spi master and devices */
 #if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
 static struct platform_device bfin_fb_device = {
 	.name = "bf537-lq035",
 };
 #endif
 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
 static struct resource bfin_uart_resources[] = {
 #ifdef CONFIG_SERIAL_BFIN_UART0
@ -850,7 +802,7 @@ static struct platform_device bfin_device_gpiokeys = {
 };
 #endif
-#if defined(CONFIG_JOYSTICK_BFIN_ROTARY) || defined(CONFIG_JOYSTICK_BFIN_ROTARY_MODULE)
+#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
 #include <linux/input.h>
 #include <asm/bfin_rotary.h>
@ -924,10 +876,6 @@ static struct platform_device *stamp_devices[] __initdata = {
 	&sl811_hcd_device,
 #endif
 #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
 	&isp1362_hcd_device,
 #endif
 #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
 	&bfin_isp1760_device,
 #endif
@ -957,10 +905,6 @@ static struct platform_device *stamp_devices[] __initdata = {
 	&bfin_spi0_device,
 #endif
 #if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
 	&bfin_fb_device,
 #endif
 #if defined(CONFIG_FB_BFIN_T350MCQB) || defined(CONFIG_FB_BFIN_T350MCQB_MODULE)
 	&bf52x_t350mcqb_device,
 #endif
@ -991,7 +935,7 @@ static struct platform_device *stamp_devices[] __initdata = {
 	&bfin_device_gpiokeys,
 #endif
-#if defined(CONFIG_JOYSTICK_BFIN_ROTARY) || defined(CONFIG_JOYSTICK_BFIN_ROTARY_MODULE)
+#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
 	&bfin_rotary_device,
 #endif
--- a/arch/blackfin/mach-bf527/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf527/include/mach/blackfin.h
@ -46,10 +46,4 @@
 #define OFFSET_SCR              0x1C	/* SCR Scratch Register                 */
 #define OFFSET_GCTL             0x24	/* Global Control Register              */
 /* PLL_DIV Masks													*/
 #define CCLK_DIV1 CSEL_DIV1	/*          CCLK = VCO / 1                                  */
 #define CCLK_DIV2 CSEL_DIV2	/*          CCLK = VCO / 2                                  */
 #define CCLK_DIV4 CSEL_DIV4	/*          CCLK = VCO / 4                                  */
 #define CCLK_DIV8 CSEL_DIV8	/*          CCLK = VCO / 8                                  */
 #endif
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF525.h
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF525.h
@ -10,15 +10,8 @@
 /* include all Core registers and bit definitions */
 #include "defBF525.h"
-/* include core specific register pointer definitions */
+/* BF525 is BF522 + USB */
-#include <asm/cdef_LPBlackfin.h>
+#include "cdefBF522.h"
 /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */
 /* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
 #include "cdefBF52x_base.h"
 /* The following are the #defines needed by ADSP-BF525 that are not in the common header */
 /* USB Control Registers */
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF527.h
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF527.h
@ -10,15 +10,8 @@
 /* include all Core registers and bit definitions */
 #include "defBF527.h"
-/* include core specific register pointer definitions */
+/* BF527 is BF525 + EMAC */
-#include <asm/cdef_LPBlackfin.h>
+#include "cdefBF525.h"
 /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */
 /* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
 #include "cdefBF52x_base.h"
 /* The following are the #defines needed by ADSP-BF527 that are not in the common header */
 /* 10/100 Ethernet Controller	(0xFFC03000 - 0xFFC031FF) */
@ -185,417 +178,4 @@
 #define bfin_read_EMAC_TXC_ABORT()		bfin_read32(EMAC_TXC_ABORT)
 #define bfin_write_EMAC_TXC_ABORT(val)		bfin_write32(EMAC_TXC_ABORT, val)
 /* USB Control Registers */
 #define bfin_read_USB_FADDR()			bfin_read16(USB_FADDR)
 #define bfin_write_USB_FADDR(val)		bfin_write16(USB_FADDR, val)
 #define bfin_read_USB_POWER()			bfin_read16(USB_POWER)
 #define bfin_write_USB_POWER(val)		bfin_write16(USB_POWER, val)
 #define bfin_read_USB_INTRTX()			bfin_read16(USB_INTRTX)
 #define bfin_write_USB_INTRTX(val)		bfin_write16(USB_INTRTX, val)
 #define bfin_read_USB_INTRRX()			bfin_read16(USB_INTRRX)
 #define bfin_write_USB_INTRRX(val)		bfin_write16(USB_INTRRX, val)
 #define bfin_read_USB_INTRTXE()			bfin_read16(USB_INTRTXE)
 #define bfin_write_USB_INTRTXE(val)		bfin_write16(USB_INTRTXE, val)
 #define bfin_read_USB_INTRRXE()			bfin_read16(USB_INTRRXE)
 #define bfin_write_USB_INTRRXE(val)		bfin_write16(USB_INTRRXE, val)
 #define bfin_read_USB_INTRUSB()			bfin_read16(USB_INTRUSB)
 #define bfin_write_USB_INTRUSB(val)		bfin_write16(USB_INTRUSB, val)
 #define bfin_read_USB_INTRUSBE()		bfin_read16(USB_INTRUSBE)
 #define bfin_write_USB_INTRUSBE(val)		bfin_write16(USB_INTRUSBE, val)
 #define bfin_read_USB_FRAME()			bfin_read16(USB_FRAME)
 #define bfin_write_USB_FRAME(val)		bfin_write16(USB_FRAME, val)
 #define bfin_read_USB_INDEX()			bfin_read16(USB_INDEX)
 #define bfin_write_USB_INDEX(val)		bfin_write16(USB_INDEX, val)
 #define bfin_read_USB_TESTMODE()		bfin_read16(USB_TESTMODE)
 #define bfin_write_USB_TESTMODE(val)		bfin_write16(USB_TESTMODE, val)
 #define bfin_read_USB_GLOBINTR()		bfin_read16(USB_GLOBINTR)
 #define bfin_write_USB_GLOBINTR(val)		bfin_write16(USB_GLOBINTR, val)
 #define bfin_read_USB_GLOBAL_CTL()		bfin_read16(USB_GLOBAL_CTL)
 #define bfin_write_USB_GLOBAL_CTL(val)		bfin_write16(USB_GLOBAL_CTL, val)
 /* USB Packet Control Registers */
 #define bfin_read_USB_TX_MAX_PACKET()		bfin_read16(USB_TX_MAX_PACKET)
 #define bfin_write_USB_TX_MAX_PACKET(val)	bfin_write16(USB_TX_MAX_PACKET, val)
 #define bfin_read_USB_CSR0()			bfin_read16(USB_CSR0)
 #define bfin_write_USB_CSR0(val)		bfin_write16(USB_CSR0, val)
 #define bfin_read_USB_TXCSR()			bfin_read16(USB_TXCSR)
 #define bfin_write_USB_TXCSR(val)		bfin_write16(USB_TXCSR, val)
 #define bfin_read_USB_RX_MAX_PACKET()		bfin_read16(USB_RX_MAX_PACKET)
 #define bfin_write_USB_RX_MAX_PACKET(val)	bfin_write16(USB_RX_MAX_PACKET, val)
 #define bfin_read_USB_RXCSR()			bfin_read16(USB_RXCSR)
 #define bfin_write_USB_RXCSR(val)		bfin_write16(USB_RXCSR, val)
 #define bfin_read_USB_COUNT0()			bfin_read16(USB_COUNT0)
 #define bfin_write_USB_COUNT0(val)		bfin_write16(USB_COUNT0, val)
 #define bfin_read_USB_RXCOUNT()			bfin_read16(USB_RXCOUNT)
 #define bfin_write_USB_RXCOUNT(val)		bfin_write16(USB_RXCOUNT, val)
 #define bfin_read_USB_TXTYPE()			bfin_read16(USB_TXTYPE)
 #define bfin_write_USB_TXTYPE(val)		bfin_write16(USB_TXTYPE, val)
 #define bfin_read_USB_NAKLIMIT0()		bfin_read16(USB_NAKLIMIT0)
 #define bfin_write_USB_NAKLIMIT0(val)		bfin_write16(USB_NAKLIMIT0, val)
 #define bfin_read_USB_TXINTERVAL()		bfin_read16(USB_TXINTERVAL)
 #define bfin_write_USB_TXINTERVAL(val)		bfin_write16(USB_TXINTERVAL, val)
 #define bfin_read_USB_RXTYPE()			bfin_read16(USB_RXTYPE)
 #define bfin_write_USB_RXTYPE(val)		bfin_write16(USB_RXTYPE, val)
 #define bfin_read_USB_RXINTERVAL()		bfin_read16(USB_RXINTERVAL)
 #define bfin_write_USB_RXINTERVAL(val)		bfin_write16(USB_RXINTERVAL, val)
 #define bfin_read_USB_TXCOUNT()			bfin_read16(USB_TXCOUNT)
 #define bfin_write_USB_TXCOUNT(val)		bfin_write16(USB_TXCOUNT, val)
 /* USB Endpoint FIFO Registers */
 #define bfin_read_USB_EP0_FIFO()		bfin_read16(USB_EP0_FIFO)
 #define bfin_write_USB_EP0_FIFO(val)		bfin_write16(USB_EP0_FIFO, val)
 #define bfin_read_USB_EP1_FIFO()		bfin_read16(USB_EP1_FIFO)
 #define bfin_write_USB_EP1_FIFO(val)		bfin_write16(USB_EP1_FIFO, val)
 #define bfin_read_USB_EP2_FIFO()		bfin_read16(USB_EP2_FIFO)
 #define bfin_write_USB_EP2_FIFO(val)		bfin_write16(USB_EP2_FIFO, val)
 #define bfin_read_USB_EP3_FIFO()		bfin_read16(USB_EP3_FIFO)
 #define bfin_write_USB_EP3_FIFO(val)		bfin_write16(USB_EP3_FIFO, val)
 #define bfin_read_USB_EP4_FIFO()		bfin_read16(USB_EP4_FIFO)
 #define bfin_write_USB_EP4_FIFO(val)		bfin_write16(USB_EP4_FIFO, val)
 #define bfin_read_USB_EP5_FIFO()		bfin_read16(USB_EP5_FIFO)
 #define bfin_write_USB_EP5_FIFO(val)		bfin_write16(USB_EP5_FIFO, val)
 #define bfin_read_USB_EP6_FIFO()		bfin_read16(USB_EP6_FIFO)
 #define bfin_write_USB_EP6_FIFO(val)		bfin_write16(USB_EP6_FIFO, val)
 #define bfin_read_USB_EP7_FIFO()		bfin_read16(USB_EP7_FIFO)
 #define bfin_write_USB_EP7_FIFO(val)		bfin_write16(USB_EP7_FIFO, val)
 /* USB OTG Control Registers */
 #define bfin_read_USB_OTG_DEV_CTL()		bfin_read16(USB_OTG_DEV_CTL)
 #define bfin_write_USB_OTG_DEV_CTL(val)		bfin_write16(USB_OTG_DEV_CTL, val)
 #define bfin_read_USB_OTG_VBUS_IRQ()		bfin_read16(USB_OTG_VBUS_IRQ)
 #define bfin_write_USB_OTG_VBUS_IRQ(val)	bfin_write16(USB_OTG_VBUS_IRQ, val)
 #define bfin_read_USB_OTG_VBUS_MASK()		bfin_read16(USB_OTG_VBUS_MASK)
 #define bfin_write_USB_OTG_VBUS_MASK(val)	bfin_write16(USB_OTG_VBUS_MASK, val)
 /* USB Phy Control Registers */
 #define bfin_read_USB_LINKINFO()		bfin_read16(USB_LINKINFO)
 #define bfin_write_USB_LINKINFO(val)		bfin_write16(USB_LINKINFO, val)
 #define bfin_read_USB_VPLEN()			bfin_read16(USB_VPLEN)
 #define bfin_write_USB_VPLEN(val)		bfin_write16(USB_VPLEN, val)
 #define bfin_read_USB_HS_EOF1()			bfin_read16(USB_HS_EOF1)
 #define bfin_write_USB_HS_EOF1(val)		bfin_write16(USB_HS_EOF1, val)
 #define bfin_read_USB_FS_EOF1()			bfin_read16(USB_FS_EOF1)
 #define bfin_write_USB_FS_EOF1(val)		bfin_write16(USB_FS_EOF1, val)
 #define bfin_read_USB_LS_EOF1()			bfin_read16(USB_LS_EOF1)
 #define bfin_write_USB_LS_EOF1(val)		bfin_write16(USB_LS_EOF1, val)
 /* (APHY_CNTRL is for ADI usage only) */
 #define bfin_read_USB_APHY_CNTRL()		bfin_read16(USB_APHY_CNTRL)
 #define bfin_write_USB_APHY_CNTRL(val)		bfin_write16(USB_APHY_CNTRL, val)
 /* (APHY_CALIB is for ADI usage only) */
 #define bfin_read_USB_APHY_CALIB()		bfin_read16(USB_APHY_CALIB)
 #define bfin_write_USB_APHY_CALIB(val)		bfin_write16(USB_APHY_CALIB, val)
 #define bfin_read_USB_APHY_CNTRL2()		bfin_read16(USB_APHY_CNTRL2)
 #define bfin_write_USB_APHY_CNTRL2(val)		bfin_write16(USB_APHY_CNTRL2, val)
 /* (PHY_TEST is for ADI usage only) */
 #define bfin_read_USB_PHY_TEST()		bfin_read16(USB_PHY_TEST)
 #define bfin_write_USB_PHY_TEST(val)		bfin_write16(USB_PHY_TEST, val)
 #define bfin_read_USB_PLLOSC_CTRL()		bfin_read16(USB_PLLOSC_CTRL)
 #define bfin_write_USB_PLLOSC_CTRL(val)		bfin_write16(USB_PLLOSC_CTRL, val)
 #define bfin_read_USB_SRP_CLKDIV()		bfin_read16(USB_SRP_CLKDIV)
 #define bfin_write_USB_SRP_CLKDIV(val)		bfin_write16(USB_SRP_CLKDIV, val)
 /* USB Endpoint 0 Control Registers */
 #define bfin_read_USB_EP_NI0_TXMAXP()		bfin_read16(USB_EP_NI0_TXMAXP)
 #define bfin_write_USB_EP_NI0_TXMAXP(val)	bfin_write16(USB_EP_NI0_TXMAXP, val)
 #define bfin_read_USB_EP_NI0_TXCSR()		bfin_read16(USB_EP_NI0_TXCSR)
 #define bfin_write_USB_EP_NI0_TXCSR(val)	bfin_write16(USB_EP_NI0_TXCSR, val)
 #define bfin_read_USB_EP_NI0_RXMAXP()		bfin_read16(USB_EP_NI0_RXMAXP)
 #define bfin_write_USB_EP_NI0_RXMAXP(val)	bfin_write16(USB_EP_NI0_RXMAXP, val)
 #define bfin_read_USB_EP_NI0_RXCSR()		bfin_read16(USB_EP_NI0_RXCSR)
 #define bfin_write_USB_EP_NI0_RXCSR(val)	bfin_write16(USB_EP_NI0_RXCSR, val)
 #define bfin_read_USB_EP_NI0_RXCOUNT()		bfin_read16(USB_EP_NI0_RXCOUNT)
 #define bfin_write_USB_EP_NI0_RXCOUNT(val)	bfin_write16(USB_EP_NI0_RXCOUNT, val)
 #define bfin_read_USB_EP_NI0_TXTYPE()		bfin_read16(USB_EP_NI0_TXTYPE)
 #define bfin_write_USB_EP_NI0_TXTYPE(val)	bfin_write16(USB_EP_NI0_TXTYPE, val)
 #define bfin_read_USB_EP_NI0_TXINTERVAL()	bfin_read16(USB_EP_NI0_TXINTERVAL)
 #define bfin_write_USB_EP_NI0_TXINTERVAL(val)	bfin_write16(USB_EP_NI0_TXINTERVAL, val)
 #define bfin_read_USB_EP_NI0_RXTYPE()		bfin_read16(USB_EP_NI0_RXTYPE)
 #define bfin_write_USB_EP_NI0_RXTYPE(val)	bfin_write16(USB_EP_NI0_RXTYPE, val)
 #define bfin_read_USB_EP_NI0_RXINTERVAL()	bfin_read16(USB_EP_NI0_RXINTERVAL)
 #define bfin_write_USB_EP_NI0_RXINTERVAL(val)	bfin_write16(USB_EP_NI0_RXINTERVAL, val)
 #define bfin_read_USB_EP_NI0_TXCOUNT()		bfin_read16(USB_EP_NI0_TXCOUNT)
 #define bfin_write_USB_EP_NI0_TXCOUNT(val)	bfin_write16(USB_EP_NI0_TXCOUNT, val)
 /* USB Endpoint 1 Control Registers */
 #define bfin_read_USB_EP_NI1_TXMAXP()		bfin_read16(USB_EP_NI1_TXMAXP)
 #define bfin_write_USB_EP_NI1_TXMAXP(val)	bfin_write16(USB_EP_NI1_TXMAXP, val)
 #define bfin_read_USB_EP_NI1_TXCSR()		bfin_read16(USB_EP_NI1_TXCSR)
 #define bfin_write_USB_EP_NI1_TXCSR(val)	bfin_write16(USB_EP_NI1_TXCSR, val)
 #define bfin_read_USB_EP_NI1_RXMAXP()		bfin_read16(USB_EP_NI1_RXMAXP)
 #define bfin_write_USB_EP_NI1_RXMAXP(val)	bfin_write16(USB_EP_NI1_RXMAXP, val)
 #define bfin_read_USB_EP_NI1_RXCSR()		bfin_read16(USB_EP_NI1_RXCSR)
 #define bfin_write_USB_EP_NI1_RXCSR(val)	bfin_write16(USB_EP_NI1_RXCSR, val)
 #define bfin_read_USB_EP_NI1_RXCOUNT()		bfin_read16(USB_EP_NI1_RXCOUNT)
 #define bfin_write_USB_EP_NI1_RXCOUNT(val)	bfin_write16(USB_EP_NI1_RXCOUNT, val)
 #define bfin_read_USB_EP_NI1_TXTYPE()		bfin_read16(USB_EP_NI1_TXTYPE)
 #define bfin_write_USB_EP_NI1_TXTYPE(val)	bfin_write16(USB_EP_NI1_TXTYPE, val)
 #define bfin_read_USB_EP_NI1_TXINTERVAL()	bfin_read16(USB_EP_NI1_TXINTERVAL)
 #define bfin_write_USB_EP_NI1_TXINTERVAL(val)	bfin_write16(USB_EP_NI1_TXINTERVAL, val)
 #define bfin_read_USB_EP_NI1_RXTYPE()		bfin_read16(USB_EP_NI1_RXTYPE)
 #define bfin_write_USB_EP_NI1_RXTYPE(val)	bfin_write16(USB_EP_NI1_RXTYPE, val)
 #define bfin_read_USB_EP_NI1_RXINTERVAL()	bfin_read16(USB_EP_NI1_RXINTERVAL)
 #define bfin_write_USB_EP_NI1_RXINTERVAL(val)	bfin_write16(USB_EP_NI1_RXINTERVAL, val)
 #define bfin_read_USB_EP_NI1_TXCOUNT()		bfin_read16(USB_EP_NI1_TXCOUNT)
 #define bfin_write_USB_EP_NI1_TXCOUNT(val)	bfin_write16(USB_EP_NI1_TXCOUNT, val)
 /* USB Endpoint 2 Control Registers */
 #define bfin_read_USB_EP_NI2_TXMAXP()		bfin_read16(USB_EP_NI2_TXMAXP)
 #define bfin_write_USB_EP_NI2_TXMAXP(val)	bfin_write16(USB_EP_NI2_TXMAXP, val)
 #define bfin_read_USB_EP_NI2_TXCSR()		bfin_read16(USB_EP_NI2_TXCSR)
 #define bfin_write_USB_EP_NI2_TXCSR(val)	bfin_write16(USB_EP_NI2_TXCSR, val)
 #define bfin_read_USB_EP_NI2_RXMAXP()		bfin_read16(USB_EP_NI2_RXMAXP)
 #define bfin_write_USB_EP_NI2_RXMAXP(val)	bfin_write16(USB_EP_NI2_RXMAXP, val)
 #define bfin_read_USB_EP_NI2_RXCSR()		bfin_read16(USB_EP_NI2_RXCSR)
 #define bfin_write_USB_EP_NI2_RXCSR(val)	bfin_write16(USB_EP_NI2_RXCSR, val)
 #define bfin_read_USB_EP_NI2_RXCOUNT()		bfin_read16(USB_EP_NI2_RXCOUNT)
 #define bfin_write_USB_EP_NI2_RXCOUNT(val)	bfin_write16(USB_EP_NI2_RXCOUNT, val)
 #define bfin_read_USB_EP_NI2_TXTYPE()		bfin_read16(USB_EP_NI2_TXTYPE)
 #define bfin_write_USB_EP_NI2_TXTYPE(val)	bfin_write16(USB_EP_NI2_TXTYPE, val)
 #define bfin_read_USB_EP_NI2_TXINTERVAL()	bfin_read16(USB_EP_NI2_TXINTERVAL)
 #define bfin_write_USB_EP_NI2_TXINTERVAL(val)	bfin_write16(USB_EP_NI2_TXINTERVAL, val)
 #define bfin_read_USB_EP_NI2_RXTYPE()		bfin_read16(USB_EP_NI2_RXTYPE)
 #define bfin_write_USB_EP_NI2_RXTYPE(val)	bfin_write16(USB_EP_NI2_RXTYPE, val)
 #define bfin_read_USB_EP_NI2_RXINTERVAL()	bfin_read16(USB_EP_NI2_RXINTERVAL)
 #define bfin_write_USB_EP_NI2_RXINTERVAL(val)	bfin_write16(USB_EP_NI2_RXINTERVAL, val)
 #define bfin_read_USB_EP_NI2_TXCOUNT()		bfin_read16(USB_EP_NI2_TXCOUNT)
 #define bfin_write_USB_EP_NI2_TXCOUNT(val)	bfin_write16(USB_EP_NI2_TXCOUNT, val)
 /* USB Endpoint 3 Control Registers */
 #define bfin_read_USB_EP_NI3_TXMAXP()		bfin_read16(USB_EP_NI3_TXMAXP)
 #define bfin_write_USB_EP_NI3_TXMAXP(val)	bfin_write16(USB_EP_NI3_TXMAXP, val)
 #define bfin_read_USB_EP_NI3_TXCSR()		bfin_read16(USB_EP_NI3_TXCSR)
 #define bfin_write_USB_EP_NI3_TXCSR(val)	bfin_write16(USB_EP_NI3_TXCSR, val)
 #define bfin_read_USB_EP_NI3_RXMAXP()		bfin_read16(USB_EP_NI3_RXMAXP)
 #define bfin_write_USB_EP_NI3_RXMAXP(val)	bfin_write16(USB_EP_NI3_RXMAXP, val)
 #define bfin_read_USB_EP_NI3_RXCSR()		bfin_read16(USB_EP_NI3_RXCSR)
 #define bfin_write_USB_EP_NI3_RXCSR(val)	bfin_write16(USB_EP_NI3_RXCSR, val)
 #define bfin_read_USB_EP_NI3_RXCOUNT()		bfin_read16(USB_EP_NI3_RXCOUNT)
 #define bfin_write_USB_EP_NI3_RXCOUNT(val)	bfin_write16(USB_EP_NI3_RXCOUNT, val)
 #define bfin_read_USB_EP_NI3_TXTYPE()		bfin_read16(USB_EP_NI3_TXTYPE)
 #define bfin_write_USB_EP_NI3_TXTYPE(val)	bfin_write16(USB_EP_NI3_TXTYPE, val)
 #define bfin_read_USB_EP_NI3_TXINTERVAL()	bfin_read16(USB_EP_NI3_TXINTERVAL)
 #define bfin_write_USB_EP_NI3_TXINTERVAL(val)	bfin_write16(USB_EP_NI3_TXINTERVAL, val)
 #define bfin_read_USB_EP_NI3_RXTYPE()		bfin_read16(USB_EP_NI3_RXTYPE)
 #define bfin_write_USB_EP_NI3_RXTYPE(val)	bfin_write16(USB_EP_NI3_RXTYPE, val)
 #define bfin_read_USB_EP_NI3_RXINTERVAL()	bfin_read16(USB_EP_NI3_RXINTERVAL)
 #define bfin_write_USB_EP_NI3_RXINTERVAL(val)	bfin_write16(USB_EP_NI3_RXINTERVAL, val)
 #define bfin_read_USB_EP_NI3_TXCOUNT()		bfin_read16(USB_EP_NI3_TXCOUNT)
 #define bfin_write_USB_EP_NI3_TXCOUNT(val)	bfin_write16(USB_EP_NI3_TXCOUNT, val)
 /* USB Endpoint 4 Control Registers */
 #define bfin_read_USB_EP_NI4_TXMAXP()		bfin_read16(USB_EP_NI4_TXMAXP)
 #define bfin_write_USB_EP_NI4_TXMAXP(val)	bfin_write16(USB_EP_NI4_TXMAXP, val)
 #define bfin_read_USB_EP_NI4_TXCSR()		bfin_read16(USB_EP_NI4_TXCSR)
 #define bfin_write_USB_EP_NI4_TXCSR(val)	bfin_write16(USB_EP_NI4_TXCSR, val)
 #define bfin_read_USB_EP_NI4_RXMAXP()		bfin_read16(USB_EP_NI4_RXMAXP)
 #define bfin_write_USB_EP_NI4_RXMAXP(val)	bfin_write16(USB_EP_NI4_RXMAXP, val)
 #define bfin_read_USB_EP_NI4_RXCSR()		bfin_read16(USB_EP_NI4_RXCSR)
 #define bfin_write_USB_EP_NI4_RXCSR(val)	bfin_write16(USB_EP_NI4_RXCSR, val)
 #define bfin_read_USB_EP_NI4_RXCOUNT()		bfin_read16(USB_EP_NI4_RXCOUNT)
 #define bfin_write_USB_EP_NI4_RXCOUNT(val)	bfin_write16(USB_EP_NI4_RXCOUNT, val)
 #define bfin_read_USB_EP_NI4_TXTYPE()		bfin_read16(USB_EP_NI4_TXTYPE)
 #define bfin_write_USB_EP_NI4_TXTYPE(val)	bfin_write16(USB_EP_NI4_TXTYPE, val)
 #define bfin_read_USB_EP_NI4_TXINTERVAL()	bfin_read16(USB_EP_NI4_TXINTERVAL)
 #define bfin_write_USB_EP_NI4_TXINTERVAL(val)	bfin_write16(USB_EP_NI4_TXINTERVAL, val)
 #define bfin_read_USB_EP_NI4_RXTYPE()		bfin_read16(USB_EP_NI4_RXTYPE)
 #define bfin_write_USB_EP_NI4_RXTYPE(val)	bfin_write16(USB_EP_NI4_RXTYPE, val)
 #define bfin_read_USB_EP_NI4_RXINTERVAL()	bfin_read16(USB_EP_NI4_RXINTERVAL)
 #define bfin_write_USB_EP_NI4_RXINTERVAL(val)	bfin_write16(USB_EP_NI4_RXINTERVAL, val)
 #define bfin_read_USB_EP_NI4_TXCOUNT()		bfin_read16(USB_EP_NI4_TXCOUNT)
 #define bfin_write_USB_EP_NI4_TXCOUNT(val)	bfin_write16(USB_EP_NI4_TXCOUNT, val)
 /* USB Endpoint 5 Control Registers */
 #define bfin_read_USB_EP_NI5_TXMAXP()		bfin_read16(USB_EP_NI5_TXMAXP)
 #define bfin_write_USB_EP_NI5_TXMAXP(val)	bfin_write16(USB_EP_NI5_TXMAXP, val)
 #define bfin_read_USB_EP_NI5_TXCSR()		bfin_read16(USB_EP_NI5_TXCSR)
 #define bfin_write_USB_EP_NI5_TXCSR(val)	bfin_write16(USB_EP_NI5_TXCSR, val)
 #define bfin_read_USB_EP_NI5_RXMAXP()		bfin_read16(USB_EP_NI5_RXMAXP)
 #define bfin_write_USB_EP_NI5_RXMAXP(val)	bfin_write16(USB_EP_NI5_RXMAXP, val)
 #define bfin_read_USB_EP_NI5_RXCSR()		bfin_read16(USB_EP_NI5_RXCSR)
 #define bfin_write_USB_EP_NI5_RXCSR(val)	bfin_write16(USB_EP_NI5_RXCSR, val)
 #define bfin_read_USB_EP_NI5_RXCOUNT()		bfin_read16(USB_EP_NI5_RXCOUNT)
 #define bfin_write_USB_EP_NI5_RXCOUNT(val)	bfin_write16(USB_EP_NI5_RXCOUNT, val)
 #define bfin_read_USB_EP_NI5_TXTYPE()		bfin_read16(USB_EP_NI5_TXTYPE)
 #define bfin_write_USB_EP_NI5_TXTYPE(val)	bfin_write16(USB_EP_NI5_TXTYPE, val)
 #define bfin_read_USB_EP_NI5_TXINTERVAL()	bfin_read16(USB_EP_NI5_TXINTERVAL)
 #define bfin_write_USB_EP_NI5_TXINTERVAL(val)	bfin_write16(USB_EP_NI5_TXINTERVAL, val)
 #define bfin_read_USB_EP_NI5_RXTYPE()		bfin_read16(USB_EP_NI5_RXTYPE)
 #define bfin_write_USB_EP_NI5_RXTYPE(val)	bfin_write16(USB_EP_NI5_RXTYPE, val)
 #define bfin_read_USB_EP_NI5_RXINTERVAL()	bfin_read16(USB_EP_NI5_RXINTERVAL)
 #define bfin_write_USB_EP_NI5_RXINTERVAL(val)	bfin_write16(USB_EP_NI5_RXINTERVAL, val)
 #define bfin_read_USB_EP_NI5_TXCOUNT()		bfin_read16(USB_EP_NI5_TXCOUNT)
 #define bfin_write_USB_EP_NI5_TXCOUNT(val)	bfin_write16(USB_EP_NI5_TXCOUNT, val)
 /* USB Endpoint 6 Control Registers */
 #define bfin_read_USB_EP_NI6_TXMAXP()		bfin_read16(USB_EP_NI6_TXMAXP)
 #define bfin_write_USB_EP_NI6_TXMAXP(val)	bfin_write16(USB_EP_NI6_TXMAXP, val)
 #define bfin_read_USB_EP_NI6_TXCSR()		bfin_read16(USB_EP_NI6_TXCSR)
 #define bfin_write_USB_EP_NI6_TXCSR(val)	bfin_write16(USB_EP_NI6_TXCSR, val)
 #define bfin_read_USB_EP_NI6_RXMAXP()		bfin_read16(USB_EP_NI6_RXMAXP)
 #define bfin_write_USB_EP_NI6_RXMAXP(val)	bfin_write16(USB_EP_NI6_RXMAXP, val)
 #define bfin_read_USB_EP_NI6_RXCSR()		bfin_read16(USB_EP_NI6_RXCSR)
 #define bfin_write_USB_EP_NI6_RXCSR(val)	bfin_write16(USB_EP_NI6_RXCSR, val)
 #define bfin_read_USB_EP_NI6_RXCOUNT()		bfin_read16(USB_EP_NI6_RXCOUNT)
 #define bfin_write_USB_EP_NI6_RXCOUNT(val)	bfin_write16(USB_EP_NI6_RXCOUNT, val)
 #define bfin_read_USB_EP_NI6_TXTYPE()		bfin_read16(USB_EP_NI6_TXTYPE)
 #define bfin_write_USB_EP_NI6_TXTYPE(val)	bfin_write16(USB_EP_NI6_TXTYPE, val)
 #define bfin_read_USB_EP_NI6_TXINTERVAL()	bfin_read16(USB_EP_NI6_TXINTERVAL)
 #define bfin_write_USB_EP_NI6_TXINTERVAL(val)	bfin_write16(USB_EP_NI6_TXINTERVAL, val)
 #define bfin_read_USB_EP_NI6_RXTYPE()		bfin_read16(USB_EP_NI6_RXTYPE)
 #define bfin_write_USB_EP_NI6_RXTYPE(val)	bfin_write16(USB_EP_NI6_RXTYPE, val)
 #define bfin_read_USB_EP_NI6_RXINTERVAL()	bfin_read16(USB_EP_NI6_RXINTERVAL)
 #define bfin_write_USB_EP_NI6_RXINTERVAL(val)	bfin_write16(USB_EP_NI6_RXINTERVAL, val)
 #define bfin_read_USB_EP_NI6_TXCOUNT()		bfin_read16(USB_EP_NI6_TXCOUNT)
 #define bfin_write_USB_EP_NI6_TXCOUNT(val)	bfin_write16(USB_EP_NI6_TXCOUNT, val)
 /* USB Endpoint 7 Control Registers */
 #define bfin_read_USB_EP_NI7_TXMAXP()		bfin_read16(USB_EP_NI7_TXMAXP)
 #define bfin_write_USB_EP_NI7_TXMAXP(val)	bfin_write16(USB_EP_NI7_TXMAXP, val)
 #define bfin_read_USB_EP_NI7_TXCSR()		bfin_read16(USB_EP_NI7_TXCSR)
 #define bfin_write_USB_EP_NI7_TXCSR(val)	bfin_write16(USB_EP_NI7_TXCSR, val)
 #define bfin_read_USB_EP_NI7_RXMAXP()		bfin_read16(USB_EP_NI7_RXMAXP)
 #define bfin_write_USB_EP_NI7_RXMAXP(val)	bfin_write16(USB_EP_NI7_RXMAXP, val)
 #define bfin_read_USB_EP_NI7_RXCSR()		bfin_read16(USB_EP_NI7_RXCSR)
 #define bfin_write_USB_EP_NI7_RXCSR(val)	bfin_write16(USB_EP_NI7_RXCSR, val)
 #define bfin_read_USB_EP_NI7_RXCOUNT()		bfin_read16(USB_EP_NI7_RXCOUNT)
 #define bfin_write_USB_EP_NI7_RXCOUNT(val)	bfin_write16(USB_EP_NI7_RXCOUNT, val)
 #define bfin_read_USB_EP_NI7_TXTYPE()		bfin_read16(USB_EP_NI7_TXTYPE)
 #define bfin_write_USB_EP_NI7_TXTYPE(val)	bfin_write16(USB_EP_NI7_TXTYPE, val)
 #define bfin_read_USB_EP_NI7_TXINTERVAL()	bfin_read16(USB_EP_NI7_TXINTERVAL)
 #define bfin_write_USB_EP_NI7_TXINTERVAL(val)	bfin_write16(USB_EP_NI7_TXINTERVAL, val)
 #define bfin_read_USB_EP_NI7_RXTYPE()		bfin_read16(USB_EP_NI7_RXTYPE)
 #define bfin_write_USB_EP_NI7_RXTYPE(val)	bfin_write16(USB_EP_NI7_RXTYPE, val)
 #define bfin_read_USB_EP_NI7_RXINTERVAL()	bfin_read16(USB_EP_NI7_RXINTERVAL)
 #define bfin_write_USB_EP_NI7_RXINTERVAL(val)	bfin_write16(USB_EP_NI7_RXINTERVAL, val)
 #define bfin_read_USB_EP_NI7_TXCOUNT()		bfin_read16(USB_EP_NI7_TXCOUNT)
 #define bfin_write_USB_EP_NI7_TXCOUNT(val)	bfin_write16(USB_EP_NI7_TXCOUNT, val)
 #define bfin_read_USB_DMA_INTERRUPT()		bfin_read16(USB_DMA_INTERRUPT)
 #define bfin_write_USB_DMA_INTERRUPT(val)	bfin_write16(USB_DMA_INTERRUPT, val)
 /* USB Channel 0 Config Registers */
 #define bfin_read_USB_DMA0CONTROL()		bfin_read16(USB_DMA0CONTROL)
 #define bfin_write_USB_DMA0CONTROL(val)		bfin_write16(USB_DMA0CONTROL, val)
 #define bfin_read_USB_DMA0ADDRLOW()		bfin_read16(USB_DMA0ADDRLOW)
 #define bfin_write_USB_DMA0ADDRLOW(val)		bfin_write16(USB_DMA0ADDRLOW, val)
 #define bfin_read_USB_DMA0ADDRHIGH()		bfin_read16(USB_DMA0ADDRHIGH)
 #define bfin_write_USB_DMA0ADDRHIGH(val)	bfin_write16(USB_DMA0ADDRHIGH, val)
 #define bfin_read_USB_DMA0COUNTLOW()		bfin_read16(USB_DMA0COUNTLOW)
 #define bfin_write_USB_DMA0COUNTLOW(val)	bfin_write16(USB_DMA0COUNTLOW, val)
 #define bfin_read_USB_DMA0COUNTHIGH()		bfin_read16(USB_DMA0COUNTHIGH)
 #define bfin_write_USB_DMA0COUNTHIGH(val)	bfin_write16(USB_DMA0COUNTHIGH, val)
 /* USB Channel 1 Config Registers */
 #define bfin_read_USB_DMA1CONTROL()		bfin_read16(USB_DMA1CONTROL)
 #define bfin_write_USB_DMA1CONTROL(val)		bfin_write16(USB_DMA1CONTROL, val)
 #define bfin_read_USB_DMA1ADDRLOW()		bfin_read16(USB_DMA1ADDRLOW)
 #define bfin_write_USB_DMA1ADDRLOW(val)		bfin_write16(USB_DMA1ADDRLOW, val)
 #define bfin_read_USB_DMA1ADDRHIGH()		bfin_read16(USB_DMA1ADDRHIGH)
 #define bfin_write_USB_DMA1ADDRHIGH(val)	bfin_write16(USB_DMA1ADDRHIGH, val)
 #define bfin_read_USB_DMA1COUNTLOW()		bfin_read16(USB_DMA1COUNTLOW)
 #define bfin_write_USB_DMA1COUNTLOW(val)	bfin_write16(USB_DMA1COUNTLOW, val)
 #define bfin_read_USB_DMA1COUNTHIGH()		bfin_read16(USB_DMA1COUNTHIGH)
 #define bfin_write_USB_DMA1COUNTHIGH(val)	bfin_write16(USB_DMA1COUNTHIGH, val)
 /* USB Channel 2 Config Registers */
 #define bfin_read_USB_DMA2CONTROL()		bfin_read16(USB_DMA2CONTROL)
 #define bfin_write_USB_DMA2CONTROL(val)		bfin_write16(USB_DMA2CONTROL, val)
 #define bfin_read_USB_DMA2ADDRLOW()		bfin_read16(USB_DMA2ADDRLOW)
 #define bfin_write_USB_DMA2ADDRLOW(val)		bfin_write16(USB_DMA2ADDRLOW, val)
 #define bfin_read_USB_DMA2ADDRHIGH()		bfin_read16(USB_DMA2ADDRHIGH)
 #define bfin_write_USB_DMA2ADDRHIGH(val)	bfin_write16(USB_DMA2ADDRHIGH, val)
 #define bfin_read_USB_DMA2COUNTLOW()		bfin_read16(USB_DMA2COUNTLOW)
 #define bfin_write_USB_DMA2COUNTLOW(val)	bfin_write16(USB_DMA2COUNTLOW, val)
 #define bfin_read_USB_DMA2COUNTHIGH()		bfin_read16(USB_DMA2COUNTHIGH)
 #define bfin_write_USB_DMA2COUNTHIGH(val)	bfin_write16(USB_DMA2COUNTHIGH, val)
 /* USB Channel 3 Config Registers */
 #define bfin_read_USB_DMA3CONTROL()		bfin_read16(USB_DMA3CONTROL)
 #define bfin_write_USB_DMA3CONTROL(val)		bfin_write16(USB_DMA3CONTROL, val)
 #define bfin_read_USB_DMA3ADDRLOW()		bfin_read16(USB_DMA3ADDRLOW)
 #define bfin_write_USB_DMA3ADDRLOW(val)		bfin_write16(USB_DMA3ADDRLOW, val)
 #define bfin_read_USB_DMA3ADDRHIGH()		bfin_read16(USB_DMA3ADDRHIGH)
 #define bfin_write_USB_DMA3ADDRHIGH(val)	bfin_write16(USB_DMA3ADDRHIGH, val)
 #define bfin_read_USB_DMA3COUNTLOW()		bfin_read16(USB_DMA3COUNTLOW)
 #define bfin_write_USB_DMA3COUNTLOW(val)	bfin_write16(USB_DMA3COUNTLOW, val)
 #define bfin_read_USB_DMA3COUNTHIGH()		bfin_read16(USB_DMA3COUNTHIGH)
 #define bfin_write_USB_DMA3COUNTHIGH(val)	bfin_write16(USB_DMA3COUNTHIGH, val)
 /* USB Channel 4 Config Registers */
 #define bfin_read_USB_DMA4CONTROL()		bfin_read16(USB_DMA4CONTROL)
 #define bfin_write_USB_DMA4CONTROL(val)		bfin_write16(USB_DMA4CONTROL, val)
 #define bfin_read_USB_DMA4ADDRLOW()		bfin_read16(USB_DMA4ADDRLOW)
 #define bfin_write_USB_DMA4ADDRLOW(val)		bfin_write16(USB_DMA4ADDRLOW, val)
 #define bfin_read_USB_DMA4ADDRHIGH()		bfin_read16(USB_DMA4ADDRHIGH)
 #define bfin_write_USB_DMA4ADDRHIGH(val)	bfin_write16(USB_DMA4ADDRHIGH, val)
 #define bfin_read_USB_DMA4COUNTLOW()		bfin_read16(USB_DMA4COUNTLOW)
 #define bfin_write_USB_DMA4COUNTLOW(val)	bfin_write16(USB_DMA4COUNTLOW, val)
 #define bfin_read_USB_DMA4COUNTHIGH()		bfin_read16(USB_DMA4COUNTHIGH)
 #define bfin_write_USB_DMA4COUNTHIGH(val)	bfin_write16(USB_DMA4COUNTHIGH, val)
 /* USB Channel 5 Config Registers */
 #define bfin_read_USB_DMA5CONTROL()		bfin_read16(USB_DMA5CONTROL)
 #define bfin_write_USB_DMA5CONTROL(val)		bfin_write16(USB_DMA5CONTROL, val)
 #define bfin_read_USB_DMA5ADDRLOW()		bfin_read16(USB_DMA5ADDRLOW)
 #define bfin_write_USB_DMA5ADDRLOW(val)		bfin_write16(USB_DMA5ADDRLOW, val)
 #define bfin_read_USB_DMA5ADDRHIGH()		bfin_read16(USB_DMA5ADDRHIGH)
 #define bfin_write_USB_DMA5ADDRHIGH(val)	bfin_write16(USB_DMA5ADDRHIGH, val)
 #define bfin_read_USB_DMA5COUNTLOW()		bfin_read16(USB_DMA5COUNTLOW)
 #define bfin_write_USB_DMA5COUNTLOW(val)	bfin_write16(USB_DMA5COUNTLOW, val)
 #define bfin_read_USB_DMA5COUNTHIGH()		bfin_read16(USB_DMA5COUNTHIGH)
 #define bfin_write_USB_DMA5COUNTHIGH(val)	bfin_write16(USB_DMA5COUNTHIGH, val)
 /* USB Channel 6 Config Registers */
 #define bfin_read_USB_DMA6CONTROL()		bfin_read16(USB_DMA6CONTROL)
 #define bfin_write_USB_DMA6CONTROL(val)		bfin_write16(USB_DMA6CONTROL, val)
 #define bfin_read_USB_DMA6ADDRLOW()		bfin_read16(USB_DMA6ADDRLOW)
 #define bfin_write_USB_DMA6ADDRLOW(val)		bfin_write16(USB_DMA6ADDRLOW, val)
 #define bfin_read_USB_DMA6ADDRHIGH()		bfin_read16(USB_DMA6ADDRHIGH)
 #define bfin_write_USB_DMA6ADDRHIGH(val)	bfin_write16(USB_DMA6ADDRHIGH, val)
 #define bfin_read_USB_DMA6COUNTLOW()		bfin_read16(USB_DMA6COUNTLOW)
 #define bfin_write_USB_DMA6COUNTLOW(val)	bfin_write16(USB_DMA6COUNTLOW, val)
 #define bfin_read_USB_DMA6COUNTHIGH()		bfin_read16(USB_DMA6COUNTHIGH)
 #define bfin_write_USB_DMA6COUNTHIGH(val)	bfin_write16(USB_DMA6COUNTHIGH, val)
 /* USB Channel 7 Config Registers */
 #define bfin_read_USB_DMA7CONTROL()		bfin_read16(USB_DMA7CONTROL)
 #define bfin_write_USB_DMA7CONTROL(val)		bfin_write16(USB_DMA7CONTROL, val)
 #define bfin_read_USB_DMA7ADDRLOW()		bfin_read16(USB_DMA7ADDRLOW)
 #define bfin_write_USB_DMA7ADDRLOW(val)		bfin_write16(USB_DMA7ADDRLOW, val)
 #define bfin_read_USB_DMA7ADDRHIGH()		bfin_read16(USB_DMA7ADDRHIGH)
 #define bfin_write_USB_DMA7ADDRHIGH(val)	bfin_write16(USB_DMA7ADDRHIGH, val)
 #define bfin_read_USB_DMA7COUNTLOW()		bfin_read16(USB_DMA7COUNTLOW)
 #define bfin_write_USB_DMA7COUNTLOW(val)	bfin_write16(USB_DMA7COUNTLOW, val)
 #define bfin_read_USB_DMA7COUNTHIGH()		bfin_read16(USB_DMA7COUNTHIGH)
 #define bfin_write_USB_DMA7COUNTHIGH(val)	bfin_write16(USB_DMA7COUNTHIGH, val)
 #endif /* _CDEF_BF527_H */
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
@ -844,6 +844,7 @@
 #define bfin_write_PPI_CONTROL(val)		bfin_write16(PPI_CONTROL, val)
 #define bfin_read_PPI_STATUS()			bfin_read16(PPI_STATUS)
 #define bfin_write_PPI_STATUS(val)		bfin_write16(PPI_STATUS, val)
 #define bfin_clear_PPI_STATUS()			bfin_write_PPI_STATUS(0xFFFF)
 #define bfin_read_PPI_DELAY()			bfin_read16(PPI_DELAY)
 #define bfin_write_PPI_DELAY(val)		bfin_write16(PPI_DELAY, val)
 #define bfin_read_PPI_COUNT()			bfin_read16(PPI_COUNT)
@ -1062,17 +1063,6 @@
 #define bfin_read_CNT_MIN()			bfin_read32(CNT_MIN)
 #define bfin_write_CNT_MIN(val)			bfin_write32(CNT_MIN, val)
 /* OTP/FUSE Registers */
 #define bfin_read_OTP_CONTROL()			bfin_read16(OTP_CONTROL)
 #define bfin_write_OTP_CONTROL(val)		bfin_write16(OTP_CONTROL, val)
 #define bfin_read_OTP_BEN()			bfin_read16(OTP_BEN)
 #define bfin_write_OTP_BEN(val)			bfin_write16(OTP_BEN, val)
 #define bfin_read_OTP_STATUS()			bfin_read16(OTP_STATUS)
 #define bfin_write_OTP_STATUS(val)		bfin_write16(OTP_STATUS, val)
 #define bfin_read_OTP_TIMING()			bfin_read32(OTP_TIMING)
 #define bfin_write_OTP_TIMING(val)		bfin_write32(OTP_TIMING, val)
 /* Security Registers */
 #define bfin_read_SECURE_SYSSWT()		bfin_read32(SECURE_SYSSWT)
@ -1082,17 +1072,6 @@
 #define bfin_read_SECURE_STATUS()		bfin_read16(SECURE_STATUS)
 #define bfin_write_SECURE_STATUS(val)		bfin_write16(SECURE_STATUS, val)
 /* OTP Read/Write Data Buffer Registers */
 #define bfin_read_OTP_DATA0()			bfin_read32(OTP_DATA0)
 #define bfin_write_OTP_DATA0(val)		bfin_write32(OTP_DATA0, val)
 #define bfin_read_OTP_DATA1()			bfin_read32(OTP_DATA1)
 #define bfin_write_OTP_DATA1(val)		bfin_write32(OTP_DATA1, val)
 #define bfin_read_OTP_DATA2()			bfin_read32(OTP_DATA2)
 #define bfin_write_OTP_DATA2(val)		bfin_write32(OTP_DATA2, val)
 #define bfin_read_OTP_DATA3()			bfin_read32(OTP_DATA3)
 #define bfin_write_OTP_DATA3(val)		bfin_write32(OTP_DATA3, val)
 /* NFC Registers */
 #define bfin_read_NFC_CTL()			bfin_read16(NFC_CTL)
--- a/arch/blackfin/mach-bf527/include/mach/defBF525.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF525.h
@ -7,15 +7,8 @@
 #ifndef _DEF_BF525_H
 #define _DEF_BF525_H
-/* Include all Core registers and bit definitions */
+/* BF525 is BF522 + USB */
-#include <asm/def_LPBlackfin.h>
+#include "defBF522.h"
 /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */
 /* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
 #include "defBF52x_base.h"
 /* The following are the #defines needed by ADSP-BF525 that are not in the common header */
 /* USB Control Registers */
--- a/arch/blackfin/mach-bf527/include/mach/defBF527.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF527.h
@ -7,15 +7,9 @@
 #ifndef _DEF_BF527_H
 #define _DEF_BF527_H
-/* Include all Core registers and bit definitions */
+/* BF527 is BF525 + EMAC */
-#include <asm/def_LPBlackfin.h>
+#include "defBF525.h"
 /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */
 /* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
 #include "defBF52x_base.h"
 /* The following are the #defines needed by ADSP-BF527 that are not in the common header */
 /* 10/100 Ethernet Controller	(0xFFC03000 - 0xFFC031FF) */
 #define EMAC_OPMODE             0xFFC03000       /* Operating Mode Register                              */
@ -394,673 +388,4 @@
 #define	TX_GE1024_CNT     0x00200000    /* 1024-Max-Byte TX Frames Sent                           */
 #define	TX_ABORT_CNT      0x00400000    /* TX Frames Aborted                                      */
 /* USB Control Registers */
 #define                        USB_FADDR  0xffc03800   /* Function address register */
 #define                        USB_POWER  0xffc03804   /* Power management register */
 #define                       USB_INTRTX  0xffc03808   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
 #define                       USB_INTRRX  0xffc0380c   /* Interrupt register for Rx endpoints 1 to 7 */
 #define                      USB_INTRTXE  0xffc03810   /* Interrupt enable register for IntrTx */
 #define                      USB_INTRRXE  0xffc03814   /* Interrupt enable register for IntrRx */
 #define                      USB_INTRUSB  0xffc03818   /* Interrupt register for common USB interrupts */
 #define                     USB_INTRUSBE  0xffc0381c   /* Interrupt enable register for IntrUSB */
 #define                        USB_FRAME  0xffc03820   /* USB frame number */
 #define                        USB_INDEX  0xffc03824   /* Index register for selecting the indexed endpoint registers */
 #define                     USB_TESTMODE  0xffc03828   /* Enabled USB 20 test modes */
 #define                     USB_GLOBINTR  0xffc0382c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
 #define                   USB_GLOBAL_CTL  0xffc03830   /* Global Clock Control for the core */
 /* USB Packet Control Registers */
 #define                USB_TX_MAX_PACKET  0xffc03840   /* Maximum packet size for Host Tx endpoint */
 #define                         USB_CSR0  0xffc03844   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
 #define                        USB_TXCSR  0xffc03844   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
 #define                USB_RX_MAX_PACKET  0xffc03848   /* Maximum packet size for Host Rx endpoint */
 #define                        USB_RXCSR  0xffc0384c   /* Control Status register for Host Rx endpoint */
 #define                       USB_COUNT0  0xffc03850   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
 #define                      USB_RXCOUNT  0xffc03850   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
 #define                       USB_TXTYPE  0xffc03854   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
 #define                    USB_NAKLIMIT0  0xffc03858   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
 #define                   USB_TXINTERVAL  0xffc03858   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
 #define                       USB_RXTYPE  0xffc0385c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
 #define                   USB_RXINTERVAL  0xffc03860   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
 #define                      USB_TXCOUNT  0xffc03868   /* Number of bytes to be written to the selected endpoint Tx FIFO */
 /* USB Endpoint FIFO Registers */
 #define                     USB_EP0_FIFO  0xffc03880   /* Endpoint 0 FIFO */
 #define                     USB_EP1_FIFO  0xffc03888   /* Endpoint 1 FIFO */
 #define                     USB_EP2_FIFO  0xffc03890   /* Endpoint 2 FIFO */
 #define                     USB_EP3_FIFO  0xffc03898   /* Endpoint 3 FIFO */
 #define                     USB_EP4_FIFO  0xffc038a0   /* Endpoint 4 FIFO */
 #define                     USB_EP5_FIFO  0xffc038a8   /* Endpoint 5 FIFO */
 #define                     USB_EP6_FIFO  0xffc038b0   /* Endpoint 6 FIFO */
 #define                     USB_EP7_FIFO  0xffc038b8   /* Endpoint 7 FIFO */
 /* USB OTG Control Registers */
 #define                  USB_OTG_DEV_CTL  0xffc03900   /* OTG Device Control Register */
 #define                 USB_OTG_VBUS_IRQ  0xffc03904   /* OTG VBUS Control Interrupts */
 #define                USB_OTG_VBUS_MASK  0xffc03908   /* VBUS Control Interrupt Enable */
 /* USB Phy Control Registers */
 #define                     USB_LINKINFO  0xffc03948   /* Enables programming of some PHY-side delays */
 #define                        USB_VPLEN  0xffc0394c   /* Determines duration of VBUS pulse for VBUS charging */
 #define                      USB_HS_EOF1  0xffc03950   /* Time buffer for High-Speed transactions */
 #define                      USB_FS_EOF1  0xffc03954   /* Time buffer for Full-Speed transactions */
 #define                      USB_LS_EOF1  0xffc03958   /* Time buffer for Low-Speed transactions */
 /* (APHY_CNTRL is for ADI usage only) */
 #define                   USB_APHY_CNTRL  0xffc039e0   /* Register that increases visibility of Analog PHY */
 /* (APHY_CALIB is for ADI usage only) */
 #define                   USB_APHY_CALIB  0xffc039e4   /* Register used to set some calibration values */
 #define                  USB_APHY_CNTRL2  0xffc039e8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
 /* (PHY_TEST is for ADI usage only) */
 #define                     USB_PHY_TEST  0xffc039ec   /* Used for reducing simulation time and simplifies FIFO testability */
 #define                  USB_PLLOSC_CTRL  0xffc039f0   /* Used to program different parameters for USB PLL and Oscillator */
 #define                   USB_SRP_CLKDIV  0xffc039f4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
 /* USB Endpoint 0 Control Registers */
 #define                USB_EP_NI0_TXMAXP  0xffc03a00   /* Maximum packet size for Host Tx endpoint0 */
 #define                 USB_EP_NI0_TXCSR  0xffc03a04   /* Control Status register for endpoint 0 */
 #define                USB_EP_NI0_RXMAXP  0xffc03a08   /* Maximum packet size for Host Rx endpoint0 */
 #define                 USB_EP_NI0_RXCSR  0xffc03a0c   /* Control Status register for Host Rx endpoint0 */
 #define               USB_EP_NI0_RXCOUNT  0xffc03a10   /* Number of bytes received in endpoint 0 FIFO */
 #define                USB_EP_NI0_TXTYPE  0xffc03a14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
 #define            USB_EP_NI0_TXINTERVAL  0xffc03a18   /* Sets the NAK response timeout on Endpoint 0 */
 #define                USB_EP_NI0_RXTYPE  0xffc03a1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
 #define            USB_EP_NI0_RXINTERVAL  0xffc03a20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
 #define               USB_EP_NI0_TXCOUNT  0xffc03a28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
 /* USB Endpoint 1 Control Registers */
 #define                USB_EP_NI1_TXMAXP  0xffc03a40   /* Maximum packet size for Host Tx endpoint1 */
 #define                 USB_EP_NI1_TXCSR  0xffc03a44   /* Control Status register for endpoint1 */
 #define                USB_EP_NI1_RXMAXP  0xffc03a48   /* Maximum packet size for Host Rx endpoint1 */
 #define                 USB_EP_NI1_RXCSR  0xffc03a4c   /* Control Status register for Host Rx endpoint1 */
 #define               USB_EP_NI1_RXCOUNT  0xffc03a50   /* Number of bytes received in endpoint1 FIFO */
 #define                USB_EP_NI1_TXTYPE  0xffc03a54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
 #define            USB_EP_NI1_TXINTERVAL  0xffc03a58   /* Sets the NAK response timeout on Endpoint1 */
 #define                USB_EP_NI1_RXTYPE  0xffc03a5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
 #define            USB_EP_NI1_RXINTERVAL  0xffc03a60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
 #define               USB_EP_NI1_TXCOUNT  0xffc03a68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
 /* USB Endpoint 2 Control Registers */
 #define                USB_EP_NI2_TXMAXP  0xffc03a80   /* Maximum packet size for Host Tx endpoint2 */
 #define                 USB_EP_NI2_TXCSR  0xffc03a84   /* Control Status register for endpoint2 */
 #define                USB_EP_NI2_RXMAXP  0xffc03a88   /* Maximum packet size for Host Rx endpoint2 */
 #define                 USB_EP_NI2_RXCSR  0xffc03a8c   /* Control Status register for Host Rx endpoint2 */
 #define               USB_EP_NI2_RXCOUNT  0xffc03a90   /* Number of bytes received in endpoint2 FIFO */
 #define                USB_EP_NI2_TXTYPE  0xffc03a94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
 #define            USB_EP_NI2_TXINTERVAL  0xffc03a98   /* Sets the NAK response timeout on Endpoint2 */
 #define                USB_EP_NI2_RXTYPE  0xffc03a9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
 #define            USB_EP_NI2_RXINTERVAL  0xffc03aa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
 #define               USB_EP_NI2_TXCOUNT  0xffc03aa8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
 /* USB Endpoint 3 Control Registers */
 #define                USB_EP_NI3_TXMAXP  0xffc03ac0   /* Maximum packet size for Host Tx endpoint3 */
 #define                 USB_EP_NI3_TXCSR  0xffc03ac4   /* Control Status register for endpoint3 */
 #define                USB_EP_NI3_RXMAXP  0xffc03ac8   /* Maximum packet size for Host Rx endpoint3 */
 #define                 USB_EP_NI3_RXCSR  0xffc03acc   /* Control Status register for Host Rx endpoint3 */
 #define               USB_EP_NI3_RXCOUNT  0xffc03ad0   /* Number of bytes received in endpoint3 FIFO */
 #define                USB_EP_NI3_TXTYPE  0xffc03ad4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
 #define            USB_EP_NI3_TXINTERVAL  0xffc03ad8   /* Sets the NAK response timeout on Endpoint3 */
 #define                USB_EP_NI3_RXTYPE  0xffc03adc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
 #define            USB_EP_NI3_RXINTERVAL  0xffc03ae0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
 #define               USB_EP_NI3_TXCOUNT  0xffc03ae8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
 /* USB Endpoint 4 Control Registers */
 #define                USB_EP_NI4_TXMAXP  0xffc03b00   /* Maximum packet size for Host Tx endpoint4 */
 #define                 USB_EP_NI4_TXCSR  0xffc03b04   /* Control Status register for endpoint4 */
 #define                USB_EP_NI4_RXMAXP  0xffc03b08   /* Maximum packet size for Host Rx endpoint4 */
 #define                 USB_EP_NI4_RXCSR  0xffc03b0c   /* Control Status register for Host Rx endpoint4 */
 #define               USB_EP_NI4_RXCOUNT  0xffc03b10   /* Number of bytes received in endpoint4 FIFO */
 #define                USB_EP_NI4_TXTYPE  0xffc03b14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
 #define            USB_EP_NI4_TXINTERVAL  0xffc03b18   /* Sets the NAK response timeout on Endpoint4 */
 #define                USB_EP_NI4_RXTYPE  0xffc03b1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
 #define            USB_EP_NI4_RXINTERVAL  0xffc03b20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
 #define               USB_EP_NI4_TXCOUNT  0xffc03b28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
 /* USB Endpoint 5 Control Registers */
 #define                USB_EP_NI5_TXMAXP  0xffc03b40   /* Maximum packet size for Host Tx endpoint5 */
 #define                 USB_EP_NI5_TXCSR  0xffc03b44   /* Control Status register for endpoint5 */
 #define                USB_EP_NI5_RXMAXP  0xffc03b48   /* Maximum packet size for Host Rx endpoint5 */
 #define                 USB_EP_NI5_RXCSR  0xffc03b4c   /* Control Status register for Host Rx endpoint5 */
 #define               USB_EP_NI5_RXCOUNT  0xffc03b50   /* Number of bytes received in endpoint5 FIFO */
 #define                USB_EP_NI5_TXTYPE  0xffc03b54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
 #define            USB_EP_NI5_TXINTERVAL  0xffc03b58   /* Sets the NAK response timeout on Endpoint5 */
 #define                USB_EP_NI5_RXTYPE  0xffc03b5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
 #define            USB_EP_NI5_RXINTERVAL  0xffc03b60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
 #define               USB_EP_NI5_TXCOUNT  0xffc03b68   /* Number of bytes to be written to the endpoint5 Tx FIFO */
 /* USB Endpoint 6 Control Registers */
 #define                USB_EP_NI6_TXMAXP  0xffc03b80   /* Maximum packet size for Host Tx endpoint6 */
 #define                 USB_EP_NI6_TXCSR  0xffc03b84   /* Control Status register for endpoint6 */
 #define                USB_EP_NI6_RXMAXP  0xffc03b88   /* Maximum packet size for Host Rx endpoint6 */
 #define                 USB_EP_NI6_RXCSR  0xffc03b8c   /* Control Status register for Host Rx endpoint6 */
 #define               USB_EP_NI6_RXCOUNT  0xffc03b90   /* Number of bytes received in endpoint6 FIFO */
 #define                USB_EP_NI6_TXTYPE  0xffc03b94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
 #define            USB_EP_NI6_TXINTERVAL  0xffc03b98   /* Sets the NAK response timeout on Endpoint6 */
 #define                USB_EP_NI6_RXTYPE  0xffc03b9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
 #define            USB_EP_NI6_RXINTERVAL  0xffc03ba0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
 #define               USB_EP_NI6_TXCOUNT  0xffc03ba8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
 /* USB Endpoint 7 Control Registers */
 #define                USB_EP_NI7_TXMAXP  0xffc03bc0   /* Maximum packet size for Host Tx endpoint7 */
 #define                 USB_EP_NI7_TXCSR  0xffc03bc4   /* Control Status register for endpoint7 */
 #define                USB_EP_NI7_RXMAXP  0xffc03bc8   /* Maximum packet size for Host Rx endpoint7 */
 #define                 USB_EP_NI7_RXCSR  0xffc03bcc   /* Control Status register for Host Rx endpoint7 */
 #define               USB_EP_NI7_RXCOUNT  0xffc03bd0   /* Number of bytes received in endpoint7 FIFO */
 #define                USB_EP_NI7_TXTYPE  0xffc03bd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
 #define            USB_EP_NI7_TXINTERVAL  0xffc03bd8   /* Sets the NAK response timeout on Endpoint7 */
 #define                USB_EP_NI7_RXTYPE  0xffc03bdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
 #define            USB_EP_NI7_RXINTERVAL  0xffc03bf0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
 #define               USB_EP_NI7_TXCOUNT  0xffc03bf8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
 #define                USB_DMA_INTERRUPT  0xffc03c00   /* Indicates pending interrupts for the DMA channels */
 /* USB Channel 0 Config Registers */
 #define                  USB_DMA0CONTROL  0xffc03c04   /* DMA master channel 0 configuration */
 #define                  USB_DMA0ADDRLOW  0xffc03c08   /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
 #define                 USB_DMA0ADDRHIGH  0xffc03c0c   /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
 #define                 USB_DMA0COUNTLOW  0xffc03c10   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
 #define                USB_DMA0COUNTHIGH  0xffc03c14   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
 /* USB Channel 1 Config Registers */
 #define                  USB_DMA1CONTROL  0xffc03c24   /* DMA master channel 1 configuration */
 #define                  USB_DMA1ADDRLOW  0xffc03c28   /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
 #define                 USB_DMA1ADDRHIGH  0xffc03c2c   /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
 #define                 USB_DMA1COUNTLOW  0xffc03c30   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
 #define                USB_DMA1COUNTHIGH  0xffc03c34   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
 /* USB Channel 2 Config Registers */
 #define                  USB_DMA2CONTROL  0xffc03c44   /* DMA master channel 2 configuration */
 #define                  USB_DMA2ADDRLOW  0xffc03c48   /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
 #define                 USB_DMA2ADDRHIGH  0xffc03c4c   /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
 #define                 USB_DMA2COUNTLOW  0xffc03c50   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
 #define                USB_DMA2COUNTHIGH  0xffc03c54   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
 /* USB Channel 3 Config Registers */
 #define                  USB_DMA3CONTROL  0xffc03c64   /* DMA master channel 3 configuration */
 #define                  USB_DMA3ADDRLOW  0xffc03c68   /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
 #define                 USB_DMA3ADDRHIGH  0xffc03c6c   /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
 #define                 USB_DMA3COUNTLOW  0xffc03c70   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
 #define                USB_DMA3COUNTHIGH  0xffc03c74   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
 /* USB Channel 4 Config Registers */
 #define                  USB_DMA4CONTROL  0xffc03c84   /* DMA master channel 4 configuration */
 #define                  USB_DMA4ADDRLOW  0xffc03c88   /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
 #define                 USB_DMA4ADDRHIGH  0xffc03c8c   /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
 #define                 USB_DMA4COUNTLOW  0xffc03c90   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
 #define                USB_DMA4COUNTHIGH  0xffc03c94   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
 /* USB Channel 5 Config Registers */
 #define                  USB_DMA5CONTROL  0xffc03ca4   /* DMA master channel 5 configuration */
 #define                  USB_DMA5ADDRLOW  0xffc03ca8   /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
 #define                 USB_DMA5ADDRHIGH  0xffc03cac   /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
 #define                 USB_DMA5COUNTLOW  0xffc03cb0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
 #define                USB_DMA5COUNTHIGH  0xffc03cb4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
 /* USB Channel 6 Config Registers */
 #define                  USB_DMA6CONTROL  0xffc03cc4   /* DMA master channel 6 configuration */
 #define                  USB_DMA6ADDRLOW  0xffc03cc8   /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
 #define                 USB_DMA6ADDRHIGH  0xffc03ccc   /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
 #define                 USB_DMA6COUNTLOW  0xffc03cd0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
 #define                USB_DMA6COUNTHIGH  0xffc03cd4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
 /* USB Channel 7 Config Registers */
 #define                  USB_DMA7CONTROL  0xffc03ce4   /* DMA master channel 7 configuration */
 #define                  USB_DMA7ADDRLOW  0xffc03ce8   /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
 #define                 USB_DMA7ADDRHIGH  0xffc03cec   /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
 #define                 USB_DMA7COUNTLOW  0xffc03cf0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
 #define                USB_DMA7COUNTHIGH  0xffc03cf4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
 /* Bit masks for USB_FADDR */
 #define          FUNCTION_ADDRESS  0x7f       /* Function address */
 /* Bit masks for USB_POWER */
 #define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
 #define          nENABLE_SUSPENDM  0x0       
 #define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
 #define             nSUSPEND_MODE  0x0       
 #define               RESUME_MODE  0x4        /* DMA Mode */
 #define              nRESUME_MODE  0x0       
 #define                     RESET  0x8        /* Reset indicator */
 #define                    nRESET  0x0       
 #define                   HS_MODE  0x10       /* High Speed mode indicator */
 #define                  nHS_MODE  0x0       
 #define                 HS_ENABLE  0x20       /* high Speed Enable */
 #define                nHS_ENABLE  0x0       
 #define                 SOFT_CONN  0x40       /* Soft connect */
 #define                nSOFT_CONN  0x0       
 #define                ISO_UPDATE  0x80       /* Isochronous update */
 #define               nISO_UPDATE  0x0       
 /* Bit masks for USB_INTRTX */
 #define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
 #define                   nEP0_TX  0x0       
 #define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
 #define                   nEP1_TX  0x0       
 #define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
 #define                   nEP2_TX  0x0       
 #define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
 #define                   nEP3_TX  0x0       
 #define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
 #define                   nEP4_TX  0x0       
 #define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
 #define                   nEP5_TX  0x0       
 #define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
 #define                   nEP6_TX  0x0       
 #define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
 #define                   nEP7_TX  0x0       
 /* Bit masks for USB_INTRRX */
 #define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
 #define                   nEP1_RX  0x0       
 #define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
 #define                   nEP2_RX  0x0       
 #define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
 #define                   nEP3_RX  0x0       
 #define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
 #define                   nEP4_RX  0x0       
 #define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
 #define                   nEP5_RX  0x0       
 #define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
 #define                   nEP6_RX  0x0       
 #define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
 #define                   nEP7_RX  0x0       
 /* Bit masks for USB_INTRTXE */
 #define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
 #define                 nEP0_TX_E  0x0       
 #define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
 #define                 nEP1_TX_E  0x0       
 #define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
 #define                 nEP2_TX_E  0x0       
 #define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
 #define                 nEP3_TX_E  0x0       
 #define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
 #define                 nEP4_TX_E  0x0       
 #define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
 #define                 nEP5_TX_E  0x0       
 #define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
 #define                 nEP6_TX_E  0x0       
 #define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
 #define                 nEP7_TX_E  0x0       
 /* Bit masks for USB_INTRRXE */
 #define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
 #define                 nEP1_RX_E  0x0       
 #define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
 #define                 nEP2_RX_E  0x0       
 #define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
 #define                 nEP3_RX_E  0x0       
 #define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
 #define                 nEP4_RX_E  0x0       
 #define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
 #define                 nEP5_RX_E  0x0       
 #define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
 #define                 nEP6_RX_E  0x0       
 #define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
 #define                 nEP7_RX_E  0x0       
 /* Bit masks for USB_INTRUSB */
 #define                 SUSPEND_B  0x1        /* Suspend indicator */
 #define                nSUSPEND_B  0x0       
 #define                  RESUME_B  0x2        /* Resume indicator */
 #define                 nRESUME_B  0x0       
 #define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
 #define         nRESET_OR_BABLE_B  0x0       
 #define                     SOF_B  0x8        /* Start of frame */
 #define                    nSOF_B  0x0       
 #define                    CONN_B  0x10       /* Connection indicator */
 #define                   nCONN_B  0x0       
 #define                  DISCON_B  0x20       /* Disconnect indicator */
 #define                 nDISCON_B  0x0       
 #define             SESSION_REQ_B  0x40       /* Session Request */
 #define            nSESSION_REQ_B  0x0       
 #define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
 #define             nVBUS_ERROR_B  0x0       
 /* Bit masks for USB_INTRUSBE */
 #define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
 #define               nSUSPEND_BE  0x0       
 #define                 RESUME_BE  0x2        /* Resume indicator int enable */
 #define                nRESUME_BE  0x0       
 #define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
 #define        nRESET_OR_BABLE_BE  0x0       
 #define                    SOF_BE  0x8        /* Start of frame int enable */
 #define                   nSOF_BE  0x0       
 #define                   CONN_BE  0x10       /* Connection indicator int enable */
 #define                  nCONN_BE  0x0       
 #define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
 #define                nDISCON_BE  0x0       
 #define            SESSION_REQ_BE  0x40       /* Session Request int enable */
 #define           nSESSION_REQ_BE  0x0       
 #define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
 #define            nVBUS_ERROR_BE  0x0       
 /* Bit masks for USB_FRAME */
 #define              FRAME_NUMBER  0x7ff      /* Frame number */
 /* Bit masks for USB_INDEX */
 #define         SELECTED_ENDPOINT  0xf        /* selected endpoint */
 /* Bit masks for USB_GLOBAL_CTL */
 #define                GLOBAL_ENA  0x1        /* enables USB module */
 #define               nGLOBAL_ENA  0x0       
 #define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
 #define               nEP1_TX_ENA  0x0       
 #define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
 #define               nEP2_TX_ENA  0x0       
 #define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
 #define               nEP3_TX_ENA  0x0       
 #define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
 #define               nEP4_TX_ENA  0x0       
 #define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
 #define               nEP5_TX_ENA  0x0       
 #define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
 #define               nEP6_TX_ENA  0x0       
 #define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
 #define               nEP7_TX_ENA  0x0       
 #define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
 #define               nEP1_RX_ENA  0x0       
 #define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
 #define               nEP2_RX_ENA  0x0       
 #define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
 #define               nEP3_RX_ENA  0x0       
 #define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
 #define               nEP4_RX_ENA  0x0       
 #define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
 #define               nEP5_RX_ENA  0x0       
 #define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
 #define               nEP6_RX_ENA  0x0       
 #define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
 #define               nEP7_RX_ENA  0x0       
 /* Bit masks for USB_OTG_DEV_CTL */
 #define                   SESSION  0x1        /* session indicator */
 #define                  nSESSION  0x0       
 #define                  HOST_REQ  0x2        /* Host negotiation request */
 #define                 nHOST_REQ  0x0       
 #define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
 #define                nHOST_MODE  0x0       
 #define                     VBUS0  0x8        /* Vbus level indicator[0] */
 #define                    nVBUS0  0x0       
 #define                     VBUS1  0x10       /* Vbus level indicator[1] */
 #define                    nVBUS1  0x0       
 #define                     LSDEV  0x20       /* Low-speed indicator */
 #define                    nLSDEV  0x0       
 #define                     FSDEV  0x40       /* Full or High-speed indicator */
 #define                    nFSDEV  0x0       
 #define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
 #define                 nB_DEVICE  0x0       
 /* Bit masks for USB_OTG_VBUS_IRQ */
 #define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
 #define            nDRIVE_VBUS_ON  0x0       
 #define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
 #define           nDRIVE_VBUS_OFF  0x0       
 #define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
 #define          nCHRG_VBUS_START  0x0       
 #define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
 #define            nCHRG_VBUS_END  0x0       
 #define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
 #define       nDISCHRG_VBUS_START  0x0       
 #define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
 #define         nDISCHRG_VBUS_END  0x0       
 /* Bit masks for USB_OTG_VBUS_MASK */
 #define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
 #define        nDRIVE_VBUS_ON_ENA  0x0       
 #define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
 #define       nDRIVE_VBUS_OFF_ENA  0x0       
 #define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
 #define      nCHRG_VBUS_START_ENA  0x0       
 #define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
 #define        nCHRG_VBUS_END_ENA  0x0       
 #define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
 #define   nDISCHRG_VBUS_START_ENA  0x0       
 #define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
 #define     nDISCHRG_VBUS_END_ENA  0x0       
 /* Bit masks for USB_CSR0 */
 #define                  RXPKTRDY  0x1        /* data packet receive indicator */
 #define                 nRXPKTRDY  0x0       
 #define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
 #define                 nTXPKTRDY  0x0       
 #define                STALL_SENT  0x4        /* STALL handshake sent */
 #define               nSTALL_SENT  0x0       
 #define                   DATAEND  0x8        /* Data end indicator */
 #define                  nDATAEND  0x0       
 #define                  SETUPEND  0x10       /* Setup end */
 #define                 nSETUPEND  0x0       
 #define                 SENDSTALL  0x20       /* Send STALL handshake */
 #define                nSENDSTALL  0x0       
 #define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
 #define        nSERVICED_RXPKTRDY  0x0       
 #define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
 #define        nSERVICED_SETUPEND  0x0       
 #define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
 #define                nFLUSHFIFO  0x0       
 #define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
 #define         nSTALL_RECEIVED_H  0x0       
 #define                SETUPPKT_H  0x8        /* send Setup token host mode */
 #define               nSETUPPKT_H  0x0       
 #define                   ERROR_H  0x10       /* timeout error indicator host mode */
 #define                  nERROR_H  0x0       
 #define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
 #define                 nREQPKT_H  0x0       
 #define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
 #define              nSTATUSPKT_H  0x0       
 #define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
 #define            nNAK_TIMEOUT_H  0x0       
 /* Bit masks for USB_COUNT0 */
 #define              EP0_RX_COUNT  0x7f       /* number of received bytes in EP0 FIFO */
 /* Bit masks for USB_NAKLIMIT0 */
 #define             EP0_NAK_LIMIT  0x1f       /* number of frames/micro frames after which EP0 timeouts */
 /* Bit masks for USB_TX_MAX_PACKET */
 #define         MAX_PACKET_SIZE_T  0x7ff      /* maximum data pay load in a frame */
 /* Bit masks for USB_RX_MAX_PACKET */
 #define         MAX_PACKET_SIZE_R  0x7ff      /* maximum data pay load in a frame */
 /* Bit masks for USB_TXCSR */
 #define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
 #define               nTXPKTRDY_T  0x0       
 #define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
 #define         nFIFO_NOT_EMPTY_T  0x0       
 #define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
 #define               nUNDERRUN_T  0x0       
 #define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
 #define              nFLUSHFIFO_T  0x0       
 #define              STALL_SEND_T  0x10       /* issue a Stall handshake */
 #define             nSTALL_SEND_T  0x0       
 #define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
 #define             nSTALL_SENT_T  0x0       
 #define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
 #define       nCLEAR_DATATOGGLE_T  0x0       
 #define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
 #define               nINCOMPTX_T  0x0       
 #define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
 #define             nDMAREQMODE_T  0x0       
 #define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
 #define       nFORCE_DATATOGGLE_T  0x0       
 #define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
 #define             nDMAREQ_ENA_T  0x0       
 #define                     ISO_T  0x4000     /* enable Isochronous transfers */
 #define                    nISO_T  0x0       
 #define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
 #define                nAUTOSET_T  0x0       
 #define                  ERROR_TH  0x4        /* error condition host mode */
 #define                 nERROR_TH  0x0       
 #define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
 #define        nSTALL_RECEIVED_TH  0x0       
 #define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
 #define           nNAK_TIMEOUT_TH  0x0       
 /* Bit masks for USB_TXCOUNT */
 #define                  TX_COUNT  0x1fff     /* Number of bytes to be written to the selected endpoint Tx FIFO */
 /* Bit masks for USB_RXCSR */
 #define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
 #define               nRXPKTRDY_R  0x0       
 #define               FIFO_FULL_R  0x2        /* FIFO not empty */
 #define              nFIFO_FULL_R  0x0       
 #define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
 #define                nOVERRUN_R  0x0       
 #define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
 #define              nDATAERROR_R  0x0       
 #define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
 #define              nFLUSHFIFO_R  0x0       
 #define              STALL_SEND_R  0x20       /* issue a Stall handshake */
 #define             nSTALL_SEND_R  0x0       
 #define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
 #define             nSTALL_SENT_R  0x0       
 #define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
 #define       nCLEAR_DATATOGGLE_R  0x0       
 #define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
 #define               nINCOMPRX_R  0x0       
 #define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
 #define             nDMAREQMODE_R  0x0       
 #define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
 #define                nDISNYET_R  0x0       
 #define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
 #define             nDMAREQ_ENA_R  0x0       
 #define                     ISO_R  0x4000     /* enable Isochronous transfers */
 #define                    nISO_R  0x0       
 #define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
 #define              nAUTOCLEAR_R  0x0       
 #define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
 #define                 nERROR_RH  0x0       
 #define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
 #define                nREQPKT_RH  0x0       
 #define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
 #define        nSTALL_RECEIVED_RH  0x0       
 #define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
 #define              nINCOMPRX_RH  0x0       
 #define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
 #define            nDMAREQMODE_RH  0x0       
 #define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
 #define               nAUTOREQ_RH  0x0       
 /* Bit masks for USB_RXCOUNT */
 #define                  RX_COUNT  0x1fff     /* Number of received bytes in the packet in the Rx FIFO */
 /* Bit masks for USB_TXTYPE */
 #define            TARGET_EP_NO_T  0xf        /* EP number */
 #define                PROTOCOL_T  0xc        /* transfer type */
 /* Bit masks for USB_TXINTERVAL */
 #define          TX_POLL_INTERVAL  0xff       /* polling interval for selected Tx EP */
 /* Bit masks for USB_RXTYPE */
 #define            TARGET_EP_NO_R  0xf        /* EP number */
 #define                PROTOCOL_R  0xc        /* transfer type */
 /* Bit masks for USB_RXINTERVAL */
 #define          RX_POLL_INTERVAL  0xff       /* polling interval for selected Rx EP */
 /* Bit masks for USB_DMA_INTERRUPT */
 #define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
 #define                 nDMA0_INT  0x0       
 #define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
 #define                 nDMA1_INT  0x0       
 #define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
 #define                 nDMA2_INT  0x0       
 #define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
 #define                 nDMA3_INT  0x0       
 #define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
 #define                 nDMA4_INT  0x0       
 #define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
 #define                 nDMA5_INT  0x0       
 #define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
 #define                 nDMA6_INT  0x0       
 #define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
 #define                 nDMA7_INT  0x0       
 /* Bit masks for USB_DMAxCONTROL */
 #define                   DMA_ENA  0x1        /* DMA enable */
 #define                  nDMA_ENA  0x0       
 #define                 DIRECTION  0x2        /* direction of DMA transfer */
 #define                nDIRECTION  0x0       
 #define                      MODE  0x4        /* DMA Bus error */
 #define                     nMODE  0x0       
 #define                   INT_ENA  0x8        /* Interrupt enable */
 #define                  nINT_ENA  0x0       
 #define                     EPNUM  0xf0       /* EP number */
 #define                  BUSERROR  0x100      /* DMA Bus error */
 #define                 nBUSERROR  0x0       
 /* Bit masks for USB_DMAxADDRHIGH */
 #define             DMA_ADDR_HIGH  0xffff     /* Upper 16-bits of memory source/destination address for the DMA master channel */
 /* Bit masks for USB_DMAxADDRLOW */
 #define              DMA_ADDR_LOW  0xffff     /* Lower 16-bits of memory source/destination address for the DMA master channel */
 /* Bit masks for USB_DMAxCOUNTHIGH */
 #define            DMA_COUNT_HIGH  0xffff     /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
 /* Bit masks for USB_DMAxCOUNTLOW */
 #define             DMA_COUNT_LOW  0xffff     /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
 #endif /* _DEF_BF527_H */
--- a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
@ -586,58 +586,6 @@
 **				modifier UNLESS the lower order bits are saved and ORed back in when
 **				the macro is used.
 *************************************************************************************/
 /*
 ** ********************* PLL AND RESET MASKS ****************************************/
 /* PLL_CTL Masks																	*/
 #define DF				0x0001	/* 0: PLL = CLKIN, 1: PLL = CLKIN/2					*/
 #define PLL_OFF			0x0002	/* PLL Not Powered									*/
 #define STOPCK			0x0008	/* Core Clock Off									*/
 #define PDWN			0x0020	/* Enter Deep Sleep Mode							*/
 #define	IN_DELAY		0x0040	/* Add 200ps Delay To EBIU Input Latches			*/
 #define	OUT_DELAY		0x0080	/* Add 200ps Delay To EBIU Output Signals			*/
 #define BYPASS			0x0100	/* Bypass the PLL									*/
 #define	MSEL			0x7E00	/* Multiplier Select For CCLK/VCO Factors			*/
 /* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits)			*/
 #define	SET_MSEL(x)		(((x)&0x3F) << 0x9)	/* Set MSEL = 0-63 --> VCO = CLKIN*MSEL		*/
 /* PLL_DIV Masks														*/
 #define SSEL			0x000F	/* System Select						*/
 #define	CSEL			0x0030	/* Core Select							*/
 #define CSEL_DIV1		0x0000	/* 		CCLK = VCO / 1					*/
 #define CSEL_DIV2		0x0010	/* 		CCLK = VCO / 2					*/
 #define	CSEL_DIV4		0x0020	/* 		CCLK = VCO / 4					*/
 #define	CSEL_DIV8		0x0030	/* 		CCLK = VCO / 8					*/
 /* PLL_DIV Macros														*/
 #define SET_SSEL(x)		((x)&0xF)		/* Set SSEL = 0-15 --> SCLK = VCO/SSEL	*/
 /* VR_CTL Masks	*/
 #define	FREQ			0x3000	/* Switching Oscillator Frequency For Regulator	*/
 #define	HIBERNATE		0x0000	/* 		Powerdown/Bypass On-Board Regulation	*/
 #define	VLEV			0x00F0	/* Internal Voltage Level					*/
 #define	VLEV_085 		0x0060	/* 		VLEV = 0.85 V (-5% - +10% Accuracy)	*/
 #define	VLEV_090		0x0070	/* 		VLEV = 0.90 V (-5% - +10% Accuracy)	*/
 #define	VLEV_095		0x0080	/* 		VLEV = 0.95 V (-5% - +10% Accuracy)	*/
 #define	VLEV_100		0x0090	/* 		VLEV = 1.00 V (-5% - +10% Accuracy)	*/
 #define	VLEV_105		0x00A0	/* 		VLEV = 1.05 V (-5% - +10% Accuracy)	*/
 #define	VLEV_110		0x00B0	/* 		VLEV = 1.10 V (-5% - +10% Accuracy)	*/
 #define	VLEV_115		0x00C0	/* 		VLEV = 1.15 V (-5% - +10% Accuracy)	*/
 #define	VLEV_120		0x00D0	/* 		VLEV = 1.20 V (-5% - +10% Accuracy)	*/
 #define	VLEV_125		0x00E0	/* 		VLEV = 1.25 V (-5% - +10% Accuracy)	*/
 #define	VLEV_130		0x00F0	/* 		VLEV = 1.30 V (-5% - +10% Accuracy)	*/
 #define	WAKE			0x0100	/* Enable RTC/Reset Wakeup From Hibernate	*/
 #define	USBWE			0x0200	/* Enable USB Wakeup From Hibernate			*/
 #define	PHYWE			0x0400	/* Enable PHY Wakeup From Hibernate			*/
 #define	CLKBUFOE		0x4000	/* CLKIN Buffer Output Enable */
 #define	PHYCLKOE		CLKBUFOE	/* Alternative legacy name for the above */
 #define	SCKELOW		0x8000	/* Enable Drive CKE Low During Reset		*/
 /* PLL_STAT Masks																	*/
 #define ACTIVE_PLLENABLED	0x0001	/* Processor In Active Mode With PLL Enabled	*/
 #define	FULL_ON				0x0002	/* Processor In Full On Mode					*/
 #define ACTIVE_PLLDISABLED	0x0004	/* Processor In Active Mode With PLL Disabled	*/
 #define	PLL_LOCKED			0x0020	/* PLL_LOCKCNT Has Been Reached					*/
 /* CHIPID Masks */
 #define CHIPID_VERSION         0xF0000000
@ -757,66 +705,6 @@
 #define IWR_DISABLE(x)	(0xFFFFFFFF ^ (1 << ((x)&0x1F))) 	/* Wakeup Disable Peripheral #x		*/
 /* ********* WATCHDOG TIMER MASKS ******************** */
 /* Watchdog Timer WDOG_CTL Register Masks */
 #define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
 #define WDEV_RESET 0x0000 /* generate reset event on roll over */
 #define WDEV_NMI 0x0002 /* generate NMI event on roll over */
 #define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
 #define WDEV_NONE 0x0006 /* no event on roll over */
 #define WDEN 0x0FF0 /* enable watchdog */
 #define WDDIS 0x0AD0 /* disable watchdog */
 #define WDRO 0x8000 /* watchdog rolled over latch */
 /* depreciated WDOG_CTL Register Masks for legacy code */
 #define ICTL WDEV
 #define ENABLE_RESET WDEV_RESET
 #define WDOG_RESET WDEV_RESET
 #define ENABLE_NMI WDEV_NMI
 #define WDOG_NMI WDEV_NMI
 #define ENABLE_GPI WDEV_GPI
 #define WDOG_GPI WDEV_GPI
 #define DISABLE_EVT WDEV_NONE
 #define WDOG_NONE WDEV_NONE
 #define TMR_EN WDEN
 #define TMR_DIS WDDIS
 #define TRO WDRO
 #define ICTL_P0 0x01
 #define ICTL_P1 0x02
 #define TRO_P 0x0F
 /* ***************  REAL TIME CLOCK MASKS  **************************/
 /* RTC_STAT and RTC_ALARM Masks										*/
 #define	RTC_SEC				0x0000003F	/* Real-Time Clock Seconds	*/
 #define	RTC_MIN				0x00000FC0	/* Real-Time Clock Minutes	*/
 #define	RTC_HR				0x0001F000	/* Real-Time Clock Hours	*/
 #define	RTC_DAY				0xFFFE0000	/* Real-Time Clock Days		*/
 /* RTC_ALARM Macro			z=day		y=hr	x=min	w=sec		*/
 #define SET_ALARM(z,y,x,w)	((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
 /* RTC_ICTL and RTC_ISTAT Masks																		*/
 #define	STOPWATCH			0x0001		/* Stopwatch Interrupt Enable								*/
 #define	ALARM				0x0002		/* Alarm Interrupt Enable									*/
 #define	SECOND				0x0004		/* Seconds (1 Hz) Interrupt Enable							*/
 #define	MINUTE				0x0008		/* Minutes Interrupt Enable									*/
 #define	HOUR				0x0010		/* Hours Interrupt Enable									*/
 #define	DAY					0x0020		/* 24 Hours (Days) Interrupt Enable							*/
 #define	DAY_ALARM			0x0040		/* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable	*/
 #define	WRITE_PENDING		0x4000		/* Write Pending Status										*/
 #define	WRITE_COMPLETE		0x8000		/* Write Complete Interrupt Enable							*/
 /* RTC_FAST / RTC_PREN Mask												*/
 #define PREN				0x0001	/* Enable Prescaler, RTC Runs @1 Hz	*/
 /* ************** UART CONTROLLER MASKS *************************/
 /* UARTx_LCR Masks												*/
 #define WLS(x)		(((x)-5) & 0x03)	/* Word Length Select */
@ -1381,33 +1269,6 @@
 /* **************************  DMA CONTROLLER MASKS  ********************************/
 /* DMAx_CONFIG, MDMA_yy_CONFIG Masks												*/
 #define DMAEN			0x0001		/* DMA Channel Enable							*/
 #define WNR				0x0002		/* Channel Direction (W/R*)						*/
 #define WDSIZE_8		0x0000		/* Transfer Word Size = 8						*/
 #define WDSIZE_16		0x0004		/* Transfer Word Size = 16						*/
 #define WDSIZE_32		0x0008		/* Transfer Word Size = 32						*/
 #define DMA2D			0x0010		/* DMA Mode (2D/1D*)							*/
 #define RESTART			0x0020		/* DMA Buffer Clear								*/
 #define DI_SEL			0x0040		/* Data Interrupt Timing Select					*/
 #define DI_EN			0x0080		/* Data Interrupt Enable						*/
 #define NDSIZE_0		0x0000		/* Next Descriptor Size = 0 (Stop/Autobuffer)	*/
 #define NDSIZE_1		0x0100		/* Next Descriptor Size = 1						*/
 #define NDSIZE_2		0x0200		/* Next Descriptor Size = 2						*/
 #define NDSIZE_3		0x0300		/* Next Descriptor Size = 3						*/
 #define NDSIZE_4		0x0400		/* Next Descriptor Size = 4						*/
 #define NDSIZE_5		0x0500		/* Next Descriptor Size = 5						*/
 #define NDSIZE_6		0x0600		/* Next Descriptor Size = 6						*/
 #define NDSIZE_7		0x0700		/* Next Descriptor Size = 7						*/
 #define NDSIZE_8		0x0800		/* Next Descriptor Size = 8						*/
 #define NDSIZE_9		0x0900		/* Next Descriptor Size = 9						*/
 #define NDSIZE	        	0x0900	/* Next Descriptor Size */
 #define DMAFLOW	        	0x7000	/* Flow Control */
 #define DMAFLOW_STOP		0x0000		/* Stop Mode									*/
 #define DMAFLOW_AUTO		0x1000		/* Autobuffer Mode								*/
 #define DMAFLOW_ARRAY		0x4000		/* Descriptor Array Mode						*/
 #define DMAFLOW_SMALL		0x6000		/* Small Model Descriptor List Mode				*/
 #define DMAFLOW_LARGE		0x7000		/* Large Model Descriptor List Mode				*/
 /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks								*/
 #define CTYPE			0x0040	/* DMA Channel Type Indicator (Memory/Peripheral*)	*/
@ -1425,13 +1286,6 @@
 #define	PMAP_UART1RX	0xA000	/* 		UART1 Port Receive DMA						*/
 #define	PMAP_UART1TX	0xB000	/* 		UART1 Port Transmit DMA						*/
 /* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks						*/
 #define DMA_DONE		0x0001	/* DMA Completion Interrupt Status	*/
 #define DMA_ERR			0x0002	/* DMA Error Interrupt Status		*/
 #define DFETCH			0x0004	/* DMA Descriptor Fetch Indicator	*/
 #define DMA_RUN			0x0008	/* DMA Channel Running Indicator	*/
 /*  ************  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
 /*  PPI_CONTROL Masks													*/
 #define PORT_EN			0x0001		/* PPI Port Enable					*/
@ -1843,46 +1697,6 @@
 #define BNDMODE_CAPT     0x2000  /* boundary capture mode */
 #define BNDMODE_AEXT     0x3000  /* boundary auto-extend mode */
 /* Bit masks for OTP_CONTROL */
 #define                FUSE_FADDR  0x1ff      /* OTP/Fuse Address */
 #define                      FIEN  0x800      /* OTP/Fuse Interrupt Enable */
 #define                     nFIEN  0x0
 #define                  FTESTDEC  0x1000     /* OTP/Fuse Test Decoder */
 #define                 nFTESTDEC  0x0
 #define                   FWRTEST  0x2000     /* OTP/Fuse Write Test */
 #define                  nFWRTEST  0x0
 #define                     FRDEN  0x4000     /* OTP/Fuse Read Enable */
 #define                    nFRDEN  0x0
 #define                     FWREN  0x8000     /* OTP/Fuse Write Enable */
 #define                    nFWREN  0x0
 /* Bit masks for OTP_BEN */
 #define                      FBEN  0xffff     /* OTP/Fuse Byte Enable */
 /* Bit masks for OTP_STATUS */
 #define                     FCOMP  0x1        /* OTP/Fuse Access Complete */
 #define                    nFCOMP  0x0
 #define                    FERROR  0x2        /* OTP/Fuse Access Error */
 #define                   nFERROR  0x0
 #define                  MMRGLOAD  0x10       /* Memory Mapped Register Gasket Load */
 #define                 nMMRGLOAD  0x0
 #define                  MMRGLOCK  0x20       /* Memory Mapped Register Gasket Lock */
 #define                 nMMRGLOCK  0x0
 #define                    FPGMEN  0x40       /* OTP/Fuse Program Enable */
 #define                   nFPGMEN  0x0
 /* Bit masks for OTP_TIMING */
 #define                   USECDIV  0xff       /* Micro Second Divider */
 #define                   READACC  0x7f00     /* Read Access Time */
 #define                   CPUMPRL  0x38000    /* Charge Pump Release Time */
 #define                   CPUMPSU  0xc0000    /* Charge Pump Setup Time */
 #define                   CPUMPHD  0xf00000   /* Charge Pump Hold Time */
 #define                   PGMTIME  0xff000000 /* Program Time */
 /* Bit masks for SECURE_SYSSWT */
 #define                   EMUDABL  0x1        /* Emulation Disable. */
--- a/arch/blackfin/mach-bf533/boards/H8606.c
+++ b/arch/blackfin/mach-bf533/boards/H8606.c
@ -166,7 +166,6 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
 #if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
 /* SPI ADC chip */
 static struct bfin5xx_spi_chip spi_adc_chip_info = {
 	.ctl_reg = 0x1000,
 	.enable_dma = 1,         /* use dma transfer with this chip*/
 	.bits_per_word = 16,
 };
@ -174,7 +173,6 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
 #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
 static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
 	.ctl_reg = 0x1000,
 	.enable_dma = 0,
 	.bits_per_word = 16,
 };
@ -258,12 +256,6 @@ static struct platform_device bfin_spi0_device = {
 };
 #endif  /* spi master and devices */
 #if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
 static struct platform_device bfin_fb_device = {
 	.name = "bf537-fb",
 };
 #endif
 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
 static struct resource bfin_uart_resources[] = {
 	{
--- a/arch/blackfin/mach-bf533/boards/ip0x.c
+++ b/arch/blackfin/mach-bf533/boards/ip0x.c
@ -20,6 +20,7 @@
 #endif
 #include <asm/irq.h>
 #include <asm/bfin5xx_spi.h>
 #include <asm/portmux.h>
 /*
 * Name the Board for the /proc/cpuinfo
@ -107,20 +108,6 @@ static struct platform_device dm9000_device2 = {
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
 /*
 * CPOL (Clock Polarity)
 *  0 - Active high SCK
 *  1 - Active low SCK
 *  CPHA (Clock Phase) Selects transfer format and operation mode
 *  0 - SCLK toggles from middle of the first data bit, slave select
 *      pins controlled by hardware.
 *  1 - SCLK toggles from beginning of first data bit, slave select
 *      pins controller by user software.
 * 	.ctl_reg = 0x1c00,		 *  CPOL=1,CPHA=1,Sandisk 1G work
 * NO NO	.ctl_reg = 0x1800,		 *  CPOL=1,CPHA=0
 * NO NO	.ctl_reg = 0x1400,		 *  CPOL=0,CPHA=1
 */
 	.ctl_reg = 0x1000,		/* CPOL=0,CPHA=0,Sandisk 1G work */
 	.enable_dma = 0,		/* if 1 - block!!! */
 	.bits_per_word = 8,
 };
--- a/arch/blackfin/mach-bf533/boards/stamp.c
+++ b/arch/blackfin/mach-bf533/boards/stamp.c
@ -321,12 +321,6 @@ static struct platform_device bfin_spi0_device = {
 };
 #endif  /* spi master and devices */
 #if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
 static struct platform_device bfin_fb_device = {
 	.name = "bf537-fb",
 };
 #endif
 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
 static struct resource bfin_uart_resources[] = {
 	{
--- a/arch/blackfin/mach-bf533/include/mach/defBF532.h
+++ b/arch/blackfin/mach-bf533/include/mach/defBF532.h
@ -370,72 +370,6 @@
 /* System MMR Register Bits */
 /******************************************************************************* */
 /* ********************* PLL AND RESET MASKS ************************ */
 /* PLL_CTL Masks */
 #define PLL_CLKIN			0x0000  /* Pass CLKIN to PLL */
 #define PLL_CLKIN_DIV2			0x0001  /* Pass CLKIN/2 to PLL */
 #define DF				0x0001	/* 0: PLL = CLKIN, 1: PLL = CLKIN/2					*/
 #define PLL_OFF				0x0002  /* Shut off PLL clocks */
 #define STOPCK_OFF			0x0008  /* Core clock off */
 #define STOPCK				0x0008	/* Core Clock Off									*/
 #define PDWN				0x0020  /* Put the PLL in a Deep Sleep state */
 #if !defined(__ADSPBF538__)
 /* this file is included in defBF538.h but IN_DELAY/OUT_DELAY are different */
 # define IN_DELAY        0x0040  /* Add 200ps Delay To EBIU Input Latches */
 # define OUT_DELAY       0x0080  /* Add 200ps Delay To EBIU Output Signals */
 #endif
 #define BYPASS				0x0100  /* Bypass the PLL */
 /* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits)			*/
 #define	SET_MSEL(x)		(((x)&0x3F) << 0x9)	/* Set MSEL = 0-63 --> VCO = CLKIN*MSEL		*/
 /* PLL_DIV Masks */
 #define SSEL				0x000F	/* System Select						*/
 #define	CSEL				0x0030	/* Core Select							*/
 #define SCLK_DIV(x)  (x)	/* SCLK = VCO / x */
 #define CCLK_DIV1              0x00000000	/* CCLK = VCO / 1 */
 #define CCLK_DIV2              0x00000010	/* CCLK = VCO / 2 */
 #define CCLK_DIV4              0x00000020	/* CCLK = VCO / 4 */
 #define CCLK_DIV8              0x00000030	/* CCLK = VCO / 8 */
 /* PLL_DIV Macros														*/
 #define SET_SSEL(x)			((x)&0xF)	/* Set SSEL = 0-15 --> SCLK = VCO/SSEL	*/
 /* PLL_STAT Masks																	*/
 #define ACTIVE_PLLENABLED	0x0001	/* Processor In Active Mode With PLL Enabled    */
 #define	FULL_ON				0x0002	/* Processor In Full On Mode                                    */
 #define ACTIVE_PLLDISABLED	0x0004	/* Processor In Active Mode With PLL Disabled   */
 #define	PLL_LOCKED			0x0020	/* PLL_LOCKCNT Has Been Reached                                 */
 /* VR_CTL Masks																	*/
 #define	FREQ			0x0003	/* Switching Oscillator Frequency For Regulator	*/
 #define	HIBERNATE		0x0000	/* 		Powerdown/Bypass On-Board Regulation	*/
 #define	FREQ_333		0x0001	/* 		Switching Frequency Is 333 kHz			*/
 #define	FREQ_667		0x0002	/* 		Switching Frequency Is 667 kHz			*/
 #define	FREQ_1000		0x0003	/* 		Switching Frequency Is 1 MHz			*/
 #define GAIN			0x000C	/* Voltage Level Gain	*/
 #define	GAIN_5			0x0000	/* 		GAIN = 5		*/
 #define	GAIN_10			0x0004	/* 		GAIN = 10		*/
 #define	GAIN_20			0x0008	/* 		GAIN = 20		*/
 #define	GAIN_50			0x000C	/* 		GAIN = 50		*/
 #define	VLEV			0x00F0	/* Internal Voltage Level					*/
 #define	VLEV_085 		0x0060	/* 		VLEV = 0.85 V (-5% - +10% Accuracy)	*/
 #define	VLEV_090		0x0070	/* 		VLEV = 0.90 V (-5% - +10% Accuracy)	*/
 #define	VLEV_095		0x0080	/* 		VLEV = 0.95 V (-5% - +10% Accuracy)	*/
 #define	VLEV_100		0x0090	/* 		VLEV = 1.00 V (-5% - +10% Accuracy)	*/
 #define	VLEV_105		0x00A0	/* 		VLEV = 1.05 V (-5% - +10% Accuracy)	*/
 #define	VLEV_110		0x00B0	/* 		VLEV = 1.10 V (-5% - +10% Accuracy)	*/
 #define	VLEV_115		0x00C0	/* 		VLEV = 1.15 V (-5% - +10% Accuracy)	*/
 #define	VLEV_120		0x00D0	/* 		VLEV = 1.20 V (-5% - +10% Accuracy)	*/
 #define	VLEV_125		0x00E0	/*              VLEV = 1.25 V (-5% - +10% Accuracy)     */
 #define	VLEV_130		0x00F0	/*              VLEV = 1.30 V (-5% - +10% Accuracy)     */
 #define	WAKE			0x0100	/* Enable RTC/Reset Wakeup From Hibernate	*/
 #define	SCKELOW			0x8000	/* Do Not Drive SCKE High During Reset After Hibernate */
 /* CHIPID Masks */
 #define CHIPID_VERSION         0xF0000000
 #define CHIPID_FAMILY          0x0FFFF000
@ -703,54 +637,7 @@
 /* **********  DMA CONTROLLER MASKS  *********************8 */
-/*DMAx_CONFIG, MDMA_yy_CONFIG Masks */
+/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
 #define DMAEN	        0x00000001	/* Channel Enable */
 #define WNR	   	0x00000002	/* Channel Direction (W/R*) */
 #define WDSIZE_8	0x00000000	/* Word Size 8 bits */
 #define WDSIZE_16	0x00000004	/* Word Size 16 bits */
 #define WDSIZE_32	0x00000008	/* Word Size 32 bits */
 #define DMA2D	        0x00000010	/* 2D/1D* Mode */
 #define RESTART         0x00000020	/* Restart */
 #define DI_SEL	        0x00000040	/* Data Interrupt Select */
 #define DI_EN	        0x00000080	/* Data Interrupt Enable */
 #define NDSIZE_0		0x0000	/* Next Descriptor Size = 0 (Stop/Autobuffer)   */
 #define NDSIZE_1		0x0100	/* Next Descriptor Size = 1                                             */
 #define NDSIZE_2		0x0200	/* Next Descriptor Size = 2                                             */
 #define NDSIZE_3		0x0300	/* Next Descriptor Size = 3                                             */
 #define NDSIZE_4		0x0400	/* Next Descriptor Size = 4                                             */
 #define NDSIZE_5		0x0500	/* Next Descriptor Size = 5                                             */
 #define NDSIZE_6		0x0600	/* Next Descriptor Size = 6                                             */
 #define NDSIZE_7		0x0700	/* Next Descriptor Size = 7                                             */
 #define NDSIZE_8		0x0800	/* Next Descriptor Size = 8                                             */
 #define NDSIZE_9		0x0900	/* Next Descriptor Size = 9                                             */
 #define NDSIZE	        0x00000900	/* Next Descriptor Size */
 #define DMAFLOW	        0x00007000	/* Flow Control */
 #define DMAFLOW_STOP		0x0000	/* Stop Mode */
 #define DMAFLOW_AUTO		0x1000	/* Autobuffer Mode */
 #define DMAFLOW_ARRAY		0x4000	/* Descriptor Array Mode */
 #define DMAFLOW_SMALL		0x6000	/* Small Model Descriptor List Mode */
 #define DMAFLOW_LARGE		0x7000	/* Large Model Descriptor List Mode */
 #define DMAEN_P	            	0	/* Channel Enable */
 #define WNR_P	            	1	/* Channel Direction (W/R*) */
 #define DMA2D_P	        	4	/* 2D/1D* Mode */
 #define RESTART_P	      	5	/* Restart */
 #define DI_SEL_P	     	6	/* Data Interrupt Select */
 #define DI_EN_P	            	7	/* Data Interrupt Enable */
 /*DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
 #define DMA_DONE		0x00000001	/* DMA Done Indicator */
 #define DMA_ERR	        	0x00000002	/* DMA Error Indicator */
 #define DFETCH	            	0x00000004	/* Descriptor Fetch Indicator */
 #define DMA_RUN	            	0x00000008	/* DMA Running Indicator */
 #define DMA_DONE_P	    	0	/* DMA Done Indicator */
 #define DMA_ERR_P     		1	/* DMA Error Indicator */
 #define DFETCH_P     		2	/* Descriptor Fetch Indicator */
 #define DMA_RUN_P     		3	/* DMA Running Indicator */
 /*DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
 #define CTYPE	            0x00000040	/* DMA Channel Type Indicator */
 #define CTYPE_P             6	/* DMA Channel Type Indicator BIT POSITION */
--- a/arch/blackfin/mach-bf537/boards/pnav10.c
+++ b/arch/blackfin/mach-bf537/boards/pnav10.c
@ -13,9 +13,6 @@
 #include <linux/mtd/partitions.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
 #include <linux/usb/isp1362.h>
 #endif
 #include <linux/irq.h>
 #include <asm/dma.h>
 #include <asm/bfin5xx_spi.h>
@ -147,45 +144,6 @@ static struct platform_device sl811_hcd_device = {
 };
 #endif
 #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
 static struct resource isp1362_hcd_resources[] = {
 	{
 		.start = 0x20360000,
 		.end = 0x20360000,
 		.flags = IORESOURCE_MEM,
 	}, {
 		.start = 0x20360004,
 		.end = 0x20360004,
 		.flags = IORESOURCE_MEM,
 	}, {
 		.start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
 		.end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
 		.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
 	},
 };
 static struct isp1362_platform_data isp1362_priv = {
 	.sel15Kres = 1,
 	.clknotstop = 0,
 	.oc_enable = 0,
 	.int_act_high = 0,
 	.int_edge_triggered = 0,
 	.remote_wakeup_connected = 0,
 	.no_power_switching = 1,
 	.power_switching_mode = 0,
 };
 static struct platform_device isp1362_hcd_device = {
 	.name = "isp1362-hcd",
 	.id = 0,
 	.dev = {
 		.platform_data = &isp1362_priv,
 	},
 	.num_resources = ARRAY_SIZE(isp1362_hcd_resources),
 	.resource = isp1362_hcd_resources,
 };
 #endif
 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
 static struct platform_device bfin_mii_bus = {
 	.name = "bfin_mii_bus",
@ -492,10 +450,6 @@ static struct platform_device *stamp_devices[] __initdata = {
 	&sl811_hcd_device,
 #endif
 #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
 	&isp1362_hcd_device,
 #endif
 #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
 	&smc91x_device,
 #endif
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@ -9,6 +9,7 @@
 #include <linux/device.h>
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
@ -25,6 +26,8 @@
 #include <linux/i2c.h>
 #include <linux/usb/sl811.h>
 #include <linux/spi/mmc_spi.h>
 #include <linux/leds.h>
 #include <linux/input.h>
 #include <asm/dma.h>
 #include <asm/bfin5xx_spi.h>
 #include <asm/reboot.h>
@ -65,7 +68,7 @@ static struct isp1760_platform_data isp1760_priv = {
 };
 static struct platform_device bfin_isp1760_device = {
-	.name           = "isp1760-hcd",
+	.name           = "isp1760",
 	.id             = 0,
 	.dev = {
 		.platform_data = &isp1760_priv,
@ -76,7 +79,6 @@ static struct platform_device bfin_isp1760_device = {
 #endif
 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
 static struct gpio_keys_button bfin_gpio_keys_table[] = {
@ -195,28 +197,6 @@ static struct platform_device dm9000_device = {
 };
 #endif
 #if defined(CONFIG_AX88180) || defined(CONFIG_AX88180_MODULE)
 static struct resource ax88180_resources[] = {
 	[0] = {
 		.start	= 0x20300000,
 		.end	= 0x20300000 + 0x8000,
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
 		.start	= IRQ_PF7,
 		.end	= IRQ_PF7,
 		.flags	= (IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL),
 	},
 };
 static struct platform_device ax88180_device = {
 	.name		= "ax88180",
 	.id		= -1,
 	.num_resources	= ARRAY_SIZE(ax88180_resources),
 	.resource	= ax88180_resources,
 };
 #endif
 #if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
 static struct resource sl811_hcd_resources[] = {
 	{
@ -272,8 +252,8 @@ static struct resource isp1362_hcd_resources[] = {
 		.end = 0x20360004,
 		.flags = IORESOURCE_MEM,
 	}, {
-		.start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
+		.start = IRQ_PF3,
-		.end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
+		.end = IRQ_PF3,
 		.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
 	},
 };
@ -300,6 +280,44 @@ static struct platform_device isp1362_hcd_device = {
 };
 #endif
 #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
 unsigned short bfin_can_peripherals[] = {
 	P_CAN0_RX, P_CAN0_TX, 0
 };
 static struct resource bfin_can_resources[] = {
 	{
 		.start = 0xFFC02A00,
 		.end = 0xFFC02FFF,
 		.flags = IORESOURCE_MEM,
 	},
 	{
 		.start = IRQ_CAN_RX,
 		.end = IRQ_CAN_RX,
 		.flags = IORESOURCE_IRQ,
 	},
 	{
 		.start = IRQ_CAN_TX,
 		.end = IRQ_CAN_TX,
 		.flags = IORESOURCE_IRQ,
 	},
 	{
 		.start = IRQ_CAN_ERROR,
 		.end = IRQ_CAN_ERROR,
 		.flags = IORESOURCE_IRQ,
 	},
 };
 static struct platform_device bfin_can_device = {
 	.name = "bfin_can",
 	.num_resources = ARRAY_SIZE(bfin_can_resources),
 	.resource = bfin_can_resources,
 	.dev = {
 		.platform_data = &bfin_can_peripherals, /* Passed to driver */
 	},
 };
 #endif
 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
 static struct platform_device bfin_mii_bus = {
 	.name = "bfin_mii_bus",
@ -514,15 +532,14 @@ static struct bfin5xx_spi_chip ad1938_spi_chip_info = {
 };
 #endif
-#if defined(CONFIG_INPUT_EVAL_AD7147EBZ)
+#if defined(CONFIG_INPUT_AD714X_SPI) || defined(CONFIG_INPUT_AD714X_SPI_MODULE)
 #include <linux/input.h>
 #include <linux/input/ad714x.h>
 static struct bfin5xx_spi_chip ad7147_spi_chip_info = {
 	.enable_dma = 0,
 	.bits_per_word = 16,
 };
-static struct ad714x_slider_plat slider_plat[] = {
+static struct ad714x_slider_plat ad7147_spi_slider_plat[] = {
 	{
 		.start_stage = 0,
 		.end_stage = 7,
@ -530,7 +547,7 @@ static struct ad714x_slider_plat slider_plat[] = {
 	},
 };
-static struct ad714x_button_plat button_plat[] = {
+static struct ad714x_button_plat ad7147_spi_button_plat[] = {
 	{
 		.keycode = BTN_FORWARD,
 		.l_mask = 0,
@ -557,11 +574,11 @@ static struct ad714x_button_plat button_plat[] = {
 		.h_mask = 0x400,
 	},
 };
-static struct ad714x_platform_data ad7147_platfrom_data = {
+static struct ad714x_platform_data ad7147_spi_platform_data = {
 	.slider_num = 1,
 	.button_num = 5,
-	.slider = slider_plat,
+	.slider = ad7147_spi_slider_plat,
-	.button = button_plat,
+	.button = ad7147_spi_button_plat,
 	.stage_cfg_reg =  {
 		{0xFBFF, 0x1FFF, 0, 0x2626, 1600, 1600, 1600, 1600},
 		{0xEFFF, 0x1FFF, 0, 0x2626, 1650, 1650, 1650, 1650},
@ -580,10 +597,9 @@ static struct ad714x_platform_data ad7147_platfrom_data = {
 };
 #endif
-#if defined(CONFIG_INPUT_EVAL_AD7142EB)
+#if defined(CONFIG_INPUT_AD714X_I2C) || defined(CONFIG_INPUT_AD714X_I2C_MODULE)
 #include <linux/input.h>
 #include <linux/input/ad714x.h>
-static struct ad714x_button_plat button_plat[] = {
+static struct ad714x_button_plat ad7142_i2c_button_plat[] = {
 	{
 		.keycode = BTN_1,
 		.l_mask = 0,
@ -605,9 +621,9 @@ static struct ad714x_button_plat button_plat[] = {
 		.h_mask = 0x8,
 	},
 };
-static struct ad714x_platform_data ad7142_platfrom_data = {
+static struct ad714x_platform_data ad7142_i2c_platform_data = {
 	.button_num = 4,
-	.button = button_plat,
+	.button = ad7142_i2c_button_plat,
 	.stage_cfg_reg =  {
 		/* fixme: figure out right setting for all comoponent according
 		 * to hardware feature of EVAL-AD7142EB board */
@ -696,8 +712,7 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
 #endif
 #if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
-#include <linux/input.h>
+#include <linux/input/adxl34x.h>
 #include <linux/spi/adxl34x.h>
 static const struct adxl34x_platform_data adxl34x_info = {
 	.x_axis_offset = 0,
 	.y_axis_offset = 0,
@ -721,9 +736,7 @@ static const struct adxl34x_platform_data adxl34x_info = {
 	.ev_code_y = ABS_Y,		/* EV_REL */
 	.ev_code_z = ABS_Z,		/* EV_REL */
-	.ev_code_tap_x = BTN_TOUCH,		/* EV_KEY */
+	.ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
 	.ev_code_tap_y = BTN_TOUCH,		/* EV_KEY */
 	.ev_code_tap_z = BTN_TOUCH,		/* EV_KEY */
 /*	.ev_code_ff = KEY_F,*/		/* EV_KEY */
 /*	.ev_code_act_inactivity = KEY_A,*/	/* EV_KEY */
@ -761,6 +774,47 @@ static struct bfin5xx_spi_chip enc28j60_spi_chip_info = {
 };
 #endif
 #if defined(CONFIG_ADF702X) || defined(CONFIG_ADF702X_MODULE)
 static struct bfin5xx_spi_chip adf7021_spi_chip_info = {
 	.bits_per_word = 16,
 	.cs_gpio = GPIO_PF10,
 };
 #include <linux/spi/adf702x.h>
 #define TXREG 0x0160A470
 static const u32 adf7021_regs[] = {
 	0x09608FA0,
 	0x00575011,
 	0x00A7F092,
 	0x2B141563,
 	0x81F29E94,
 	0x00003155,
 	0x050A4F66,
 	0x00000007,
 	0x00000008,
 	0x000231E9,
 	0x3296354A,
 	0x891A2B3B,
 	0x00000D9C,
 	0x0000000D,
 	0x0000000E,
 	0x0000000F,
 };
 static struct adf702x_platform_data adf7021_platform_data = {
 	.regs_base = (void *)SPORT1_TCR1,
 	.dma_ch_rx = CH_SPORT1_RX,
 	.dma_ch_tx = CH_SPORT1_TX,
 	.irq_sport_err = IRQ_SPORT1_ERROR,
 	.gpio_int_rfs = GPIO_PF8,
 	.pin_req = {P_SPORT1_DTPRI, P_SPORT1_RFS, P_SPORT1_DRPRI,
 			P_SPORT1_RSCLK, P_SPORT1_TSCLK, 0},
 	.adf702x_model = MODEL_ADF7021,
 	.adf702x_regs = adf7021_regs,
 	.tx_reg = TXREG,
 };
 #endif
 #if defined(CONFIG_MTD_DATAFLASH) \
 	|| defined(CONFIG_MTD_DATAFLASH_MODULE)
@ -794,6 +848,13 @@ static struct bfin5xx_spi_chip data_flash_chip_info = {
 };
 #endif
 #if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
 static struct bfin5xx_spi_chip spi_adxl34x_chip_info = {
 	.enable_dma = 0,         /* use dma transfer with this chip*/
 	.bits_per_word = 8,
 };
 #endif
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #if defined(CONFIG_MTD_M25P80) \
 	|| defined(CONFIG_MTD_M25P80_MODULE)
@ -855,7 +916,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 	},
 #endif
-#if defined(CONFIG_INPUT_EVAL_AD7147EBZ)
+#if defined(CONFIG_INPUT_AD714X_SPI) || defined(CONFIG_INPUT_AD714X_SPI_MODULE)
 	{
 		.modalias = "ad714x_captouch",
 		.max_speed_hz = 1000000,     /* max spi clock (SCK) speed in HZ */
@ -863,7 +924,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 		.bus_num = 0,
 		.chip_select = 5,
 		.mode = SPI_MODE_3,
-		.platform_data = &ad7147_platfrom_data,
+		.platform_data = &ad7147_spi_platform_data,
 		.controller_data = &ad7147_spi_chip_info,
 	},
 #endif
@ -932,6 +993,30 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 		.mode = SPI_MODE_0,
 	},
 #endif
 #if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
 	{
 		.modalias	= "adxl34x",
 		.platform_data	= &adxl34x_info,
 		.irq		= IRQ_PF6,
 		.max_speed_hz	= 5000000,    /* max spi clock (SCK) speed in HZ */
 		.bus_num	= 0,
 		.chip_select	= 2,
 		.controller_data = &spi_adxl34x_chip_info,
 		.mode = SPI_MODE_3,
 	},
 #endif
 #if defined(CONFIG_ADF702X) || defined(CONFIG_ADF702X_MODULE)
 	{
 		.modalias = "adf702x",
 		.max_speed_hz = 16000000,     /* max spi clock (SCK) speed in HZ */
 		.bus_num = 0,
 		.chip_select = 0,	/* GPIO controlled SSEL */
 		.controller_data = &adf7021_spi_chip_info,
 		.platform_data = &adf7021_platform_data,
 		.mode = SPI_MODE_0,
 	},
 #endif
 };
 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
@ -1175,7 +1260,6 @@ static struct platform_device i2c_bfin_twi_device = {
 #endif
 #if defined(CONFIG_KEYBOARD_ADP5588) || defined(CONFIG_KEYBOARD_ADP5588_MODULE)
 #include <linux/input.h>
 #include <linux/i2c/adp5588.h>
 static const unsigned short adp5588_keymap[ADP5588_KEYMAPSIZE] = {
 	[0]	 = KEY_GRAVE,
@ -1268,35 +1352,33 @@ static struct adp5588_kpad_platform_data adp5588_kpad_data = {
 	 *  ADP5520/5501 Backlight Data
 	 */
-static struct adp5520_backlight_platfrom_data adp5520_backlight_data = {
+static struct adp5520_backlight_platform_data adp5520_backlight_data = {
-	.fade_in 		= FADE_T_1200ms,
+	.fade_in		= ADP5520_FADE_T_1200ms,
-	.fade_out 		= FADE_T_1200ms,
+	.fade_out		= ADP5520_FADE_T_1200ms,
-	.fade_led_law 		= BL_LAW_LINEAR,
+	.fade_led_law		= ADP5520_BL_LAW_LINEAR,
-	.en_ambl_sens 		= 1,
+	.en_ambl_sens		= 1,
-	.abml_filt 		= BL_AMBL_FILT_640ms,
+	.abml_filt		= ADP5520_BL_AMBL_FILT_640ms,
-	.l1_daylight_max 	= BL_CUR_mA(15),
+	.l1_daylight_max	= ADP5520_BL_CUR_mA(15),
-	.l1_daylight_dim 	= BL_CUR_mA(0),
+	.l1_daylight_dim	= ADP5520_BL_CUR_mA(0),
-	.l2_office_max 		= BL_CUR_mA(7),
+	.l2_office_max		= ADP5520_BL_CUR_mA(7),
-	.l2_office_dim 		= BL_CUR_mA(0),
+	.l2_office_dim		= ADP5520_BL_CUR_mA(0),
-	.l3_dark_max 		= BL_CUR_mA(3),
+	.l3_dark_max		= ADP5520_BL_CUR_mA(3),
-	.l3_dark_dim 		= BL_CUR_mA(0),
+	.l3_dark_dim		= ADP5520_BL_CUR_mA(0),
-	.l2_trip 		= L2_COMP_CURR_uA(700),
+	.l2_trip		= ADP5520_L2_COMP_CURR_uA(700),
-	.l2_hyst 		= L2_COMP_CURR_uA(50),
+	.l2_hyst		= ADP5520_L2_COMP_CURR_uA(50),
-	.l3_trip 		= L3_COMP_CURR_uA(80),
+	.l3_trip		= ADP5520_L3_COMP_CURR_uA(80),
-	.l3_hyst 		= L3_COMP_CURR_uA(20),
+	.l3_hyst		= ADP5520_L3_COMP_CURR_uA(20),
 };
 	/*
 	 *  ADP5520/5501 LEDs Data
 	 */
 #include <linux/leds.h>
 static struct led_info adp5520_leds[] = {
 	{
 		.name = "adp5520-led1",
 		.default_trigger = "none",
-		.flags = FLAG_ID_ADP5520_LED1_ADP5501_LED0 | LED_OFFT_600ms,
+		.flags = FLAG_ID_ADP5520_LED1_ADP5501_LED0 | ADP5520_LED_OFFT_600ms,
 	},
 #ifdef ADP5520_EN_ALL_LEDS
 	{
@ -1312,51 +1394,50 @@ static struct led_info adp5520_leds[] = {
 #endif
 };
-static struct adp5520_leds_platfrom_data adp5520_leds_data = {
+static struct adp5520_leds_platform_data adp5520_leds_data = {
 	.num_leds = ARRAY_SIZE(adp5520_leds),
 	.leds = adp5520_leds,
-	.fade_in = FADE_T_600ms,
+	.fade_in = ADP5520_FADE_T_600ms,
-	.fade_out = FADE_T_600ms,
+	.fade_out = ADP5520_FADE_T_600ms,
-	.led_on_time = LED_ONT_600ms,
+	.led_on_time = ADP5520_LED_ONT_600ms,
 };
 	/*
 	 *  ADP5520 GPIO Data
 	 */
-static struct adp5520_gpio_platfrom_data adp5520_gpio_data = {
+static struct adp5520_gpio_platform_data adp5520_gpio_data = {
 	.gpio_start = 50,
-	.gpio_en_mask = GPIO_C1 | GPIO_C2 | GPIO_R2,
+	.gpio_en_mask = ADP5520_GPIO_C1 | ADP5520_GPIO_C2 | ADP5520_GPIO_R2,
-	.gpio_pullup_mask = GPIO_C1 | GPIO_C2 | GPIO_R2,
+	.gpio_pullup_mask = ADP5520_GPIO_C1 | ADP5520_GPIO_C2 | ADP5520_GPIO_R2,
 };
 	/*
 	 *  ADP5520 Keypad Data
 	 */
 #include <linux/input.h>
 static const unsigned short adp5520_keymap[ADP5520_KEYMAPSIZE] = {
-	[KEY(0, 0)]	= KEY_GRAVE,
+	[ADP5520_KEY(0, 0)]	= KEY_GRAVE,
-	[KEY(0, 1)]	= KEY_1,
+	[ADP5520_KEY(0, 1)]	= KEY_1,
-	[KEY(0, 2)]	= KEY_2,
+	[ADP5520_KEY(0, 2)]	= KEY_2,
-	[KEY(0, 3)]	= KEY_3,
+	[ADP5520_KEY(0, 3)]	= KEY_3,
-	[KEY(1, 0)]	= KEY_4,
+	[ADP5520_KEY(1, 0)]	= KEY_4,
-	[KEY(1, 1)]	= KEY_5,
+	[ADP5520_KEY(1, 1)]	= KEY_5,
-	[KEY(1, 2)]	= KEY_6,
+	[ADP5520_KEY(1, 2)]	= KEY_6,
-	[KEY(1, 3)]	= KEY_7,
+	[ADP5520_KEY(1, 3)]	= KEY_7,
-	[KEY(2, 0)]	= KEY_8,
+	[ADP5520_KEY(2, 0)]	= KEY_8,
-	[KEY(2, 1)]	= KEY_9,
+	[ADP5520_KEY(2, 1)]	= KEY_9,
-	[KEY(2, 2)]	= KEY_0,
+	[ADP5520_KEY(2, 2)]	= KEY_0,
-	[KEY(2, 3)]	= KEY_MINUS,
+	[ADP5520_KEY(2, 3)]	= KEY_MINUS,
-	[KEY(3, 0)]	= KEY_EQUAL,
+	[ADP5520_KEY(3, 0)]	= KEY_EQUAL,
-	[KEY(3, 1)]	= KEY_BACKSLASH,
+	[ADP5520_KEY(3, 1)]	= KEY_BACKSLASH,
-	[KEY(3, 2)]	= KEY_BACKSPACE,
+	[ADP5520_KEY(3, 2)]	= KEY_BACKSPACE,
-	[KEY(3, 3)]	= KEY_ENTER,
+	[ADP5520_KEY(3, 3)]	= KEY_ENTER,
 };
-static struct adp5520_keys_platfrom_data adp5520_keys_data = {
+static struct adp5520_keys_platform_data adp5520_keys_data = {
-	.rows_en_mask	= ROW_R3 | ROW_R2 | ROW_R1 | ROW_R0,
+	.rows_en_mask	= ADP5520_ROW_R3 | ADP5520_ROW_R2 | ADP5520_ROW_R1 | ADP5520_ROW_R0,
-	.cols_en_mask	= COL_C3 | COL_C2 | COL_C1 | COL_C0,
+	.cols_en_mask	= ADP5520_COL_C3 | ADP5520_COL_C2 | ADP5520_COL_C1 | ADP5520_COL_C0,
 	.keymap		= adp5520_keymap,
 	.keymapsize	= ARRAY_SIZE(adp5520_keymap),
 	.repeat		= 0,
@ -1366,50 +1447,81 @@ static struct adp5520_keys_platfrom_data adp5520_keys_data = {
 	 *  ADP5520/5501 Multifuction Device Init Data
 	 */
 static struct adp5520_subdev_info adp5520_subdevs[] = {
 	{
 		.name = "adp5520-backlight",
 		.id = ID_ADP5520,
 		.platform_data = &adp5520_backlight_data,
 	},
 	{
 		.name = "adp5520-led",
 		.id = ID_ADP5520,
 		.platform_data = &adp5520_leds_data,
 	},
 	{
 		.name = "adp5520-gpio",
 		.id = ID_ADP5520,
 		.platform_data = &adp5520_gpio_data,
 	},
 	{
 		.name = "adp5520-keys",
 		.id = ID_ADP5520,
 		.platform_data = &adp5520_keys_data,
 	},
 };
 static struct adp5520_platform_data adp5520_pdev_data = {
-	.num_subdevs = ARRAY_SIZE(adp5520_subdevs),
+	.backlight = &adp5520_backlight_data,
-	.subdevs = adp5520_subdevs,
+	.leds = &adp5520_leds_data,
 	.gpio = &adp5520_gpio_data,
 	.keys = &adp5520_keys_data,
 };
 #endif
 #if defined(CONFIG_GPIO_ADP5588) || defined(CONFIG_GPIO_ADP5588_MODULE)
 #include <linux/i2c/adp5588.h>
-static struct adp5588_gpio_platfrom_data adp5588_gpio_data = {
+static struct adp5588_gpio_platform_data adp5588_gpio_data = {
 	.gpio_start = 50,
 	.pullup_dis_mask = 0,
 };
 #endif
 #if defined(CONFIG_BACKLIGHT_ADP8870) || defined(CONFIG_BACKLIGHT_ADP8870_MODULE)
 #include <linux/i2c/adp8870.h>
 static struct led_info adp8870_leds[] = {
 	{
 		.name = "adp8870-led7",
 		.default_trigger = "none",
 		.flags = ADP8870_LED_D7 | ADP8870_LED_OFFT_600ms,
 	},
 };
 static struct adp8870_backlight_platform_data adp8870_pdata = {
 	.bl_led_assign = ADP8870_BL_D1 | ADP8870_BL_D2 | ADP8870_BL_D3 |
 			 ADP8870_BL_D4 | ADP8870_BL_D5 | ADP8870_BL_D6,	/* 1 = Backlight 0 = Individual LED */
 	.pwm_assign = 0,				/* 1 = Enables PWM mode */
 	.bl_fade_in = ADP8870_FADE_T_1200ms,		/* Backlight Fade-In Timer */
 	.bl_fade_out = ADP8870_FADE_T_1200ms,		/* Backlight Fade-Out Timer */
 	.bl_fade_law = ADP8870_FADE_LAW_CUBIC1,		/* fade-on/fade-off transfer characteristic */
 	.en_ambl_sens = 1,				/* 1 = enable ambient light sensor */
 	.abml_filt = ADP8870_BL_AMBL_FILT_320ms,	/* Light sensor filter time */
 	.l1_daylight_max = ADP8870_BL_CUR_mA(20),	/* use BL_CUR_mA(I) 0 <= I <= 30 mA */
 	.l1_daylight_dim = ADP8870_BL_CUR_mA(0),	/* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
 	.l2_bright_max = ADP8870_BL_CUR_mA(14),		/* use BL_CUR_mA(I) 0 <= I <= 30 mA */
 	.l2_bright_dim = ADP8870_BL_CUR_mA(0),		/* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
 	.l3_office_max = ADP8870_BL_CUR_mA(6),		/* use BL_CUR_mA(I) 0 <= I <= 30 mA */
 	.l3_office_dim = ADP8870_BL_CUR_mA(0),		/* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
 	.l4_indoor_max = ADP8870_BL_CUR_mA(3),		/* use BL_CUR_mA(I) 0 <= I <= 30 mA */
 	.l4_indor_dim = ADP8870_BL_CUR_mA(0),		/* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
 	.l5_dark_max = ADP8870_BL_CUR_mA(2),		/* use BL_CUR_mA(I) 0 <= I <= 30 mA */
 	.l5_dark_dim = ADP8870_BL_CUR_mA(0),		/* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
 	.l2_trip = ADP8870_L2_COMP_CURR_uA(710),	/* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */
 	.l2_hyst = ADP8870_L2_COMP_CURR_uA(73),		/* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */
 	.l3_trip = ADP8870_L3_COMP_CURR_uA(389),	/* use L3_COMP_CURR_uA(I) 0 <= I <= 551 uA */
 	.l3_hyst = ADP8870_L3_COMP_CURR_uA(54),		/* use L3_COMP_CURR_uA(I) 0 <= I <= 551 uA */
 	.l4_trip = ADP8870_L4_COMP_CURR_uA(167),	/* use L4_COMP_CURR_uA(I) 0 <= I <= 275 uA */
 	.l4_hyst = ADP8870_L4_COMP_CURR_uA(16),		/* use L4_COMP_CURR_uA(I) 0 <= I <= 275 uA */
 	.l5_trip = ADP8870_L5_COMP_CURR_uA(43),		/* use L5_COMP_CURR_uA(I) 0 <= I <= 138 uA */
 	.l5_hyst = ADP8870_L5_COMP_CURR_uA(11),		/* use L6_COMP_CURR_uA(I) 0 <= I <= 138 uA */
 	.leds = adp8870_leds,
 	.num_leds = ARRAY_SIZE(adp8870_leds),
 	.led_fade_law = ADP8870_FADE_LAW_SQUARE,	/* fade-on/fade-off transfer characteristic */
 	.led_fade_in = ADP8870_FADE_T_600ms,
 	.led_fade_out = ADP8870_FADE_T_600ms,
 	.led_on_time = ADP8870_LED_ONT_200ms,
 };
 #endif
 static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if defined(CONFIG_INPUT_EVAL_AD7142EB)
+#if defined(CONFIG_INPUT_AD714X_I2C) || defined(CONFIG_INPUT_AD714X_I2C_MODULE)
 	{
 		I2C_BOARD_INFO("ad7142_captouch", 0x2C),
 		.irq = IRQ_PG5,
-		.platform_data = (void *)&ad7142_platfrom_data,
+		.platform_data = (void *)&ad7142_i2c_platform_data,
 	},
 #endif
 #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
@ -1462,6 +1574,32 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
 		I2C_BOARD_INFO("bfin-adv7393", 0x2B),
 	},
 #endif
 #if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
 	{
 		I2C_BOARD_INFO("bf537-lq035-ad5280", 0x2C),
 	},
 #endif
 #if defined(CONFIG_BACKLIGHT_ADP8870) || defined(CONFIG_BACKLIGHT_ADP8870_MODULE)
 	{
 		I2C_BOARD_INFO("adp8870", 0x2B),
 		.platform_data = (void *)&adp8870_pdata,
 	},
 #endif
 #if defined(CONFIG_SND_SOC_ADAU1371) || defined(CONFIG_SND_SOC_ADAU1371_MODULE)
 	{
 		I2C_BOARD_INFO("adau1371", 0x1A),
 	},
 #endif
 #if defined(CONFIG_SND_SOC_ADAU1761) || defined(CONFIG_SND_SOC_ADAU1761_MODULE)
 	{
 		I2C_BOARD_INFO("adau1761", 0x38),
 	},
 #endif
 #if defined(CONFIG_AD525X_DPOT) || defined(CONFIG_AD525X_DPOT_MODULE)
 	{
 		I2C_BOARD_INFO("ad5258", 0x18),
 	},
 #endif
 };
 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
@ -1602,8 +1740,8 @@ static struct platform_device *stamp_devices[] __initdata = {
 	&dm9000_device,
 #endif
-#if defined(CONFIG_AX88180) || defined(CONFIG_AX88180_MODULE)
+#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
-	&ax88180_device,
+	&bfin_can_device,
 #endif
 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
--- a/Show More
+++ b/Show More