mirror of https://gitee.com/openkylin/linux.git
ARM: dts: Add support for phyCORE-AM335x SoM
phyCORE-AM335x is a SoM (System on Module) containing a AM335x SOC. The module can be connected to different carrier boards. Some hardware parts are configurable on the phyCORE-AM335x. So they are disabled on default in this som dtsi file. They will be enabled in the board dts files, when populated. * RAM up to 1GiB * PMIC * NAND flash up to 1GiB * Eth PHY on SOM: 1x RMII * SPI NOR flash 8MiB (optional) * i2c RTC (optional) * i2c EEPROM 4kiB (optional) Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Tony Lindgren <tony@atomide.com>
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Teresa Remmet
Tony Lindgren
parent
ec49a86ce0
commit
52b0dcb1d1
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/*
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* Copyright (C) 2015 Phytec Messtechnik GmbH
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* Author: Teresa Remmet <t.remmet@phytec.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include "am33xx.dtsi"
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/ {
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model = "Phytec AM335x phyCORE";
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compatible = "phytec,am335x-phycore-som", "ti,am33xx";
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aliases {
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rtc0 = &i2c_rtc;
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rtc1 = &rtc;
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};
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cpus {
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cpu@0 {
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cpu0-supply = <&vdd1_reg>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x80000000 0x10000000>; /* 256 MB */
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};
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vbat: fixedregulator@0 {
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compatible = "regulator-fixed";
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};
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};
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/* Crypto Module */
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&aes {
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status = "okay";
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};
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&sham {
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status = "okay";
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};
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/* Ethernet */
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&am33xx_pinmux {
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ethernet0_pins: pinmux_ethernet0 {
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pinctrl-single,pins = <
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0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
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0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
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0x114 (PIN_OUTPUT | MUX_MODE1) /* mii1_txen.rmii1_txen */
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0x124 (PIN_OUTPUT | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
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0x128 (PIN_OUTPUT | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
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0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
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0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
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0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */
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>;
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};
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mdio_pins: pinmux_mdio {
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pinctrl-single,pins = <
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/* MDIO */
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0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
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0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
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>;
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};
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};
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&cpsw_emac0 {
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phy_id = <&davinci_mdio>, <0>;
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phy-mode = "rmii";
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dual_emac_res_vlan = <1>;
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};
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&davinci_mdio {
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pinctrl-names = "default";
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pinctrl-0 = <&mdio_pins>;
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status = "okay";
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};
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&mac {
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slaves = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <ðernet0_pins>;
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status = "okay";
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};
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&phy_sel {
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rmii-clock-ext;
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};
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/* I2C Busses */
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&am33xx_pinmux {
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i2c0_pins: pinmux_i2c0 {
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pinctrl-single,pins = <
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0x188 (PIN_INPUT | MUX_MODE0) /* i2c0_sda.i2c0_sda */
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0x18c (PIN_INPUT | MUX_MODE0) /* i2c0_scl.i2c0_scl */
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>;
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};
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};
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&i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins>;
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clock-frequency = <400000>;
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status = "okay";
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tps: pmic@2d {
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reg = <0x2d>;
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};
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i2c_eeprom: eeprom@52 {
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compatible = "atmel,24c32";
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pagesize = <32>;
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reg = <0x52>;
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status = "disabled";
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};
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i2c_rtc: rtc@68 {
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compatible = "rv4162";
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reg = <0x68>;
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status = "disabled";
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};
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};
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/* NAND memory */
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&am33xx_pinmux {
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nandflash_pins: pinmux_nandflash {
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pinctrl-single,pins = <
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0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
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0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
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0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
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0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
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0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
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0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
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0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
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0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
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0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
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0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
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0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
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0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
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0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
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0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
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>;
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};
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};
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&elm {
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status = "okay";
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};
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&gpmc {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&nandflash_pins>;
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ranges = <0 0 0x08000000 0x1000000>; /* CS0: NAND */
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nandflash: nand@0,0 {
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reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
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nand-bus-width = <8>;
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ti,nand-ecc-opt = "bch8";
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gpmc,device-nand = "true";
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gpmc,device-width = <1>;
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gpmc,sync-clk-ps = <0>;
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gpmc,cs-on-ns = <0>;
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gpmc,cs-rd-off-ns = <30>;
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gpmc,cs-wr-off-ns = <30>;
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gpmc,adv-on-ns = <0>;
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gpmc,adv-rd-off-ns = <30>;
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gpmc,adv-wr-off-ns = <30>;
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gpmc,we-on-ns = <0>;
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gpmc,we-off-ns = <20>;
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gpmc,oe-on-ns = <10>;
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gpmc,oe-off-ns = <30>;
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gpmc,access-ns = <30>;
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gpmc,rd-cycle-ns = <30>;
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gpmc,wr-cycle-ns = <30>;
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gpmc,wait-on-read = "true";
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gpmc,wait-on-write = "true";
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gpmc,bus-turnaround-ns = <0>;
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gpmc,cycle2cycle-delay-ns = <50>;
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gpmc,cycle2cycle-diffcsen;
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gpmc,clk-activation-ns = <0>;
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gpmc,wait-monitoring-ns = <0>;
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gpmc,wr-access-ns = <30>;
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gpmc,wr-data-mux-bus-ns = <0>;
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elm_id = <&elm>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "xload";
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reg = <0x0 0x20000>;
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};
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partition@1 {
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label = "xload_backup1";
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reg = <0x20000 0x20000>;
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};
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partition@2 {
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label = "xload_backup2";
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reg = <0x40000 0x20000>;
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};
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partition@3 {
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label = "xload_backup3";
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reg = <0x60000 0x20000>;
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};
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partition@4 {
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label = "barebox";
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reg = <0x80000 0x80000>;
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};
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partition@5 {
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label = "bareboxenv";
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reg = <0x100000 0x40000>;
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};
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partition@6 {
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label = "oftree";
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reg = <0x140000 0x40000>;
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};
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partition@7 {
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label = "kernel";
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reg = <0x180000 0x800000>;
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};
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partition@8 {
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label = "root";
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reg = <0x980000 0x0>;
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};
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};
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};
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/* Power */
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#include "tps65910.dtsi"
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&tps {
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vcc1-supply = <&vbat>;
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vcc2-supply = <&vbat>;
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vcc3-supply = <&vbat>;
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vcc4-supply = <&vbat>;
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vcc5-supply = <&vbat>;
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vcc6-supply = <&vbat>;
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vcc7-supply = <&vbat>;
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vccio-supply = <&vbat>;
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regulators {
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vrtc_reg: regulator@0 {
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regulator-always-on;
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};
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vio_reg: regulator@1 {
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regulator-always-on;
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};
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vdd1_reg: regulator@2 {
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/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
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regulator-name = "vdd_mpu";
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regulator-min-microvolt = <912500>;
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regulator-max-microvolt = <1312500>;
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regulator-boot-on;
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regulator-always-on;
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};
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vdd2_reg: regulator@3 {
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/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
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regulator-name = "vdd_core";
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regulator-min-microvolt = <912500>;
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regulator-max-microvolt = <1150000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vdd3_reg: regulator@4 {
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regulator-always-on;
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};
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vdig1_reg: regulator@5 {
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regulator-name = "vdig1_1p8v";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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vdig2_reg: regulator@6 {
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regulator-always-on;
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};
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vpll_reg: regulator@7 {
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regulator-always-on;
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};
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vdac_reg: regulator@8 {
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regulator-always-on;
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};
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vaux1_reg: regulator@9 {
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regulator-always-on;
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};
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vaux2_reg: regulator@10 {
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regulator-always-on;
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};
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vaux33_reg: regulator@11 {
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regulator-always-on;
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};
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vmmc_reg: regulator@12 {
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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};
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};
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&vbat {
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regulator-name = "vbat";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-boot-on;
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};
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/* SPI Busses */
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&am33xx_pinmux {
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spi0_pins: pinmux_spi0 {
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pinctrl-single,pins = <
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0x150 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_clk.spi0_clk */
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0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_d0.spi0_d0 */
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0x158 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */
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0x15c (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
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>;
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};
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};
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&spi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_pins>;
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status = "okay";
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serial_flash: m25p80@0 {
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compatible = "m25p80";
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spi-max-frequency = <48000000>;
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reg = <0x0>;
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m25p,fast-read;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "xload";
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reg = <0x0 0x20000>;
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};
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partition@1 {
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label = "barebox";
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reg = <0x20000 0x80000>;
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};
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partition@2 {
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label = "bareboxenv";
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reg = <0xa0000 0x20000>;
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};
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partition@3 {
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label = "oftree";
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reg = <0xc0000 0x20000>;
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};
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partition@4 {
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label = "kernel";
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reg = <0xe0000 0x0>;
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};
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};
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};
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