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drm/i915: Clear self-refresh watermarks when disabled 

If we elect to disable self-refresh as they require too many FIFO
entries, clear the values prior to writing them into the registers. If
they are too large they may occupy more bits than available and so
corrupt neighbouring WM values.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Chris Wilson 2012-12-07 10:43:24 +00:00 committed by Daniel Vetter
parent af6c4575af
commit 52bd02d8e3
1 changed files with 8 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
drivers/gpu/drm/i915/intel_pm.c
View File

@ -1303,7 +1303,6 @@ static void valleyview_update_wm(struct drm_device *dev)
&planeb_wm, &cursorb_wm)) &planeb_wm, &cursorb_wm))
enabled |= 2; enabled |= 2;
plane_sr = cursor_sr = 0;
if (single_plane_enabled(enabled) && if (single_plane_enabled(enabled) &&
g4x_compute_srwm(dev, ffs(enabled) - 1, g4x_compute_srwm(dev, ffs(enabled) - 1,
sr_latency_ns, sr_latency_ns,
@ -1314,11 +1313,13 @@ static void valleyview_update_wm(struct drm_device *dev)
2*sr_latency_ns, 2*sr_latency_ns,
&valleyview_wm_info, &valleyview_wm_info,
&valleyview_cursor_wm_info, &valleyview_cursor_wm_info,
&ignore_plane_sr, &cursor_sr)) &ignore_plane_sr, &cursor_sr)) {
I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN); I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
else } else {
I915_WRITE(FW_BLC_SELF_VLV, I915_WRITE(FW_BLC_SELF_VLV,
I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN); I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
plane_sr = cursor_sr = 0;
}
DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
planea_wm, cursora_wm, planea_wm, cursora_wm,
@ -1358,17 +1359,18 @@ static void g4x_update_wm(struct drm_device *dev)
&planeb_wm, &cursorb_wm)) &planeb_wm, &cursorb_wm))
enabled |= 2; enabled |= 2;
plane_sr = cursor_sr = 0;
if (single_plane_enabled(enabled) && if (single_plane_enabled(enabled) &&
g4x_compute_srwm(dev, ffs(enabled) - 1, g4x_compute_srwm(dev, ffs(enabled) - 1,
sr_latency_ns, sr_latency_ns,
&g4x_wm_info, &g4x_wm_info,
&g4x_cursor_wm_info, &g4x_cursor_wm_info,
&plane_sr, &cursor_sr)) &plane_sr, &cursor_sr)) {
I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
else } else {
I915_WRITE(FW_BLC_SELF, I915_WRITE(FW_BLC_SELF,
I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN); I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
plane_sr = cursor_sr = 0;
}
DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
planea_wm, cursora_wm, planea_wm, cursora_wm,