mirror of https://gitee.com/openkylin/linux.git
can: c_can: Add d_can raminit support
Add D_CAN raminit support to C_CAN driver to enable D_CAN RAM, which holds all the message objects during transmission or receiving of data. This initialization/de-initialization should be done in synchronous with D_CAN clock. In case of AM335X-EVM (current user of D_CAN driver) message RAM is controlled through control module register for both instances. So control module register details is required to initialization or de-initialization of message RAM according to instance number. Control module memory resource is obtained from D_CAN dt node and instance number obtained from device tree aliases node. This patch was tested on AM335x-EVM along with pinctrl data addition patch, d_can dt aliases addition and control module data addition. pinctrl data addition is not added to am335x-evm.dts (only supports CPLD profile#0) because d_can1 is supported under CPLD profile#1. Signed-off-by: AnilKumar Ch <anilkumar@ti.com> [mkl: fix instance for non DT in probe, cleaned up raminit] Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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@ -233,6 +233,12 @@ static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv)
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pm_runtime_put_sync(priv->device);
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pm_runtime_put_sync(priv->device);
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}
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}
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static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable)
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{
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if (priv->raminit)
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priv->raminit(priv, enable);
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}
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static inline int get_tx_next_msg_obj(const struct c_can_priv *priv)
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static inline int get_tx_next_msg_obj(const struct c_can_priv *priv)
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{
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{
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return (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) +
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return (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) +
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@ -1090,6 +1096,7 @@ static int c_can_open(struct net_device *dev)
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struct c_can_priv *priv = netdev_priv(dev);
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struct c_can_priv *priv = netdev_priv(dev);
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c_can_pm_runtime_get_sync(priv);
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c_can_pm_runtime_get_sync(priv);
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c_can_reset_ram(priv, true);
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/* open the can device */
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/* open the can device */
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err = open_candev(dev);
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err = open_candev(dev);
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@ -1118,6 +1125,7 @@ static int c_can_open(struct net_device *dev)
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exit_irq_fail:
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exit_irq_fail:
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close_candev(dev);
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close_candev(dev);
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exit_open_fail:
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exit_open_fail:
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c_can_reset_ram(priv, false);
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c_can_pm_runtime_put_sync(priv);
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c_can_pm_runtime_put_sync(priv);
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return err;
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return err;
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}
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}
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@ -1131,6 +1139,8 @@ static int c_can_close(struct net_device *dev)
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c_can_stop(dev);
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c_can_stop(dev);
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free_irq(dev->irq, dev);
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free_irq(dev->irq, dev);
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close_candev(dev);
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close_candev(dev);
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c_can_reset_ram(priv, false);
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c_can_pm_runtime_put_sync(priv);
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c_can_pm_runtime_put_sync(priv);
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return 0;
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return 0;
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@ -1188,6 +1198,7 @@ int c_can_power_down(struct net_device *dev)
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c_can_stop(dev);
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c_can_stop(dev);
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c_can_reset_ram(priv, false);
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c_can_pm_runtime_put_sync(priv);
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c_can_pm_runtime_put_sync(priv);
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return 0;
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return 0;
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@ -1206,6 +1217,7 @@ int c_can_power_up(struct net_device *dev)
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WARN_ON(priv->type != BOSCH_D_CAN);
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WARN_ON(priv->type != BOSCH_D_CAN);
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c_can_pm_runtime_get_sync(priv);
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c_can_pm_runtime_get_sync(priv);
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c_can_reset_ram(priv, true);
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/* Clear PDR and INIT bits */
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/* Clear PDR and INIT bits */
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val = priv->read_reg(priv, C_CAN_CTRL_EX_REG);
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val = priv->read_reg(priv, C_CAN_CTRL_EX_REG);
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@ -169,6 +169,9 @@ struct c_can_priv {
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void *priv; /* for board-specific data */
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void *priv; /* for board-specific data */
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u16 irqstatus;
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u16 irqstatus;
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enum c_can_dev_id type;
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enum c_can_dev_id type;
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u32 __iomem *raminit_ctrlreg;
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unsigned int instance;
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void (*raminit) (const struct c_can_priv *priv, bool enable);
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};
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};
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struct net_device *alloc_c_can_dev(void);
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struct net_device *alloc_c_can_dev(void);
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@ -38,6 +38,8 @@
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#include "c_can.h"
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#include "c_can.h"
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#define CAN_RAMINIT_START_MASK(i) (1 << (i))
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/*
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/*
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* 16-bit c_can registers can be arranged differently in the memory
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* 16-bit c_can registers can be arranged differently in the memory
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* architecture of different implementations. For example: 16-bit
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* architecture of different implementations. For example: 16-bit
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@ -68,6 +70,18 @@ static void c_can_plat_write_reg_aligned_to_32bit(struct c_can_priv *priv,
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writew(val, priv->base + 2 * priv->regs[index]);
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writew(val, priv->base + 2 * priv->regs[index]);
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}
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}
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static void c_can_hw_raminit(const struct c_can_priv *priv, bool enable)
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{
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u32 val;
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val = readl(priv->raminit_ctrlreg);
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if (enable)
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val |= CAN_RAMINIT_START_MASK(priv->instance);
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else
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val &= ~CAN_RAMINIT_START_MASK(priv->instance);
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writel(val, priv->raminit_ctrlreg);
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}
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static struct platform_device_id c_can_id_table[] = {
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static struct platform_device_id c_can_id_table[] = {
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[BOSCH_C_CAN_PLATFORM] = {
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[BOSCH_C_CAN_PLATFORM] = {
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.name = KBUILD_MODNAME,
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.name = KBUILD_MODNAME,
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@ -99,7 +113,7 @@ static int __devinit c_can_plat_probe(struct platform_device *pdev)
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const struct of_device_id *match;
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const struct of_device_id *match;
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const struct platform_device_id *id;
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const struct platform_device_id *id;
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struct pinctrl *pinctrl;
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struct pinctrl *pinctrl;
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struct resource *mem;
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struct resource *mem, *res;
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int irq;
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int irq;
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struct clk *clk;
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struct clk *clk;
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@ -178,6 +192,18 @@ static int __devinit c_can_plat_probe(struct platform_device *pdev)
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priv->can.ctrlmode_supported |= CAN_CTRLMODE_3_SAMPLES;
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priv->can.ctrlmode_supported |= CAN_CTRLMODE_3_SAMPLES;
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priv->read_reg = c_can_plat_read_reg_aligned_to_16bit;
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priv->read_reg = c_can_plat_read_reg_aligned_to_16bit;
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priv->write_reg = c_can_plat_write_reg_aligned_to_16bit;
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priv->write_reg = c_can_plat_write_reg_aligned_to_16bit;
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if (pdev->dev.of_node)
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priv->instance = of_alias_get_id(pdev->dev.of_node, "d_can");
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else
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priv->instance = pdev->id;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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priv->raminit_ctrlreg = devm_request_and_ioremap(&pdev->dev, res);
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if (!priv->raminit_ctrlreg || priv->instance < 0)
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dev_info(&pdev->dev, "control memory is not used for raminit\n");
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else
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priv->raminit = c_can_hw_raminit;
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break;
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break;
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default:
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default:
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ret = -EINVAL;
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ret = -EINVAL;
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