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pinctrl: sh-pfc: Updates for v4.8 

- Voltage switching support for R-Car H3,
   - DRIF pin support for R-Car H3,
   - Cleanups and fixes.
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Merge tag 'sh-pfc-for-v4.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v4.8

  - Voltage switching support for R-Car H3,
  - DRIF pin support for R-Car H3,
  - Cleanups and fixes.
This commit is contained in:
Linus Walleij 2016-06-29 10:02:06 +02:00
parent 4e80c8f505 2d77583198
commit 53673a5179
13 changed files with 414 additions and 159 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
View File

@ -72,7 +72,7 @@ Pin Configuration Node Properties:
The pin configuration parameters use the generic pinconf bindings defined in
pinctrl-bindings.txt in this directory. The supported parameters are
bias-disable, bias-pull-up, bias-pull-down, drive strength and power-source. For
bias-disable, bias-pull-up, bias-pull-down, drive-strength and power-source. For
pins that have a configurable I/O voltage, the power-source value should be the
nominal I/O voltage in millivolts.

10
drivers/pinctrl/sh-pfc/core.c
View File

@ -598,15 +598,6 @@ static int sh_pfc_probe(struct platform_device *pdev)
return 0;
}
static int sh_pfc_remove(struct platform_device *pdev)
{
#ifdef CONFIG_PINCTRL_SH_PFC_GPIO
sh_pfc_unregister_gpiochip(platform_get_drvdata(pdev));
#endif
return 0;
}
static const struct platform_device_id sh_pfc_id_table[] = {
#ifdef CONFIG_PINCTRL_PFC_SH7203
{ "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
@ -650,7 +641,6 @@ static const struct platform_device_id sh_pfc_id_table[] = {
static struct platform_driver sh_pfc_driver = {
.probe = sh_pfc_probe,
.remove = sh_pfc_remove,
.id_table = sh_pfc_id_table,
.driver = {
.name = DRV_NAME,

58
drivers/pinctrl/sh-pfc/core.h
View File

@ -10,50 +10,16 @@
#ifndef __SH_PFC_CORE_H__
#define __SH_PFC_CORE_H__
#include <linux/compiler.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include "sh_pfc.h"
struct sh_pfc_window {
phys_addr_t phys;
void __iomem *virt;
unsigned long size;
};
struct sh_pfc_chip;
struct sh_pfc_pinctrl;
struct sh_pfc_pin_range {
u16 start;
u16 end;
};
struct sh_pfc {
struct device *dev;
const struct sh_pfc_soc_info *info;
spinlock_t lock;
unsigned int num_windows;
struct sh_pfc_window *windows;
unsigned int num_irqs;
unsigned int *irqs;
struct sh_pfc_pin_range *ranges;
unsigned int nr_ranges;
unsigned int nr_gpio_pins;
struct sh_pfc_chip *gpio;
#ifdef CONFIG_SUPERH
struct sh_pfc_chip *func;
#endif
};
int sh_pfc_register_gpiochip(struct sh_pfc *pfc);
int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc);
int sh_pfc_register_pinctrl(struct sh_pfc *pfc);
@ -67,28 +33,4 @@ void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width,
int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin);
int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
extern const struct sh_pfc_soc_info emev2_pinmux_info;
extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
extern const struct sh_pfc_soc_info sh7203_pinmux_info;
extern const struct sh_pfc_soc_info sh7264_pinmux_info;
extern const struct sh_pfc_soc_info sh7269_pinmux_info;
extern const struct sh_pfc_soc_info sh73a0_pinmux_info;
extern const struct sh_pfc_soc_info sh7720_pinmux_info;
extern const struct sh_pfc_soc_info sh7722_pinmux_info;
extern const struct sh_pfc_soc_info sh7723_pinmux_info;
extern const struct sh_pfc_soc_info sh7724_pinmux_info;
extern const struct sh_pfc_soc_info sh7734_pinmux_info;
extern const struct sh_pfc_soc_info sh7757_pinmux_info;
extern const struct sh_pfc_soc_info sh7785_pinmux_info;
extern const struct sh_pfc_soc_info sh7786_pinmux_info;
extern const struct sh_pfc_soc_info shx3_pinmux_info;
#endif /* __SH_PFC_CORE_H__ */

13
drivers/pinctrl/sh-pfc/gpio.c
View File

@ -318,7 +318,7 @@ sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *),
if (ret < 0)
return ERR_PTR(ret);
ret = gpiochip_add_data(&chip->gpio_chip, chip);
ret = devm_gpiochip_add_data(pfc->dev, &chip->gpio_chip, chip);
if (unlikely(ret < 0))
return ERR_PTR(ret);
@ -399,18 +399,7 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL);
if (IS_ERR(chip))
return PTR_ERR(chip);
pfc->func = chip;
#endif /* CONFIG_SUPERH */
return 0;
}
int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc)
{
gpiochip_remove(&pfc->gpio->gpio_chip);
#ifdef CONFIG_SUPERH
gpiochip_remove(&pfc->func->gpio_chip);
#endif
return 0;
}

1
drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
View File

@ -21,7 +21,6 @@
#include <linux/kernel.h>
#include <linux/pinctrl/pinconf-generic.h>
#include "core.h"
#include "sh_pfc.h"
#define CPU_ALL_PORT(fn, pfx, sfx) \

1
drivers/pinctrl/sh-pfc/pfc-r8a7740.c
View File

@ -22,7 +22,6 @@
#include <linux/kernel.h>
#include <linux/pinctrl/pinconf-generic.h>
#include "core.h"
#include "sh_pfc.h"
#define CPU_ALL_PORT(fn, pfx, sfx) \

2
drivers/pinctrl/sh-pfc/pfc-r8a7778.c
View File

@ -23,7 +23,7 @@
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/pinctrl/pinconf-generic.h>
#include "core.h"
#include "sh_pfc.h"
#define PORT_GP_PUP_1(bank, pin, fn, sfx) \

59
drivers/pinctrl/sh-pfc/pfc-r8a7790.c
View File

@ -24,7 +24,6 @@
#include <linux/io.h>
#include <linux/kernel.h>
#include "core.h"
#include "sh_pfc.h"
/*
@ -4696,47 +4695,6 @@ static const char * const vin3_groups[] = {
"vin3_clk",
};
#define IOCTRL6 0x8c
static int r8a7790_get_io_voltage(struct sh_pfc *pfc, unsigned int pin)
{
u32 data, mask;
if (WARN(pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31), "invalid pin %#x", pin))
return -EINVAL;
data = ioread32(pfc->windows->virt + IOCTRL6),
/* Bits in IOCTRL6 are numbered in opposite order to pins */
mask = 0x80000000 >> (pin & 0x1f);
return (data & mask) ? 3300 : 1800;
}
static int r8a7790_set_io_voltage(struct sh_pfc *pfc, unsigned int pin, u16 mV)
{
u32 data, mask;
if (WARN(pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31), "invalid pin %#x", pin))
return -EINVAL;
if (mV != 1800 && mV != 3300)
return -EINVAL;
data = ioread32(pfc->windows->virt + IOCTRL6);
/* Bits in IOCTRL6 are numbered in opposite order to pins */
mask = 0x80000000 >> (pin & 0x1f);
if (mV == 3300)
data |= mask;
else
data &= ~mask;
iowrite32(~data, pfc->windows->virt); /* unlock reg */
iowrite32(data, pfc->windows->virt + IOCTRL6);
return 0;
}
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(audio_clk),
SH_PFC_FUNCTION(avb),
@ -5736,14 +5694,23 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ },
};
static const struct sh_pfc_soc_operations pinmux_ops = {
.get_io_voltage = r8a7790_get_io_voltage,
.set_io_voltage = r8a7790_set_io_voltage,
static int r8a7790_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
{
if (pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31))
return -EINVAL;
*pocctrl = 0xe606008c;
return 31 - (pin & 0x1f);
}
static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = {
.pin_to_pocctrl = r8a7790_pin_to_pocctrl,
};
const struct sh_pfc_soc_info r8a7790_pinmux_info = {
.name = "r8a77900_pfc",
.ops = &pinmux_ops,
.ops = &r8a7790_pinmux_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

1
drivers/pinctrl/sh-pfc/pfc-r8a7791.c
View File

@ -11,7 +11,6 @@
#include <linux/kernel.h>
#include "core.h"
#include "sh_pfc.h"
#define CPU_ALL_PORT(fn, sfx) \

327
drivers/pinctrl/sh-pfc/pfc-r8a7795.c
View File

@ -17,8 +17,12 @@
PORT_GP_CFG_16(0, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
PORT_GP_CFG_15(2, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
PORT_GP_CFG_16(3, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
PORT_GP_CFG_18(4, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
PORT_GP_CFG_12(3, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(3, 12, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
PORT_GP_CFG_1(3, 13, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
PORT_GP_CFG_1(3, 14, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
PORT_GP_CFG_1(3, 15, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
PORT_GP_CFG_18(4, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_26(5, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
PORT_GP_CFG_32(6, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
PORT_GP_CFG_4(7, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH)
@ -552,6 +556,9 @@ static const u16 pinmux_data[] = {
PINMUX_SINGLE(AVS2),
PINMUX_SINGLE(HDMI0_CEC),
PINMUX_SINGLE(HDMI1_CEC),
PINMUX_SINGLE(I2C_SEL_0_1),
PINMUX_SINGLE(I2C_SEL_3_1),
PINMUX_SINGLE(I2C_SEL_5_1),
PINMUX_SINGLE(MSIOF0_RXD),
PINMUX_SINGLE(MSIOF0_SCK),
PINMUX_SINGLE(MSIOF0_TXD),
@ -1401,11 +1408,6 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP17_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP17_7_4, RIF2_D1_B, SEL_DRIF2_1),
PINMUX_IPSR_GPSR(IP17_7_4, TPU0TO3),
/* I2C */
PINMUX_IPSR_NOGP(0, I2C_SEL_0_1),
PINMUX_IPSR_NOGP(0, I2C_SEL_3_1),
PINMUX_IPSR_NOGP(0, I2C_SEL_5_1),
};
static const struct sh_pfc_pin pinmux_pins[] = {
@ -1654,6 +1656,221 @@ static const unsigned int canfd1_data_mux[] = {
CANFD1_TX_MARK, CANFD1_RX_MARK,
};
/* - DRIF0 --------------------------------------------------------------- */
static const unsigned int drif0_ctrl_a_pins[] = {
/* CLK, SYNC */
RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
};
static const unsigned int drif0_ctrl_a_mux[] = {
RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
};
static const unsigned int drif0_data0_a_pins[] = {
/* D0 */
RCAR_GP_PIN(6, 10),
};
static const unsigned int drif0_data0_a_mux[] = {
RIF0_D0_A_MARK,
};
static const unsigned int drif0_data1_a_pins[] = {
/* D1 */
RCAR_GP_PIN(6, 7),
};
static const unsigned int drif0_data1_a_mux[] = {
RIF0_D1_A_MARK,
};
static const unsigned int drif0_ctrl_b_pins[] = {
/* CLK, SYNC */
RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
};
static const unsigned int drif0_ctrl_b_mux[] = {
RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
};
static const unsigned int drif0_data0_b_pins[] = {
/* D0 */
RCAR_GP_PIN(5, 1),
};
static const unsigned int drif0_data0_b_mux[] = {
RIF0_D0_B_MARK,
};
static const unsigned int drif0_data1_b_pins[] = {
/* D1 */
RCAR_GP_PIN(5, 2),
};
static const unsigned int drif0_data1_b_mux[] = {
RIF0_D1_B_MARK,
};
static const unsigned int drif0_ctrl_c_pins[] = {
/* CLK, SYNC */
RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
};
static const unsigned int drif0_ctrl_c_mux[] = {
RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
};
static const unsigned int drif0_data0_c_pins[] = {
/* D0 */
RCAR_GP_PIN(5, 13),
};
static const unsigned int drif0_data0_c_mux[] = {
RIF0_D0_C_MARK,
};
static const unsigned int drif0_data1_c_pins[] = {
/* D1 */
RCAR_GP_PIN(5, 14),
};
static const unsigned int drif0_data1_c_mux[] = {
RIF0_D1_C_MARK,
};
/* - DRIF1 --------------------------------------------------------------- */
static const unsigned int drif1_ctrl_a_pins[] = {
/* CLK, SYNC */
RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
};
static const unsigned int drif1_ctrl_a_mux[] = {
RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
};
static const unsigned int drif1_data0_a_pins[] = {
/* D0 */
RCAR_GP_PIN(6, 19),
};
static const unsigned int drif1_data0_a_mux[] = {
RIF1_D0_A_MARK,
};
static const unsigned int drif1_data1_a_pins[] = {
/* D1 */
RCAR_GP_PIN(6, 20),
};
static const unsigned int drif1_data1_a_mux[] = {
RIF1_D1_A_MARK,
};
static const unsigned int drif1_ctrl_b_pins[] = {
/* CLK, SYNC */
RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
};
static const unsigned int drif1_ctrl_b_mux[] = {
RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
};
static const unsigned int drif1_data0_b_pins[] = {
/* D0 */
RCAR_GP_PIN(5, 7),
};
static const unsigned int drif1_data0_b_mux[] = {
RIF1_D0_B_MARK,
};
static const unsigned int drif1_data1_b_pins[] = {
/* D1 */
RCAR_GP_PIN(5, 8),
};
static const unsigned int drif1_data1_b_mux[] = {
RIF1_D1_B_MARK,
};
static const unsigned int drif1_ctrl_c_pins[] = {
/* CLK, SYNC */
RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
};
static const unsigned int drif1_ctrl_c_mux[] = {
RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
};
static const unsigned int drif1_data0_c_pins[] = {
/* D0 */
RCAR_GP_PIN(5, 6),
};
static const unsigned int drif1_data0_c_mux[] = {
RIF1_D0_C_MARK,
};
static const unsigned int drif1_data1_c_pins[] = {
/* D1 */
RCAR_GP_PIN(5, 10),
};
static const unsigned int drif1_data1_c_mux[] = {
RIF1_D1_C_MARK,
};
/* - DRIF2 --------------------------------------------------------------- */
static const unsigned int drif2_ctrl_a_pins[] = {
/* CLK, SYNC */
RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
};
static const unsigned int drif2_ctrl_a_mux[] = {
RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
};
static const unsigned int drif2_data0_a_pins[] = {
/* D0 */
RCAR_GP_PIN(6, 7),
};
static const unsigned int drif2_data0_a_mux[] = {
RIF2_D0_A_MARK,
};
static const unsigned int drif2_data1_a_pins[] = {
/* D1 */
RCAR_GP_PIN(6, 10),
};
static const unsigned int drif2_data1_a_mux[] = {
RIF2_D1_A_MARK,
};
static const unsigned int drif2_ctrl_b_pins[] = {
/* CLK, SYNC */
RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
};
static const unsigned int drif2_ctrl_b_mux[] = {
RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
};
static const unsigned int drif2_data0_b_pins[] = {
/* D0 */
RCAR_GP_PIN(6, 30),
};
static const unsigned int drif2_data0_b_mux[] = {
RIF2_D0_B_MARK,
};
static const unsigned int drif2_data1_b_pins[] = {
/* D1 */
RCAR_GP_PIN(6, 31),
};
static const unsigned int drif2_data1_b_mux[] = {
RIF2_D1_B_MARK,
};
/* - DRIF3 --------------------------------------------------------------- */
static const unsigned int drif3_ctrl_a_pins[] = {
/* CLK, SYNC */
RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
};
static const unsigned int drif3_ctrl_a_mux[] = {
RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
};
static const unsigned int drif3_data0_a_pins[] = {
/* D0 */
RCAR_GP_PIN(6, 19),
};
static const unsigned int drif3_data0_a_mux[] = {
RIF3_D0_A_MARK,
};
static const unsigned int drif3_data1_a_pins[] = {
/* D1 */
RCAR_GP_PIN(6, 20),
};
static const unsigned int drif3_data1_a_mux[] = {
RIF3_D1_A_MARK,
};
static const unsigned int drif3_ctrl_b_pins[] = {
/* CLK, SYNC */
RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
};
static const unsigned int drif3_ctrl_b_mux[] = {
RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
};
static const unsigned int drif3_data0_b_pins[] = {
/* D0 */
RCAR_GP_PIN(6, 28),
};
static const unsigned int drif3_data0_b_mux[] = {
RIF3_D0_B_MARK,
};
static const unsigned int drif3_data1_b_pins[] = {
/* D1 */
RCAR_GP_PIN(6, 29),
};
static const unsigned int drif3_data1_b_mux[] = {
RIF3_D1_B_MARK,
};
/* - HSCIF0 ----------------------------------------------------------------- */
static const unsigned int hscif0_data_pins[] = {
/* RX, TX */
@ -3346,6 +3563,36 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(canfd0_data_a),
SH_PFC_PIN_GROUP(canfd0_data_b),
SH_PFC_PIN_GROUP(canfd1_data),
SH_PFC_PIN_GROUP(drif0_ctrl_a),
SH_PFC_PIN_GROUP(drif0_data0_a),
SH_PFC_PIN_GROUP(drif0_data1_a),
SH_PFC_PIN_GROUP(drif0_ctrl_b),
SH_PFC_PIN_GROUP(drif0_data0_b),
SH_PFC_PIN_GROUP(drif0_data1_b),
SH_PFC_PIN_GROUP(drif0_ctrl_c),
SH_PFC_PIN_GROUP(drif0_data0_c),
SH_PFC_PIN_GROUP(drif0_data1_c),
SH_PFC_PIN_GROUP(drif1_ctrl_a),
SH_PFC_PIN_GROUP(drif1_data0_a),
SH_PFC_PIN_GROUP(drif1_data1_a),
SH_PFC_PIN_GROUP(drif1_ctrl_b),
SH_PFC_PIN_GROUP(drif1_data0_b),
SH_PFC_PIN_GROUP(drif1_data1_b),
SH_PFC_PIN_GROUP(drif1_ctrl_c),
SH_PFC_PIN_GROUP(drif1_data0_c),
SH_PFC_PIN_GROUP(drif1_data1_c),
SH_PFC_PIN_GROUP(drif2_ctrl_a),
SH_PFC_PIN_GROUP(drif2_data0_a),
SH_PFC_PIN_GROUP(drif2_data1_a),
SH_PFC_PIN_GROUP(drif2_ctrl_b),
SH_PFC_PIN_GROUP(drif2_data0_b),
SH_PFC_PIN_GROUP(drif2_data1_b),
SH_PFC_PIN_GROUP(drif3_ctrl_a),
SH_PFC_PIN_GROUP(drif3_data0_a),
SH_PFC_PIN_GROUP(drif3_data1_a),
SH_PFC_PIN_GROUP(drif3_ctrl_b),
SH_PFC_PIN_GROUP(drif3_data0_b),
SH_PFC_PIN_GROUP(drif3_data1_b),
SH_PFC_PIN_GROUP(hscif0_data),
SH_PFC_PIN_GROUP(hscif0_clk),
SH_PFC_PIN_GROUP(hscif0_ctrl),
@ -3629,6 +3876,48 @@ static const char * const canfd1_groups[] = {
"canfd1_data",
};
static const char * const drif0_groups[] = {
"drif0_ctrl_a",
"drif0_data0_a",
"drif0_data1_a",
"drif0_ctrl_b",
"drif0_data0_b",
"drif0_data1_b",
"drif0_ctrl_c",
"drif0_data0_c",
"drif0_data1_c",
};
static const char * const drif1_groups[] = {
"drif1_ctrl_a",
"drif1_data0_a",
"drif1_data1_a",
"drif1_ctrl_b",
"drif1_data0_b",
"drif1_data1_b",
"drif1_ctrl_c",
"drif1_data0_c",
"drif1_data1_c",
};
static const char * const drif2_groups[] = {
"drif2_ctrl_a",
"drif2_data0_a",
"drif2_data1_a",
"drif2_ctrl_b",
"drif2_data0_b",
"drif2_data1_b",
};
static const char * const drif3_groups[] = {
"drif3_ctrl_a",
"drif3_data0_a",
"drif3_data1_a",
"drif3_ctrl_b",
"drif3_data0_b",
"drif3_data1_b",
};
static const char * const hscif0_groups[] = {
"hscif0_data",
"hscif0_clk",
@ -3972,6 +4261,10 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(can_clk),
SH_PFC_FUNCTION(canfd0),
SH_PFC_FUNCTION(canfd1),
SH_PFC_FUNCTION(drif0),
SH_PFC_FUNCTION(drif1),
SH_PFC_FUNCTION(drif2),
SH_PFC_FUNCTION(drif3),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(hscif2),
@ -4765,8 +5058,28 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ },
};
static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
{
int bit = -EINVAL;
*pocctrl = 0xe6060380;
if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
bit = pin & 0x1f;
if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
bit = (pin & 0x1f) + 12;
return bit;
}
static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
.pin_to_pocctrl = r8a7795_pin_to_pocctrl,
};
const struct sh_pfc_soc_info r8a7795_pinmux_info = {
.name = "r8a77950_pfc",
.ops = &r8a7795_pinmux_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

1
drivers/pinctrl/sh-pfc/pfc-sh7757.c
View File

@ -1625,7 +1625,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(VBIOS_CS),
/* PTW (mobule: LBSC, EVC, SCIF) */
GPIO_FN(A16),
GPIO_FN(A15),
GPIO_FN(A14),
GPIO_FN(A13),

43
drivers/pinctrl/sh-pfc/pinctrl.c
View File

@ -632,19 +632,21 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
}
case PIN_CONFIG_POWER_SOURCE: {
int ret;
u32 pocctrl, val;
int bit;
if (!pfc->info->ops || !pfc->info->ops->get_io_voltage)
if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
return -ENOTSUPP;
bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &pocctrl);
if (WARN(bit < 0, "invalid pin %#x", _pin))
return bit;
spin_lock_irqsave(&pfc->lock, flags);
ret = pfc->info->ops->get_io_voltage(pfc, _pin);
val = sh_pfc_read_reg(pfc, pocctrl, 32);
spin_unlock_irqrestore(&pfc->lock, flags);
if (ret < 0)
return ret;
*config = ret;
*config = (val & BIT(bit)) ? 3300 : 1800;
break;
}
@ -696,19 +698,28 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
}
case PIN_CONFIG_POWER_SOURCE: {
unsigned int arg =
pinconf_to_config_argument(configs[i]);
int ret;
unsigned int mV = pinconf_to_config_argument(configs[i]);
u32 pocctrl, val;
int bit;
if (!pfc->info->ops || !pfc->info->ops->set_io_voltage)
if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
return -ENOTSUPP;
spin_lock_irqsave(&pfc->lock, flags);
ret = pfc->info->ops->set_io_voltage(pfc, _pin, arg);
spin_unlock_irqrestore(&pfc->lock, flags);
bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &pocctrl);
if (WARN(bit < 0, "invalid pin %#x", _pin))
return bit;
if (ret)
return ret;
if (mV != 1800 && mV != 3300)
return -EINVAL;
spin_lock_irqsave(&pfc->lock, flags);
val = sh_pfc_read_reg(pfc, pocctrl, 32);
if (mV == 3300)
val |= BIT(bit);
else
val &= ~BIT(bit);
sh_pfc_write_reg(pfc, pocctrl, 32, val);
spin_unlock_irqrestore(&pfc->lock, flags);
break;
}

55
drivers/pinctrl/sh-pfc/sh_pfc.h
View File

@ -13,6 +13,7 @@
#include <linux/bug.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/spinlock.h>
#include <linux/stringify.h>
enum {
@ -182,16 +183,38 @@ struct pinmux_range {
u16 force;
};
struct sh_pfc;
struct sh_pfc_window {
phys_addr_t phys;
void __iomem *virt;
unsigned long size;
};
struct sh_pfc_pin_range;
struct sh_pfc {
struct device *dev;
const struct sh_pfc_soc_info *info;
spinlock_t lock;
unsigned int num_windows;
struct sh_pfc_window *windows;
unsigned int num_irqs;
unsigned int *irqs;
struct sh_pfc_pin_range *ranges;
unsigned int nr_ranges;
unsigned int nr_gpio_pins;
struct sh_pfc_chip *gpio;
};
struct sh_pfc_soc_operations {
int (*init)(struct sh_pfc *pfc);
unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
unsigned int bias);
int (*get_io_voltage)(struct sh_pfc *pfc, unsigned int pin);
int (*set_io_voltage)(struct sh_pfc *pfc, unsigned int pin,
u16 voltage_mV);
int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl);
};
struct sh_pfc_soc_info {
@ -227,6 +250,30 @@ struct sh_pfc_soc_info {
u32 unlock_reg;
};
extern const struct sh_pfc_soc_info emev2_pinmux_info;
extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
extern const struct sh_pfc_soc_info sh7203_pinmux_info;
extern const struct sh_pfc_soc_info sh7264_pinmux_info;
extern const struct sh_pfc_soc_info sh7269_pinmux_info;
extern const struct sh_pfc_soc_info sh73a0_pinmux_info;
extern const struct sh_pfc_soc_info sh7720_pinmux_info;
extern const struct sh_pfc_soc_info sh7722_pinmux_info;
extern const struct sh_pfc_soc_info sh7723_pinmux_info;
extern const struct sh_pfc_soc_info sh7724_pinmux_info;
extern const struct sh_pfc_soc_info sh7734_pinmux_info;
extern const struct sh_pfc_soc_info sh7757_pinmux_info;
extern const struct sh_pfc_soc_info sh7785_pinmux_info;
extern const struct sh_pfc_soc_info sh7786_pinmux_info;
extern const struct sh_pfc_soc_info shx3_pinmux_info;
/* -----------------------------------------------------------------------------
* Helper macros to create pin and port lists
*/