mirror of https://gitee.com/openkylin/linux.git
net-next/hinic: Set qp context
Update the nic about the resources of the queue pairs. Signed-off-by: Aviad Krawczyk <aviad.krawczyk@huawei.com> Signed-off-by: Zhao Chen <zhaochen6@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Aviad Krawczyk
David S. Miller
parent
f91090f7da
commit
53e7d6feb9
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@ -1,5 +1,6 @@
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obj-$(CONFIG_HINIC) += hinic.o
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hinic-y := hinic_main.o hinic_tx.o hinic_rx.o hinic_port.o hinic_hw_dev.o \
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hinic_hw_io.o hinic_hw_qp.o hinic_hw_wq.o hinic_hw_mgmt.o \
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hinic_hw_api_cmd.o hinic_hw_eqs.o hinic_hw_if.o
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hinic_hw_io.o hinic_hw_qp.o hinic_hw_cmdq.o hinic_hw_wq.o \
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hinic_hw_mgmt.o hinic_hw_api_cmd.o hinic_hw_eqs.o hinic_hw_if.o \
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hinic_common.o
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@ -0,0 +1,55 @@
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/*
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* Huawei HiNIC PCI Express Linux driver
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* Copyright(c) 2017 Huawei Technologies Co., Ltd
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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*/
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#include <linux/types.h>
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#include <asm/byteorder.h>
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#include "hinic_common.h"
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/**
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* hinic_cpu_to_be32 - convert data to big endian 32 bit format
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* @data: the data to convert
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* @len: length of data to convert
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**/
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void hinic_cpu_to_be32(void *data, int len)
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{
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u32 *mem = data;
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int i;
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len = len / sizeof(u32);
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for (i = 0; i < len; i++) {
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*mem = cpu_to_be32(*mem);
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mem++;
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}
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}
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/**
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* hinic_be32_to_cpu - convert data from big endian 32 bit format
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* @data: the data to convert
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* @len: length of data to convert
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**/
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void hinic_be32_to_cpu(void *data, int len)
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{
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u32 *mem = data;
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int i;
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len = len / sizeof(u32);
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for (i = 0; i < len; i++) {
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*mem = be32_to_cpu(*mem);
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mem++;
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}
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}
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@ -22,4 +22,8 @@ struct hinic_sge {
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u32 len;
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};
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void hinic_cpu_to_be32(void *data, int len);
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void hinic_be32_to_cpu(void *data, int len);
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#endif
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@ -0,0 +1,87 @@
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/*
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* Huawei HiNIC PCI Express Linux driver
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* Copyright(c) 2017 Huawei Technologies Co., Ltd
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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*/
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#include <linux/types.h>
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#include <linux/errno.h>
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#include "hinic_hw_if.h"
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#include "hinic_hw_cmdq.h"
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/**
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* hinic_alloc_cmdq_buf - alloc buffer for sending command
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* @cmdqs: the cmdqs
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* @cmdq_buf: the buffer returned in this struct
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*
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* Return 0 - Success, negative - Failure
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**/
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int hinic_alloc_cmdq_buf(struct hinic_cmdqs *cmdqs,
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struct hinic_cmdq_buf *cmdq_buf)
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{
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/* should be implemented */
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return -ENOMEM;
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}
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/**
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* hinic_free_cmdq_buf - free buffer
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* @cmdqs: the cmdqs
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* @cmdq_buf: the buffer to free that is in this struct
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**/
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void hinic_free_cmdq_buf(struct hinic_cmdqs *cmdqs,
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struct hinic_cmdq_buf *cmdq_buf)
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{
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/* should be implemented */
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}
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/**
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* hinic_cmdq_direct_resp - send command with direct data as resp
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* @cmdqs: the cmdqs
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* @mod: module on the card that will handle the command
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* @cmd: the command
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* @buf_in: the buffer for the command
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* @resp: the response to return
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*
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* Return 0 - Success, negative - Failure
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**/
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int hinic_cmdq_direct_resp(struct hinic_cmdqs *cmdqs,
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enum hinic_mod_type mod, u8 cmd,
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struct hinic_cmdq_buf *buf_in, u64 *resp)
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{
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/* should be implemented */
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return -EINVAL;
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}
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/**
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* hinic_init_cmdqs - init all cmdqs
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* @cmdqs: cmdqs to init
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* @hwif: HW interface for accessing cmdqs
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* @db_area: doorbell areas for all the cmdqs
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*
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* Return 0 - Success, negative - Failure
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**/
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int hinic_init_cmdqs(struct hinic_cmdqs *cmdqs, struct hinic_hwif *hwif,
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void __iomem **db_area)
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{
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/* should be implemented */
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return -EINVAL;
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}
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/**
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* hinic_free_cmdqs - free all cmdqs
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* @cmdqs: cmdqs to free
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**/
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void hinic_free_cmdqs(struct hinic_cmdqs *cmdqs)
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{
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/* should be implemented */
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}
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@ -0,0 +1,84 @@
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/*
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* Huawei HiNIC PCI Express Linux driver
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* Copyright(c) 2017 Huawei Technologies Co., Ltd
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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*/
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#ifndef HINIC_CMDQ_H
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#define HINIC_CMDQ_H
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#include <linux/types.h>
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#include <linux/spinlock.h>
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#include <linux/completion.h>
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#include <linux/pci.h>
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#include "hinic_hw_if.h"
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#include "hinic_hw_wq.h"
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#define HINIC_CMDQ_BUF_SIZE 2048
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enum hinic_cmdq_type {
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HINIC_CMDQ_SYNC,
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HINIC_MAX_CMDQ_TYPES,
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};
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struct hinic_cmdq_buf {
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void *buf;
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dma_addr_t dma_addr;
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size_t size;
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};
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struct hinic_cmdq {
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struct hinic_wq *wq;
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enum hinic_cmdq_type cmdq_type;
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int wrapped;
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/* Lock for keeping the doorbell order */
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spinlock_t cmdq_lock;
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struct completion **done;
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int **errcode;
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/* doorbell area */
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void __iomem *db_base;
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};
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struct hinic_cmdqs {
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struct hinic_hwif *hwif;
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struct pci_pool *cmdq_buf_pool;
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struct hinic_wq *saved_wqs;
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struct hinic_cmdq_pages cmdq_pages;
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struct hinic_cmdq cmdq[HINIC_MAX_CMDQ_TYPES];
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};
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int hinic_alloc_cmdq_buf(struct hinic_cmdqs *cmdqs,
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struct hinic_cmdq_buf *cmdq_buf);
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void hinic_free_cmdq_buf(struct hinic_cmdqs *cmdqs,
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struct hinic_cmdq_buf *cmdq_buf);
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int hinic_cmdq_direct_resp(struct hinic_cmdqs *cmdqs,
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enum hinic_mod_type mod, u8 cmd,
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struct hinic_cmdq_buf *buf_in, u64 *out_param);
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int hinic_init_cmdqs(struct hinic_cmdqs *cmdqs, struct hinic_hwif *hwif,
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void __iomem **db_area);
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void hinic_free_cmdqs(struct hinic_cmdqs *cmdqs);
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#endif
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@ -25,6 +25,7 @@
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#include "hinic_hw_if.h"
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#include "hinic_hw_eqs.h"
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#include "hinic_hw_mgmt.h"
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#include "hinic_hw_qp_ctxt.h"
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#include "hinic_hw_qp.h"
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#include "hinic_hw_io.h"
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#include "hinic_hw_dev.h"
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@ -76,6 +77,9 @@ static int get_capability(struct hinic_hwdev *hwdev,
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/* Each QP has its own (SQ + RQ) interrupts */
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nic_cap->num_qps = (num_irqs - (num_aeqs + num_ceqs)) / 2;
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if (nic_cap->num_qps > HINIC_Q_CTXT_MAX)
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nic_cap->num_qps = HINIC_Q_CTXT_MAX;
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/* num_qps must be power of 2 */
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nic_cap->num_qps = BIT(fls(nic_cap->num_qps) - 1);
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@ -27,6 +27,8 @@
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#include "hinic_hw_if.h"
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#include "hinic_hw_wqe.h"
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#include "hinic_hw_wq.h"
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#include "hinic_hw_cmdq.h"
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#include "hinic_hw_qp_ctxt.h"
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#include "hinic_hw_qp.h"
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#include "hinic_hw_io.h"
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@ -40,6 +42,10 @@
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#define DB_IDX(db, db_base) \
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(((unsigned long)(db) - (unsigned long)(db_base)) / HINIC_DB_PAGE_SIZE)
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enum io_cmd {
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IO_CMD_MODIFY_QUEUE_CTXT = 0,
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};
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static void init_db_area_idx(struct hinic_free_db_area *free_db_area)
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{
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int i;
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@ -100,6 +106,109 @@ static void return_db_area(struct hinic_func_to_io *func_to_io,
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up(&free_db_area->idx_lock);
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}
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static int write_sq_ctxts(struct hinic_func_to_io *func_to_io, u16 base_qpn,
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u16 num_sqs)
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{
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struct hinic_hwif *hwif = func_to_io->hwif;
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struct hinic_sq_ctxt_block *sq_ctxt_block;
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struct pci_dev *pdev = hwif->pdev;
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struct hinic_cmdq_buf cmdq_buf;
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struct hinic_sq_ctxt *sq_ctxt;
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struct hinic_qp *qp;
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u64 out_param;
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int err, i;
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err = hinic_alloc_cmdq_buf(&func_to_io->cmdqs, &cmdq_buf);
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if (err) {
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dev_err(&pdev->dev, "Failed to allocate cmdq buf\n");
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return err;
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}
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sq_ctxt_block = cmdq_buf.buf;
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sq_ctxt = sq_ctxt_block->sq_ctxt;
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hinic_qp_prepare_header(&sq_ctxt_block->hdr, HINIC_QP_CTXT_TYPE_SQ,
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num_sqs, func_to_io->max_qps);
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for (i = 0; i < num_sqs; i++) {
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qp = &func_to_io->qps[i];
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hinic_sq_prepare_ctxt(&sq_ctxt[i], &qp->sq,
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base_qpn + qp->q_id);
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}
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cmdq_buf.size = HINIC_SQ_CTXT_SIZE(num_sqs);
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err = hinic_cmdq_direct_resp(&func_to_io->cmdqs, HINIC_MOD_L2NIC,
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IO_CMD_MODIFY_QUEUE_CTXT, &cmdq_buf,
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&out_param);
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if ((err) || (out_param != 0)) {
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dev_err(&pdev->dev, "Failed to set SQ ctxts\n");
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err = -EFAULT;
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}
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hinic_free_cmdq_buf(&func_to_io->cmdqs, &cmdq_buf);
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return err;
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}
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static int write_rq_ctxts(struct hinic_func_to_io *func_to_io, u16 base_qpn,
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u16 num_rqs)
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{
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struct hinic_hwif *hwif = func_to_io->hwif;
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struct hinic_rq_ctxt_block *rq_ctxt_block;
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struct pci_dev *pdev = hwif->pdev;
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struct hinic_cmdq_buf cmdq_buf;
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struct hinic_rq_ctxt *rq_ctxt;
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struct hinic_qp *qp;
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u64 out_param;
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int err, i;
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err = hinic_alloc_cmdq_buf(&func_to_io->cmdqs, &cmdq_buf);
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if (err) {
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dev_err(&pdev->dev, "Failed to allocate cmdq buf\n");
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return err;
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}
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rq_ctxt_block = cmdq_buf.buf;
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rq_ctxt = rq_ctxt_block->rq_ctxt;
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hinic_qp_prepare_header(&rq_ctxt_block->hdr, HINIC_QP_CTXT_TYPE_RQ,
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num_rqs, func_to_io->max_qps);
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for (i = 0; i < num_rqs; i++) {
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qp = &func_to_io->qps[i];
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hinic_rq_prepare_ctxt(&rq_ctxt[i], &qp->rq,
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base_qpn + qp->q_id);
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}
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cmdq_buf.size = HINIC_RQ_CTXT_SIZE(num_rqs);
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err = hinic_cmdq_direct_resp(&func_to_io->cmdqs, HINIC_MOD_L2NIC,
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IO_CMD_MODIFY_QUEUE_CTXT, &cmdq_buf,
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&out_param);
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if ((err) || (out_param != 0)) {
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dev_err(&pdev->dev, "Failed to set RQ ctxts\n");
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err = -EFAULT;
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}
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hinic_free_cmdq_buf(&func_to_io->cmdqs, &cmdq_buf);
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return err;
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}
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/**
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* write_qp_ctxts - write the qp ctxt to HW
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* @func_to_io: func to io channel that holds the IO components
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* @base_qpn: first qp number
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* @num_qps: number of qps to write
|
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*
|
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* Return 0 - Success, negative - Failure
|
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**/
|
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static int write_qp_ctxts(struct hinic_func_to_io *func_to_io, u16 base_qpn,
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u16 num_qps)
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{
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return (write_sq_ctxts(func_to_io, base_qpn, num_qps) ||
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write_rq_ctxts(func_to_io, base_qpn, num_qps));
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}
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/**
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* init_qp - Initialize a Queue Pair
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* @func_to_io: func to io channel that holds the IO components
|
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|
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@ -265,8 +374,15 @@ int hinic_io_create_qps(struct hinic_func_to_io *func_to_io,
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}
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}
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err = write_qp_ctxts(func_to_io, base_qpn, num_qps);
|
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if (err) {
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dev_err(&pdev->dev, "Failed to init QP ctxts\n");
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goto err_write_qp_ctxts;
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}
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return 0;
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err_write_qp_ctxts:
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err_init_qp:
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for (j = 0; j < i; j++)
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destroy_qp(func_to_io, &func_to_io->qps[j]);
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@ -331,6 +447,8 @@ int hinic_io_init(struct hinic_func_to_io *func_to_io,
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struct msix_entry *ceq_msix_entries)
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{
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struct pci_dev *pdev = hwif->pdev;
|
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enum hinic_cmdq_type cmdq, type;
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void __iomem *db_area;
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int err;
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func_to_io->hwif = hwif;
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@ -351,8 +469,34 @@ int hinic_io_init(struct hinic_func_to_io *func_to_io,
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}
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init_db_area_idx(&func_to_io->free_db_area);
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|
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for (cmdq = HINIC_CMDQ_SYNC; cmdq < HINIC_MAX_CMDQ_TYPES; cmdq++) {
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db_area = get_db_area(func_to_io);
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if (IS_ERR(db_area)) {
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dev_err(&pdev->dev, "Failed to get cmdq db area\n");
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err = PTR_ERR(db_area);
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goto err_db_area;
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}
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func_to_io->cmdq_db_area[cmdq] = db_area;
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}
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|
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err = hinic_init_cmdqs(&func_to_io->cmdqs, hwif,
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func_to_io->cmdq_db_area);
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if (err) {
|
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dev_err(&pdev->dev, "Failed to initialize cmdqs\n");
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goto err_init_cmdqs;
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}
|
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|
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return 0;
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|
||||
err_init_cmdqs:
|
||||
err_db_area:
|
||||
for (type = HINIC_CMDQ_SYNC; type < cmdq; type++)
|
||||
return_db_area(func_to_io, func_to_io->cmdq_db_area[type]);
|
||||
|
||||
iounmap(func_to_io->db_base);
|
||||
|
||||
err_db_ioremap:
|
||||
hinic_wqs_free(&func_to_io->wqs);
|
||||
return err;
|
||||
|
|
@ -364,6 +508,13 @@ int hinic_io_init(struct hinic_func_to_io *func_to_io,
|
|||
**/
|
||||
void hinic_io_free(struct hinic_func_to_io *func_to_io)
|
||||
{
|
||||
enum hinic_cmdq_type cmdq;
|
||||
|
||||
hinic_free_cmdqs(&func_to_io->cmdqs);
|
||||
|
||||
for (cmdq = HINIC_CMDQ_SYNC; cmdq < HINIC_MAX_CMDQ_TYPES; cmdq++)
|
||||
return_db_area(func_to_io, func_to_io->cmdq_db_area[cmdq]);
|
||||
|
||||
iounmap(func_to_io->db_base);
|
||||
hinic_wqs_free(&func_to_io->wqs);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@
|
|||
|
||||
#include "hinic_hw_if.h"
|
||||
#include "hinic_hw_wq.h"
|
||||
#include "hinic_hw_cmdq.h"
|
||||
#include "hinic_hw_qp.h"
|
||||
|
||||
#define HINIC_DB_PAGE_SIZE SZ_4K
|
||||
|
|
@ -60,6 +61,10 @@ struct hinic_func_to_io {
|
|||
dma_addr_t ci_dma_base;
|
||||
|
||||
struct hinic_free_db_area free_db_area;
|
||||
|
||||
void __iomem *cmdq_db_area[HINIC_MAX_CMDQ_TYPES];
|
||||
|
||||
struct hinic_cmdqs cmdqs;
|
||||
};
|
||||
|
||||
int hinic_io_create_qps(struct hinic_func_to_io *func_to_io,
|
||||
|
|
|
|||
|
|
@ -21,13 +21,173 @@
|
|||
#include <linux/vmalloc.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <linux/atomic.h>
|
||||
#include <asm/byteorder.h>
|
||||
|
||||
#include "hinic_common.h"
|
||||
#include "hinic_hw_if.h"
|
||||
#include "hinic_hw_wq.h"
|
||||
#include "hinic_hw_qp_ctxt.h"
|
||||
#include "hinic_hw_qp.h"
|
||||
|
||||
#define SQ_DB_OFF SZ_2K
|
||||
|
||||
/* The number of cache line to prefetch Until threshold state */
|
||||
#define WQ_PREFETCH_MAX 2
|
||||
/* The number of cache line to prefetch After threshold state */
|
||||
#define WQ_PREFETCH_MIN 1
|
||||
/* Threshold state */
|
||||
#define WQ_PREFETCH_THRESHOLD 256
|
||||
|
||||
/* sizes of the SQ/RQ ctxt */
|
||||
#define Q_CTXT_SIZE 48
|
||||
#define CTXT_RSVD 240
|
||||
|
||||
#define SQ_CTXT_OFFSET(max_sqs, max_rqs, q_id) \
|
||||
(((max_rqs) + (max_sqs)) * CTXT_RSVD + (q_id) * Q_CTXT_SIZE)
|
||||
|
||||
#define RQ_CTXT_OFFSET(max_sqs, max_rqs, q_id) \
|
||||
(((max_rqs) + (max_sqs)) * CTXT_RSVD + \
|
||||
(max_sqs + (q_id)) * Q_CTXT_SIZE)
|
||||
|
||||
#define SIZE_16BYTES(size) (ALIGN(size, 16) >> 4)
|
||||
|
||||
void hinic_qp_prepare_header(struct hinic_qp_ctxt_header *qp_ctxt_hdr,
|
||||
enum hinic_qp_ctxt_type ctxt_type,
|
||||
u16 num_queues, u16 max_queues)
|
||||
{
|
||||
u16 max_sqs = max_queues;
|
||||
u16 max_rqs = max_queues;
|
||||
|
||||
qp_ctxt_hdr->num_queues = num_queues;
|
||||
qp_ctxt_hdr->queue_type = ctxt_type;
|
||||
|
||||
if (ctxt_type == HINIC_QP_CTXT_TYPE_SQ)
|
||||
qp_ctxt_hdr->addr_offset = SQ_CTXT_OFFSET(max_sqs, max_rqs, 0);
|
||||
else
|
||||
qp_ctxt_hdr->addr_offset = RQ_CTXT_OFFSET(max_sqs, max_rqs, 0);
|
||||
|
||||
qp_ctxt_hdr->addr_offset = SIZE_16BYTES(qp_ctxt_hdr->addr_offset);
|
||||
|
||||
hinic_cpu_to_be32(qp_ctxt_hdr, sizeof(*qp_ctxt_hdr));
|
||||
}
|
||||
|
||||
void hinic_sq_prepare_ctxt(struct hinic_sq_ctxt *sq_ctxt,
|
||||
struct hinic_sq *sq, u16 global_qid)
|
||||
{
|
||||
u32 wq_page_pfn_hi, wq_page_pfn_lo, wq_block_pfn_hi, wq_block_pfn_lo;
|
||||
u64 wq_page_addr, wq_page_pfn, wq_block_pfn;
|
||||
u16 pi_start, ci_start;
|
||||
struct hinic_wq *wq;
|
||||
|
||||
wq = sq->wq;
|
||||
ci_start = atomic_read(&wq->cons_idx);
|
||||
pi_start = atomic_read(&wq->prod_idx);
|
||||
|
||||
/* Read the first page paddr from the WQ page paddr ptrs */
|
||||
wq_page_addr = be64_to_cpu(*wq->block_vaddr);
|
||||
|
||||
wq_page_pfn = HINIC_WQ_PAGE_PFN(wq_page_addr);
|
||||
wq_page_pfn_hi = upper_32_bits(wq_page_pfn);
|
||||
wq_page_pfn_lo = lower_32_bits(wq_page_pfn);
|
||||
|
||||
wq_block_pfn = HINIC_WQ_BLOCK_PFN(wq->block_paddr);
|
||||
wq_block_pfn_hi = upper_32_bits(wq_block_pfn);
|
||||
wq_block_pfn_lo = lower_32_bits(wq_block_pfn);
|
||||
|
||||
sq_ctxt->ceq_attr = HINIC_SQ_CTXT_CEQ_ATTR_SET(global_qid,
|
||||
GLOBAL_SQ_ID) |
|
||||
HINIC_SQ_CTXT_CEQ_ATTR_SET(0, EN);
|
||||
|
||||
sq_ctxt->ci_wrapped = HINIC_SQ_CTXT_CI_SET(ci_start, IDX) |
|
||||
HINIC_SQ_CTXT_CI_SET(1, WRAPPED);
|
||||
|
||||
sq_ctxt->wq_hi_pfn_pi =
|
||||
HINIC_SQ_CTXT_WQ_PAGE_SET(wq_page_pfn_hi, HI_PFN) |
|
||||
HINIC_SQ_CTXT_WQ_PAGE_SET(pi_start, PI);
|
||||
|
||||
sq_ctxt->wq_lo_pfn = wq_page_pfn_lo;
|
||||
|
||||
sq_ctxt->pref_cache =
|
||||
HINIC_SQ_CTXT_PREF_SET(WQ_PREFETCH_MIN, CACHE_MIN) |
|
||||
HINIC_SQ_CTXT_PREF_SET(WQ_PREFETCH_MAX, CACHE_MAX) |
|
||||
HINIC_SQ_CTXT_PREF_SET(WQ_PREFETCH_THRESHOLD, CACHE_THRESHOLD);
|
||||
|
||||
sq_ctxt->pref_wrapped = 1;
|
||||
|
||||
sq_ctxt->pref_wq_hi_pfn_ci =
|
||||
HINIC_SQ_CTXT_PREF_SET(ci_start, CI) |
|
||||
HINIC_SQ_CTXT_PREF_SET(wq_page_pfn_hi, WQ_HI_PFN);
|
||||
|
||||
sq_ctxt->pref_wq_lo_pfn = wq_page_pfn_lo;
|
||||
|
||||
sq_ctxt->wq_block_hi_pfn =
|
||||
HINIC_SQ_CTXT_WQ_BLOCK_SET(wq_block_pfn_hi, HI_PFN);
|
||||
|
||||
sq_ctxt->wq_block_lo_pfn = wq_block_pfn_lo;
|
||||
|
||||
hinic_cpu_to_be32(sq_ctxt, sizeof(*sq_ctxt));
|
||||
}
|
||||
|
||||
void hinic_rq_prepare_ctxt(struct hinic_rq_ctxt *rq_ctxt,
|
||||
struct hinic_rq *rq, u16 global_qid)
|
||||
{
|
||||
u32 wq_page_pfn_hi, wq_page_pfn_lo, wq_block_pfn_hi, wq_block_pfn_lo;
|
||||
u64 wq_page_addr, wq_page_pfn, wq_block_pfn;
|
||||
u16 pi_start, ci_start;
|
||||
struct hinic_wq *wq;
|
||||
|
||||
wq = rq->wq;
|
||||
ci_start = atomic_read(&wq->cons_idx);
|
||||
pi_start = atomic_read(&wq->prod_idx);
|
||||
|
||||
/* Read the first page paddr from the WQ page paddr ptrs */
|
||||
wq_page_addr = be64_to_cpu(*wq->block_vaddr);
|
||||
|
||||
wq_page_pfn = HINIC_WQ_PAGE_PFN(wq_page_addr);
|
||||
wq_page_pfn_hi = upper_32_bits(wq_page_pfn);
|
||||
wq_page_pfn_lo = lower_32_bits(wq_page_pfn);
|
||||
|
||||
wq_block_pfn = HINIC_WQ_BLOCK_PFN(wq->block_paddr);
|
||||
wq_block_pfn_hi = upper_32_bits(wq_block_pfn);
|
||||
wq_block_pfn_lo = lower_32_bits(wq_block_pfn);
|
||||
|
||||
rq_ctxt->ceq_attr = HINIC_RQ_CTXT_CEQ_ATTR_SET(0, EN) |
|
||||
HINIC_RQ_CTXT_CEQ_ATTR_SET(1, WRAPPED);
|
||||
|
||||
rq_ctxt->pi_intr_attr = HINIC_RQ_CTXT_PI_SET(pi_start, IDX) |
|
||||
HINIC_RQ_CTXT_PI_SET(rq->msix_entry, INTR);
|
||||
|
||||
rq_ctxt->wq_hi_pfn_ci = HINIC_RQ_CTXT_WQ_PAGE_SET(wq_page_pfn_hi,
|
||||
HI_PFN) |
|
||||
HINIC_RQ_CTXT_WQ_PAGE_SET(ci_start, CI);
|
||||
|
||||
rq_ctxt->wq_lo_pfn = wq_page_pfn_lo;
|
||||
|
||||
rq_ctxt->pref_cache =
|
||||
HINIC_RQ_CTXT_PREF_SET(WQ_PREFETCH_MIN, CACHE_MIN) |
|
||||
HINIC_RQ_CTXT_PREF_SET(WQ_PREFETCH_MAX, CACHE_MAX) |
|
||||
HINIC_RQ_CTXT_PREF_SET(WQ_PREFETCH_THRESHOLD, CACHE_THRESHOLD);
|
||||
|
||||
rq_ctxt->pref_wrapped = 1;
|
||||
|
||||
rq_ctxt->pref_wq_hi_pfn_ci =
|
||||
HINIC_RQ_CTXT_PREF_SET(wq_page_pfn_hi, WQ_HI_PFN) |
|
||||
HINIC_RQ_CTXT_PREF_SET(ci_start, CI);
|
||||
|
||||
rq_ctxt->pref_wq_lo_pfn = wq_page_pfn_lo;
|
||||
|
||||
rq_ctxt->pi_paddr_hi = upper_32_bits(rq->pi_dma_addr);
|
||||
rq_ctxt->pi_paddr_lo = lower_32_bits(rq->pi_dma_addr);
|
||||
|
||||
rq_ctxt->wq_block_hi_pfn =
|
||||
HINIC_RQ_CTXT_WQ_BLOCK_SET(wq_block_pfn_hi, HI_PFN);
|
||||
|
||||
rq_ctxt->wq_block_lo_pfn = wq_block_pfn_lo;
|
||||
|
||||
hinic_cpu_to_be32(rq_ctxt, sizeof(*rq_ctxt));
|
||||
}
|
||||
|
||||
/**
|
||||
* alloc_sq_skb_arr - allocate sq array for saved skb
|
||||
* @sq: HW Send Queue
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@
|
|||
#include "hinic_hw_if.h"
|
||||
#include "hinic_hw_wqe.h"
|
||||
#include "hinic_hw_wq.h"
|
||||
#include "hinic_hw_qp_ctxt.h"
|
||||
|
||||
#define HINIC_SQ_WQEBB_SIZE 64
|
||||
#define HINIC_RQ_WQEBB_SIZE 32
|
||||
|
|
@ -78,6 +79,16 @@ struct hinic_qp {
|
|||
u16 q_id;
|
||||
};
|
||||
|
||||
void hinic_qp_prepare_header(struct hinic_qp_ctxt_header *qp_ctxt_hdr,
|
||||
enum hinic_qp_ctxt_type ctxt_type,
|
||||
u16 num_queues, u16 max_queues);
|
||||
|
||||
void hinic_sq_prepare_ctxt(struct hinic_sq_ctxt *sq_ctxt,
|
||||
struct hinic_sq *sq, u16 global_qid);
|
||||
|
||||
void hinic_rq_prepare_ctxt(struct hinic_rq_ctxt *rq_ctxt,
|
||||
struct hinic_rq *rq, u16 global_qid);
|
||||
|
||||
int hinic_init_sq(struct hinic_sq *sq, struct hinic_hwif *hwif,
|
||||
struct hinic_wq *wq, struct msix_entry *entry, void *ci_addr,
|
||||
dma_addr_t ci_dma_addr, void __iomem *db_base);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,214 @@
|
|||
/*
|
||||
* Huawei HiNIC PCI Express Linux driver
|
||||
* Copyright(c) 2017 Huawei Technologies Co., Ltd
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef HINIC_HW_QP_CTXT_H
|
||||
#define HINIC_HW_QP_CTXT_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
#include "hinic_hw_cmdq.h"
|
||||
|
||||
#define HINIC_SQ_CTXT_CEQ_ATTR_GLOBAL_SQ_ID_SHIFT 13
|
||||
#define HINIC_SQ_CTXT_CEQ_ATTR_EN_SHIFT 23
|
||||
|
||||
#define HINIC_SQ_CTXT_CEQ_ATTR_GLOBAL_SQ_ID_MASK 0x3FF
|
||||
#define HINIC_SQ_CTXT_CEQ_ATTR_EN_MASK 0x1
|
||||
|
||||
#define HINIC_SQ_CTXT_CEQ_ATTR_SET(val, member) \
|
||||
(((u32)(val) & HINIC_SQ_CTXT_CEQ_ATTR_##member##_MASK) \
|
||||
<< HINIC_SQ_CTXT_CEQ_ATTR_##member##_SHIFT)
|
||||
|
||||
#define HINIC_SQ_CTXT_CI_IDX_SHIFT 11
|
||||
#define HINIC_SQ_CTXT_CI_WRAPPED_SHIFT 23
|
||||
|
||||
#define HINIC_SQ_CTXT_CI_IDX_MASK 0xFFF
|
||||
#define HINIC_SQ_CTXT_CI_WRAPPED_MASK 0x1
|
||||
|
||||
#define HINIC_SQ_CTXT_CI_SET(val, member) \
|
||||
(((u32)(val) & HINIC_SQ_CTXT_CI_##member##_MASK) \
|
||||
<< HINIC_SQ_CTXT_CI_##member##_SHIFT)
|
||||
|
||||
#define HINIC_SQ_CTXT_WQ_PAGE_HI_PFN_SHIFT 0
|
||||
#define HINIC_SQ_CTXT_WQ_PAGE_PI_SHIFT 20
|
||||
|
||||
#define HINIC_SQ_CTXT_WQ_PAGE_HI_PFN_MASK 0xFFFFF
|
||||
#define HINIC_SQ_CTXT_WQ_PAGE_PI_MASK 0xFFF
|
||||
|
||||
#define HINIC_SQ_CTXT_WQ_PAGE_SET(val, member) \
|
||||
(((u32)(val) & HINIC_SQ_CTXT_WQ_PAGE_##member##_MASK) \
|
||||
<< HINIC_SQ_CTXT_WQ_PAGE_##member##_SHIFT)
|
||||
|
||||
#define HINIC_SQ_CTXT_PREF_CACHE_THRESHOLD_SHIFT 0
|
||||
#define HINIC_SQ_CTXT_PREF_CACHE_MAX_SHIFT 14
|
||||
#define HINIC_SQ_CTXT_PREF_CACHE_MIN_SHIFT 25
|
||||
|
||||
#define HINIC_SQ_CTXT_PREF_CACHE_THRESHOLD_MASK 0x3FFF
|
||||
#define HINIC_SQ_CTXT_PREF_CACHE_MAX_MASK 0x7FF
|
||||
#define HINIC_SQ_CTXT_PREF_CACHE_MIN_MASK 0x7F
|
||||
|
||||
#define HINIC_SQ_CTXT_PREF_WQ_HI_PFN_SHIFT 0
|
||||
#define HINIC_SQ_CTXT_PREF_CI_SHIFT 20
|
||||
|
||||
#define HINIC_SQ_CTXT_PREF_WQ_HI_PFN_MASK 0xFFFFF
|
||||
#define HINIC_SQ_CTXT_PREF_CI_MASK 0xFFF
|
||||
|
||||
#define HINIC_SQ_CTXT_PREF_SET(val, member) \
|
||||
(((u32)(val) & HINIC_SQ_CTXT_PREF_##member##_MASK) \
|
||||
<< HINIC_SQ_CTXT_PREF_##member##_SHIFT)
|
||||
|
||||
#define HINIC_SQ_CTXT_WQ_BLOCK_HI_PFN_SHIFT 0
|
||||
|
||||
#define HINIC_SQ_CTXT_WQ_BLOCK_HI_PFN_MASK 0x7FFFFF
|
||||
|
||||
#define HINIC_SQ_CTXT_WQ_BLOCK_SET(val, member) \
|
||||
(((u32)(val) & HINIC_SQ_CTXT_WQ_BLOCK_##member##_MASK) \
|
||||
<< HINIC_SQ_CTXT_WQ_BLOCK_##member##_SHIFT)
|
||||
|
||||
#define HINIC_RQ_CTXT_CEQ_ATTR_EN_SHIFT 0
|
||||
#define HINIC_RQ_CTXT_CEQ_ATTR_WRAPPED_SHIFT 1
|
||||
|
||||
#define HINIC_RQ_CTXT_CEQ_ATTR_EN_MASK 0x1
|
||||
#define HINIC_RQ_CTXT_CEQ_ATTR_WRAPPED_MASK 0x1
|
||||
|
||||
#define HINIC_RQ_CTXT_CEQ_ATTR_SET(val, member) \
|
||||
(((u32)(val) & HINIC_RQ_CTXT_CEQ_ATTR_##member##_MASK) \
|
||||
<< HINIC_RQ_CTXT_CEQ_ATTR_##member##_SHIFT)
|
||||
|
||||
#define HINIC_RQ_CTXT_PI_IDX_SHIFT 0
|
||||
#define HINIC_RQ_CTXT_PI_INTR_SHIFT 22
|
||||
|
||||
#define HINIC_RQ_CTXT_PI_IDX_MASK 0xFFF
|
||||
#define HINIC_RQ_CTXT_PI_INTR_MASK 0x3FF
|
||||
|
||||
#define HINIC_RQ_CTXT_PI_SET(val, member) \
|
||||
(((u32)(val) & HINIC_RQ_CTXT_PI_##member##_MASK) << \
|
||||
HINIC_RQ_CTXT_PI_##member##_SHIFT)
|
||||
|
||||
#define HINIC_RQ_CTXT_WQ_PAGE_HI_PFN_SHIFT 0
|
||||
#define HINIC_RQ_CTXT_WQ_PAGE_CI_SHIFT 20
|
||||
|
||||
#define HINIC_RQ_CTXT_WQ_PAGE_HI_PFN_MASK 0xFFFFF
|
||||
#define HINIC_RQ_CTXT_WQ_PAGE_CI_MASK 0xFFF
|
||||
|
||||
#define HINIC_RQ_CTXT_WQ_PAGE_SET(val, member) \
|
||||
(((u32)(val) & HINIC_RQ_CTXT_WQ_PAGE_##member##_MASK) << \
|
||||
HINIC_RQ_CTXT_WQ_PAGE_##member##_SHIFT)
|
||||
|
||||
#define HINIC_RQ_CTXT_PREF_CACHE_THRESHOLD_SHIFT 0
|
||||
#define HINIC_RQ_CTXT_PREF_CACHE_MAX_SHIFT 14
|
||||
#define HINIC_RQ_CTXT_PREF_CACHE_MIN_SHIFT 25
|
||||
|
||||
#define HINIC_RQ_CTXT_PREF_CACHE_THRESHOLD_MASK 0x3FFF
|
||||
#define HINIC_RQ_CTXT_PREF_CACHE_MAX_MASK 0x7FF
|
||||
#define HINIC_RQ_CTXT_PREF_CACHE_MIN_MASK 0x7F
|
||||
|
||||
#define HINIC_RQ_CTXT_PREF_WQ_HI_PFN_SHIFT 0
|
||||
#define HINIC_RQ_CTXT_PREF_CI_SHIFT 20
|
||||
|
||||
#define HINIC_RQ_CTXT_PREF_WQ_HI_PFN_MASK 0xFFFFF
|
||||
#define HINIC_RQ_CTXT_PREF_CI_MASK 0xFFF
|
||||
|
||||
#define HINIC_RQ_CTXT_PREF_SET(val, member) \
|
||||
(((u32)(val) & HINIC_RQ_CTXT_PREF_##member##_MASK) << \
|
||||
HINIC_RQ_CTXT_PREF_##member##_SHIFT)
|
||||
|
||||
#define HINIC_RQ_CTXT_WQ_BLOCK_HI_PFN_SHIFT 0
|
||||
|
||||
#define HINIC_RQ_CTXT_WQ_BLOCK_HI_PFN_MASK 0x7FFFFF
|
||||
|
||||
#define HINIC_RQ_CTXT_WQ_BLOCK_SET(val, member) \
|
||||
(((u32)(val) & HINIC_RQ_CTXT_WQ_BLOCK_##member##_MASK) << \
|
||||
HINIC_RQ_CTXT_WQ_BLOCK_##member##_SHIFT)
|
||||
|
||||
#define HINIC_SQ_CTXT_SIZE(num_sqs) (sizeof(struct hinic_qp_ctxt_header) \
|
||||
+ (num_sqs) * sizeof(struct hinic_sq_ctxt))
|
||||
|
||||
#define HINIC_RQ_CTXT_SIZE(num_rqs) (sizeof(struct hinic_qp_ctxt_header) \
|
||||
+ (num_rqs) * sizeof(struct hinic_rq_ctxt))
|
||||
|
||||
#define HINIC_WQ_PAGE_PFN_SHIFT 12
|
||||
#define HINIC_WQ_BLOCK_PFN_SHIFT 9
|
||||
|
||||
#define HINIC_WQ_PAGE_PFN(page_addr) ((page_addr) >> HINIC_WQ_PAGE_PFN_SHIFT)
|
||||
#define HINIC_WQ_BLOCK_PFN(page_addr) ((page_addr) >> \
|
||||
HINIC_WQ_BLOCK_PFN_SHIFT)
|
||||
|
||||
#define HINIC_Q_CTXT_MAX \
|
||||
((HINIC_CMDQ_BUF_SIZE - sizeof(struct hinic_qp_ctxt_header)) \
|
||||
/ sizeof(struct hinic_sq_ctxt))
|
||||
|
||||
enum hinic_qp_ctxt_type {
|
||||
HINIC_QP_CTXT_TYPE_SQ,
|
||||
HINIC_QP_CTXT_TYPE_RQ
|
||||
};
|
||||
|
||||
struct hinic_qp_ctxt_header {
|
||||
u16 num_queues;
|
||||
u16 queue_type;
|
||||
u32 addr_offset;
|
||||
};
|
||||
|
||||
struct hinic_sq_ctxt {
|
||||
u32 ceq_attr;
|
||||
|
||||
u32 ci_wrapped;
|
||||
|
||||
u32 wq_hi_pfn_pi;
|
||||
u32 wq_lo_pfn;
|
||||
|
||||
u32 pref_cache;
|
||||
u32 pref_wrapped;
|
||||
u32 pref_wq_hi_pfn_ci;
|
||||
u32 pref_wq_lo_pfn;
|
||||
|
||||
u32 rsvd0;
|
||||
u32 rsvd1;
|
||||
|
||||
u32 wq_block_hi_pfn;
|
||||
u32 wq_block_lo_pfn;
|
||||
};
|
||||
|
||||
struct hinic_rq_ctxt {
|
||||
u32 ceq_attr;
|
||||
|
||||
u32 pi_intr_attr;
|
||||
|
||||
u32 wq_hi_pfn_ci;
|
||||
u32 wq_lo_pfn;
|
||||
|
||||
u32 pref_cache;
|
||||
u32 pref_wrapped;
|
||||
|
||||
u32 pref_wq_hi_pfn_ci;
|
||||
u32 pref_wq_lo_pfn;
|
||||
|
||||
u32 pi_paddr_hi;
|
||||
u32 pi_paddr_lo;
|
||||
|
||||
u32 wq_block_hi_pfn;
|
||||
u32 wq_block_lo_pfn;
|
||||
};
|
||||
|
||||
struct hinic_sq_ctxt_block {
|
||||
struct hinic_qp_ctxt_header hdr;
|
||||
struct hinic_sq_ctxt sq_ctxt[HINIC_Q_CTXT_MAX];
|
||||
};
|
||||
|
||||
struct hinic_rq_ctxt_block {
|
||||
struct hinic_qp_ctxt_header hdr;
|
||||
struct hinic_rq_ctxt rq_ctxt[HINIC_Q_CTXT_MAX];
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -72,6 +72,15 @@ struct hinic_wqs {
|
|||
struct semaphore alloc_blocks_lock;
|
||||
};
|
||||
|
||||
struct hinic_cmdq_pages {
|
||||
/* The addresses are 64 bit in the HW */
|
||||
u64 page_paddr;
|
||||
u64 *page_vaddr;
|
||||
void **shadow_page_vaddr;
|
||||
|
||||
struct hinic_hwif *hwif;
|
||||
};
|
||||
|
||||
int hinic_wqs_alloc(struct hinic_wqs *wqs, int num_wqs,
|
||||
struct hinic_hwif *hwif);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue