mirror of https://gitee.com/openkylin/linux.git
drm/nouveau/secboot: add gp102/gp104/gp106/gp107 support
These gp10x chips are supporting using (roughly) the same firmware. Compared to previous secure chips, ACR runs on SEC2 and so does the low-secure msgqueue. ACR for these chips is based on r367. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Alexandre Courbot
Ben Skeggs
parent
84074e5b10
commit
5429f82f34
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@ -59,5 +59,6 @@ int nvkm_secboot_reset(struct nvkm_secboot *, enum nvkm_secboot_falcon);
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int gm200_secboot_new(struct nvkm_device *, int, struct nvkm_secboot **);
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int gm20b_secboot_new(struct nvkm_device *, int, struct nvkm_secboot **);
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int gp102_secboot_new(struct nvkm_device *, int, struct nvkm_secboot **);
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#endif
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@ -10,3 +10,4 @@ nvkm-y += nvkm/subdev/secboot/acr_r367.o
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nvkm-y += nvkm/subdev/secboot/acr_r375.o
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nvkm-y += nvkm/subdev/secboot/gm200.o
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nvkm-y += nvkm/subdev/secboot/gm20b.o
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nvkm-y += nvkm/subdev/secboot/gp102.o
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@ -0,0 +1,251 @@
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/*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "acr.h"
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#include "gm200.h"
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#include "ls_ucode.h"
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#include "hs_ucode.h"
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#include <subdev/mc.h>
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#include <subdev/timer.h>
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#include <engine/falcon.h>
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#include <engine/nvdec.h>
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static bool
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gp102_secboot_scrub_required(struct nvkm_secboot *sb)
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{
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struct nvkm_subdev *subdev = &sb->subdev;
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struct nvkm_device *device = subdev->device;
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u32 reg;
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nvkm_wr32(device, 0x100cd0, 0x2);
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reg = nvkm_rd32(device, 0x100cd0);
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return (reg & BIT(4));
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}
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static int
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gp102_run_secure_scrub(struct nvkm_secboot *sb)
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{
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struct nvkm_subdev *subdev = &sb->subdev;
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struct nvkm_device *device = subdev->device;
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struct nvkm_engine *engine;
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struct nvkm_falcon *falcon;
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void *scrub_image;
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struct fw_bin_header *hsbin_hdr;
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struct hsf_fw_header *fw_hdr;
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struct hsf_load_header *lhdr;
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void *scrub_data;
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int ret;
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nvkm_debug(subdev, "running VPR scrubber binary on NVDEC...\n");
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if (!(engine = nvkm_engine_ref(&device->nvdec->engine)))
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return PTR_ERR(engine);
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falcon = device->nvdec->falcon;
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nvkm_falcon_get(falcon, &sb->subdev);
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scrub_image = hs_ucode_load_blob(subdev, falcon, "nvdec/scrubber");
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if (IS_ERR(scrub_image))
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return PTR_ERR(scrub_image);
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nvkm_falcon_reset(falcon);
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nvkm_falcon_bind_context(falcon, NULL);
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hsbin_hdr = scrub_image;
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fw_hdr = scrub_image + hsbin_hdr->header_offset;
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lhdr = scrub_image + fw_hdr->hdr_offset;
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scrub_data = scrub_image + hsbin_hdr->data_offset;
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nvkm_falcon_load_imem(falcon, scrub_data, lhdr->non_sec_code_off,
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lhdr->non_sec_code_size,
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lhdr->non_sec_code_off >> 8, 0, false);
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nvkm_falcon_load_imem(falcon, scrub_data + lhdr->apps[0],
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ALIGN(lhdr->apps[0], 0x100),
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lhdr->apps[1],
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lhdr->apps[0] >> 8, 0, true);
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nvkm_falcon_load_dmem(falcon, scrub_data + lhdr->data_dma_base, 0,
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lhdr->data_size, 0);
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kfree(scrub_image);
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nvkm_falcon_set_start_addr(falcon, 0x0);
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nvkm_falcon_start(falcon);
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ret = nvkm_falcon_wait_for_halt(falcon, 500);
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if (ret < 0) {
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nvkm_error(subdev, "failed to run VPR scrubber binary!\n");
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ret = -ETIMEDOUT;
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goto end;
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}
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/* put nvdec in clean state - without reset it will remain in HS mode */
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nvkm_falcon_reset(falcon);
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if (gp102_secboot_scrub_required(sb)) {
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nvkm_error(subdev, "VPR scrubber binary failed!\n");
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ret = -EINVAL;
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goto end;
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}
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nvkm_debug(subdev, "VPR scrub successfully completed\n");
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end:
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nvkm_falcon_put(falcon, &sb->subdev);
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nvkm_engine_unref(&engine);
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return ret;
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}
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static int
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gp102_secboot_run_blob(struct nvkm_secboot *sb, struct nvkm_gpuobj *blob,
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struct nvkm_falcon *falcon)
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{
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int ret;
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/* make sure the VPR region is unlocked */
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if (gp102_secboot_scrub_required(sb)) {
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ret = gp102_run_secure_scrub(sb);
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if (ret)
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return ret;
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}
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return gm200_secboot_run_blob(sb, blob, falcon);
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}
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static const struct nvkm_secboot_func
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gp102_secboot = {
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.dtor = gm200_secboot_dtor,
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.oneinit = gm200_secboot_oneinit,
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.fini = gm200_secboot_fini,
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.run_blob = gp102_secboot_run_blob,
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};
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int
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gp102_secboot_new(struct nvkm_device *device, int index,
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struct nvkm_secboot **psb)
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{
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int ret;
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struct gm200_secboot *gsb;
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struct nvkm_acr *acr;
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acr = acr_r367_new(NVKM_SECBOOT_FALCON_SEC2,
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BIT(NVKM_SECBOOT_FALCON_FECS) |
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BIT(NVKM_SECBOOT_FALCON_GPCCS) |
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BIT(NVKM_SECBOOT_FALCON_SEC2));
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if (IS_ERR(acr))
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return PTR_ERR(acr);
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gsb = kzalloc(sizeof(*gsb), GFP_KERNEL);
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if (!gsb) {
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psb = NULL;
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return -ENOMEM;
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}
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*psb = &gsb->base;
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ret = nvkm_secboot_ctor(&gp102_secboot, acr, device, index, &gsb->base);
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if (ret)
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return ret;
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return 0;
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}
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MODULE_FIRMWARE("nvidia/gp102/acr/bl.bin");
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MODULE_FIRMWARE("nvidia/gp102/acr/unload_bl.bin");
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MODULE_FIRMWARE("nvidia/gp102/acr/ucode_load.bin");
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MODULE_FIRMWARE("nvidia/gp102/acr/ucode_unload.bin");
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MODULE_FIRMWARE("nvidia/gp102/gr/fecs_bl.bin");
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MODULE_FIRMWARE("nvidia/gp102/gr/fecs_inst.bin");
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MODULE_FIRMWARE("nvidia/gp102/gr/fecs_data.bin");
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MODULE_FIRMWARE("nvidia/gp102/gr/fecs_sig.bin");
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MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_bl.bin");
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MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_inst.bin");
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MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_data.bin");
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MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_sig.bin");
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MODULE_FIRMWARE("nvidia/gp102/gr/sw_ctx.bin");
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MODULE_FIRMWARE("nvidia/gp102/gr/sw_nonctx.bin");
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MODULE_FIRMWARE("nvidia/gp102/gr/sw_bundle_init.bin");
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MODULE_FIRMWARE("nvidia/gp102/gr/sw_method_init.bin");
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MODULE_FIRMWARE("nvidia/gp102/nvdec/scrubber.bin");
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MODULE_FIRMWARE("nvidia/gp102/sec2/desc.bin");
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MODULE_FIRMWARE("nvidia/gp102/sec2/image.bin");
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MODULE_FIRMWARE("nvidia/gp102/sec2/sig.bin");
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MODULE_FIRMWARE("nvidia/gp104/acr/bl.bin");
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MODULE_FIRMWARE("nvidia/gp104/acr/unload_bl.bin");
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MODULE_FIRMWARE("nvidia/gp104/acr/ucode_load.bin");
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MODULE_FIRMWARE("nvidia/gp104/acr/ucode_unload.bin");
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MODULE_FIRMWARE("nvidia/gp104/gr/fecs_bl.bin");
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MODULE_FIRMWARE("nvidia/gp104/gr/fecs_inst.bin");
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MODULE_FIRMWARE("nvidia/gp104/gr/fecs_data.bin");
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MODULE_FIRMWARE("nvidia/gp104/gr/fecs_sig.bin");
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MODULE_FIRMWARE("nvidia/gp104/gr/gpccs_bl.bin");
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MODULE_FIRMWARE("nvidia/gp104/gr/gpccs_inst.bin");
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MODULE_FIRMWARE("nvidia/gp104/gr/gpccs_data.bin");
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MODULE_FIRMWARE("nvidia/gp104/gr/gpccs_sig.bin");
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MODULE_FIRMWARE("nvidia/gp104/gr/sw_ctx.bin");
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MODULE_FIRMWARE("nvidia/gp104/gr/sw_nonctx.bin");
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MODULE_FIRMWARE("nvidia/gp104/gr/sw_bundle_init.bin");
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MODULE_FIRMWARE("nvidia/gp104/gr/sw_method_init.bin");
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MODULE_FIRMWARE("nvidia/gp104/nvdec/scrubber.bin");
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MODULE_FIRMWARE("nvidia/gp104/sec2/desc.bin");
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MODULE_FIRMWARE("nvidia/gp104/sec2/image.bin");
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MODULE_FIRMWARE("nvidia/gp104/sec2/sig.bin");
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MODULE_FIRMWARE("nvidia/gp106/acr/bl.bin");
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MODULE_FIRMWARE("nvidia/gp106/acr/unload_bl.bin");
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MODULE_FIRMWARE("nvidia/gp106/acr/ucode_load.bin");
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MODULE_FIRMWARE("nvidia/gp106/acr/ucode_unload.bin");
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MODULE_FIRMWARE("nvidia/gp106/gr/fecs_bl.bin");
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MODULE_FIRMWARE("nvidia/gp106/gr/fecs_inst.bin");
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MODULE_FIRMWARE("nvidia/gp106/gr/fecs_data.bin");
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MODULE_FIRMWARE("nvidia/gp106/gr/fecs_sig.bin");
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MODULE_FIRMWARE("nvidia/gp106/gr/gpccs_bl.bin");
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MODULE_FIRMWARE("nvidia/gp106/gr/gpccs_inst.bin");
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MODULE_FIRMWARE("nvidia/gp106/gr/gpccs_data.bin");
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MODULE_FIRMWARE("nvidia/gp106/gr/gpccs_sig.bin");
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MODULE_FIRMWARE("nvidia/gp106/gr/sw_ctx.bin");
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MODULE_FIRMWARE("nvidia/gp106/gr/sw_nonctx.bin");
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MODULE_FIRMWARE("nvidia/gp106/gr/sw_bundle_init.bin");
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MODULE_FIRMWARE("nvidia/gp106/gr/sw_method_init.bin");
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MODULE_FIRMWARE("nvidia/gp106/nvdec/scrubber.bin");
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MODULE_FIRMWARE("nvidia/gp106/sec2/desc.bin");
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MODULE_FIRMWARE("nvidia/gp106/sec2/image.bin");
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MODULE_FIRMWARE("nvidia/gp106/sec2/sig.bin");
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MODULE_FIRMWARE("nvidia/gp107/acr/bl.bin");
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MODULE_FIRMWARE("nvidia/gp107/acr/unload_bl.bin");
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MODULE_FIRMWARE("nvidia/gp107/acr/ucode_load.bin");
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MODULE_FIRMWARE("nvidia/gp107/acr/ucode_unload.bin");
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MODULE_FIRMWARE("nvidia/gp107/gr/fecs_bl.bin");
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MODULE_FIRMWARE("nvidia/gp107/gr/fecs_inst.bin");
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MODULE_FIRMWARE("nvidia/gp107/gr/fecs_data.bin");
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MODULE_FIRMWARE("nvidia/gp107/gr/fecs_sig.bin");
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MODULE_FIRMWARE("nvidia/gp107/gr/gpccs_bl.bin");
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MODULE_FIRMWARE("nvidia/gp107/gr/gpccs_inst.bin");
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MODULE_FIRMWARE("nvidia/gp107/gr/gpccs_data.bin");
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MODULE_FIRMWARE("nvidia/gp107/gr/gpccs_sig.bin");
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MODULE_FIRMWARE("nvidia/gp107/gr/sw_ctx.bin");
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MODULE_FIRMWARE("nvidia/gp107/gr/sw_nonctx.bin");
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MODULE_FIRMWARE("nvidia/gp107/gr/sw_bundle_init.bin");
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MODULE_FIRMWARE("nvidia/gp107/gr/sw_method_init.bin");
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MODULE_FIRMWARE("nvidia/gp107/nvdec/scrubber.bin");
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MODULE_FIRMWARE("nvidia/gp107/sec2/desc.bin");
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MODULE_FIRMWARE("nvidia/gp107/sec2/image.bin");
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MODULE_FIRMWARE("nvidia/gp107/sec2/sig.bin");
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