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mmc: omap: clarify DDR timing mode between SD-UHS and eMMC 

Replaced UHS_DDR50 with MMC_DDR52.

Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>
Acked-by: Balaji T K <balajitk@ti.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Chris Ball <chris@printf.net>
This commit is contained in:
Seungwon Jeon 2014-03-14 21:12:27 +09:00 committed by Chris Ball
parent 6dad6c9594
commit 5438ad95a5
1 changed files with 2 additions and 2 deletions
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4
drivers/mmc/host/omap_hsmmc.c
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@ -582,7 +582,7 @@ static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
* - MMC/SD clock coming out of controller > 25MHz * - MMC/SD clock coming out of controller > 25MHz
*/ */
if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) && if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) &&
(ios->timing != MMC_TIMING_UHS_DDR50) && (ios->timing != MMC_TIMING_MMC_DDR52) &&
((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
regval = OMAP_HSMMC_READ(host->base, HCTL); regval = OMAP_HSMMC_READ(host->base, HCTL);
if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
@ -602,7 +602,7 @@ static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
u32 con; u32 con;
con = OMAP_HSMMC_READ(host->base, CON); con = OMAP_HSMMC_READ(host->base, CON);
if (ios->timing == MMC_TIMING_UHS_DDR50) if (ios->timing == MMC_TIMING_MMC_DDR52)
con |= DDR; /* configure in DDR mode */ con |= DDR; /* configure in DDR mode */
else else
con &= ~DDR; con &= ~DDR;