mirror of https://gitee.com/openkylin/linux.git
octeontx2-af: Add Marvell OcteonTX2 RVU AF driver
This patch adds basic template for Marvell OcteonTX2's resource virtualization unit (RVU) admin function (AF) driver. Just the driver registration and probe. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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e40a826a6c
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@ -167,4 +167,7 @@ config SKY2_DEBUG
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If unsure, say N.
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source "drivers/net/ethernet/marvell/octeontx2/Kconfig"
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endif # NET_VENDOR_MARVELL
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@ -11,3 +11,4 @@ obj-$(CONFIG_MVPP2) += mvpp2/
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obj-$(CONFIG_PXA168_ETH) += pxa168_eth.o
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obj-$(CONFIG_SKGE) += skge.o
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obj-$(CONFIG_SKY2) += sky2.o
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obj-y += octeontx2/
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@ -0,0 +1,13 @@
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#
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# Marvell OcteonTX2 drivers configuration
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#
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config OCTEONTX2_AF
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tristate "Marvell OcteonTX2 RVU Admin Function driver"
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depends on (64BIT && COMPILE_TEST) || ARM64
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depends on PCI
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help
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This driver supports Marvell's OcteonTX2 Resource Virtualization
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Unit's admin function manager which manages all RVU HW resources
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and provides a medium to other PF/VFs to configure HW. Should be
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enabled for other RVU device drivers to work.
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@ -0,0 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0
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#
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# Makefile for Marvell OcteonTX2 device drivers.
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#
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obj-$(CONFIG_OCTEONTX2_AF) += af/
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@ -0,0 +1,8 @@
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# SPDX-License-Identifier: GPL-2.0
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#
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# Makefile for Marvell's OcteonTX2 RVU Admin Function driver
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#
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obj-$(CONFIG_OCTEONTX2_AF) += octeontx2_af.o
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octeontx2_af-y := rvu.o
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@ -0,0 +1,126 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Marvell OcteonTx2 RVU Admin Function driver
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*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/pci.h>
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#include <linux/sysfs.h>
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#include "rvu.h"
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#define DRV_NAME "octeontx2-af"
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#define DRV_STRING "Marvell OcteonTX2 RVU Admin Function Driver"
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#define DRV_VERSION "1.0"
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/* Supported devices */
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static const struct pci_device_id rvu_id_table[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AF) },
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{ 0, } /* end of table */
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};
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MODULE_AUTHOR("Marvell International Ltd.");
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MODULE_DESCRIPTION(DRV_STRING);
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MODULE_LICENSE("GPL v2");
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MODULE_VERSION(DRV_VERSION);
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MODULE_DEVICE_TABLE(pci, rvu_id_table);
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static int rvu_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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struct device *dev = &pdev->dev;
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struct rvu *rvu;
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int err;
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rvu = devm_kzalloc(dev, sizeof(*rvu), GFP_KERNEL);
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if (!rvu)
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return -ENOMEM;
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pci_set_drvdata(pdev, rvu);
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rvu->pdev = pdev;
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rvu->dev = &pdev->dev;
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err = pci_enable_device(pdev);
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if (err) {
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dev_err(dev, "Failed to enable PCI device\n");
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goto err_freemem;
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}
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err = pci_request_regions(pdev, DRV_NAME);
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if (err) {
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dev_err(dev, "PCI request regions failed 0x%x\n", err);
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goto err_disable_device;
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}
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err = pci_set_dma_mask(pdev, DMA_BIT_MASK(48));
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if (err) {
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dev_err(dev, "Unable to set DMA mask\n");
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goto err_release_regions;
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}
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err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(48));
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if (err) {
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dev_err(dev, "Unable to set consistent DMA mask\n");
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goto err_release_regions;
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}
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/* Map Admin function CSRs */
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rvu->afreg_base = pcim_iomap(pdev, PCI_AF_REG_BAR_NUM, 0);
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rvu->pfreg_base = pcim_iomap(pdev, PCI_PF_REG_BAR_NUM, 0);
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if (!rvu->afreg_base || !rvu->pfreg_base) {
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dev_err(dev, "Unable to map admin function CSRs, aborting\n");
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err = -ENOMEM;
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goto err_release_regions;
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}
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return 0;
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err_release_regions:
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pci_release_regions(pdev);
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err_disable_device:
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pci_disable_device(pdev);
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err_freemem:
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pci_set_drvdata(pdev, NULL);
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devm_kfree(dev, rvu);
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return err;
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}
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static void rvu_remove(struct pci_dev *pdev)
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{
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struct rvu *rvu = pci_get_drvdata(pdev);
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pci_release_regions(pdev);
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pci_disable_device(pdev);
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pci_set_drvdata(pdev, NULL);
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devm_kfree(&pdev->dev, rvu);
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}
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static struct pci_driver rvu_driver = {
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.name = DRV_NAME,
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.id_table = rvu_id_table,
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.probe = rvu_probe,
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.remove = rvu_remove,
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};
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static int __init rvu_init_module(void)
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{
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pr_info("%s: %s\n", DRV_NAME, DRV_STRING);
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return pci_register_driver(&rvu_driver);
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}
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static void __exit rvu_cleanup_module(void)
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{
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pci_unregister_driver(&rvu_driver);
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}
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module_init(rvu_init_module);
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module_exit(rvu_cleanup_module);
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@ -0,0 +1,31 @@
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/* SPDX-License-Identifier: GPL-2.0
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* Marvell OcteonTx2 RVU Admin Function driver
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*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef RVU_H
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#define RVU_H
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/* PCI device IDs */
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#define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065
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/* PCI BAR nos */
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#define PCI_AF_REG_BAR_NUM 0
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#define PCI_PF_REG_BAR_NUM 2
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#define PCI_MBOX_BAR_NUM 4
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#define NAME_SIZE 32
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struct rvu {
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void __iomem *afreg_base;
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void __iomem *pfreg_base;
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struct pci_dev *pdev;
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struct device *dev;
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};
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#endif /* RVU_H */
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