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MIPS: Octeon: Scale Octeon2 clocks in octeon_init_cvmcount()
The per-CPU clocks are synchronized from IPD_CLK_COUNT, on cn63XX it must be scaled by the clock frequency ratio. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1667/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -4,14 +4,18 @@
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* for more details.
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*
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* Copyright (C) 2007 by Ralf Baechle
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* Copyright (C) 2009, 2010 Cavium Networks, Inc.
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*/
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#include <linux/clocksource.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <asm/cpu-info.h>
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#include <asm/time.h>
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#include <asm/octeon/octeon.h>
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#include <asm/octeon/cvmx-ipd-defs.h>
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#include <asm/octeon/cvmx-mio-defs.h>
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/*
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* Set the current core's cvmcount counter to the value of the
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@ -19,11 +23,23 @@
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* on-line. This allows for a read from a local cpu register to
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* access a synchronized counter.
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*
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* On CPU_CAVIUM_OCTEON2 the IPD_CLK_COUNT is scaled by rdiv/sdiv.
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*/
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void octeon_init_cvmcount(void)
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{
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unsigned long flags;
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unsigned loops = 2;
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u64 f = 0;
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u64 rdiv = 0;
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u64 sdiv = 0;
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if (current_cpu_type() == CPU_CAVIUM_OCTEON2) {
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union cvmx_mio_rst_boot rst_boot;
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rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
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rdiv = rst_boot.s.c_mul; /* CPU clock */
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sdiv = rst_boot.s.pnr_mul; /* I/O clock */
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f = (0x8000000000000000ull / sdiv) * 2;
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}
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/* Clobber loops so GCC will not unroll the following while loop. */
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asm("" : "+r" (loops));
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@ -33,8 +49,20 @@ void octeon_init_cvmcount(void)
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* Loop several times so we are executing from the cache,
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* which should give more deterministic timing.
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*/
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while (loops--)
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write_c0_cvmcount(cvmx_read_csr(CVMX_IPD_CLK_COUNT));
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while (loops--) {
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u64 ipd_clk_count = cvmx_read_csr(CVMX_IPD_CLK_COUNT);
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if (rdiv != 0) {
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ipd_clk_count *= rdiv;
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if (f != 0) {
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asm("dmultu\t%[cnt],%[f]\n\t"
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"mfhi\t%[cnt]"
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: [cnt] "+r" (ipd_clk_count),
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[f] "=r" (f)
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: : "hi", "lo");
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}
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}
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write_c0_cvmcount(ipd_clk_count);
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}
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local_irq_restore(flags);
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}
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@ -77,7 +105,7 @@ unsigned long long notrace sched_clock(void)
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void __init plat_time_init(void)
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{
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clocksource_mips.rating = 300;
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clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
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clocksource_set_clock(&clocksource_mips, octeon_get_clock_rate());
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clocksource_register(&clocksource_mips);
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}
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