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drm/i915: Don't mark pdps clear if pdps are not submitted 

Don't mark pdps clear if never do the necessary actions
with the hardware to make them clear.

v2: totally get rid of confusing ppgtt bool (Chris)

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1488295691-9404-2-git-send-email-mika.kuoppala@intel.com
This commit is contained in:
Mika Kuoppala 2017-02-28 17:28:08 +02:00 committed by Mika Kuoppala
parent 3e490042a8
commit 54af56dbf8
1 changed files with 10 additions and 11 deletions
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21
drivers/gpu/drm/i915/intel_lrc.c
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@ -1291,9 +1291,8 @@ static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
static int gen8_emit_bb_start(struct drm_i915_gem_request *req, static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
u64 offset, u32 len, u64 offset, u32 len,
unsigned int dispatch_flags) const unsigned int flags)
{ {
bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
u32 *cs; u32 *cs;
int ret; int ret;
@ -1304,13 +1303,12 @@ static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
* not idle). PML4 is allocated during ppgtt init so this is * not idle). PML4 is allocated during ppgtt init so this is
* not needed in 48-bit.*/ * not needed in 48-bit.*/
if (req->ctx->ppgtt && if (req->ctx->ppgtt &&
(intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) { (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings) &&
if (!i915_vm_is_48bit(&req->ctx->ppgtt->base) && !i915_vm_is_48bit(&req->ctx->ppgtt->base) &&
!intel_vgpu_active(req->i915)) { !intel_vgpu_active(req->i915)) {
ret = intel_logical_ring_emit_pdps(req); ret = intel_logical_ring_emit_pdps(req);
if (ret) if (ret)
return ret; return ret;
}
req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine); req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine);
} }
@ -1320,8 +1318,9 @@ static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
return PTR_ERR(cs); return PTR_ERR(cs);
/* FIXME(BDW): Address space and security selectors. */ /* FIXME(BDW): Address space and security selectors. */
*cs++ = MI_BATCH_BUFFER_START_GEN8 | (ppgtt << 8) | (dispatch_flags & *cs++ = MI_BATCH_BUFFER_START_GEN8 |
I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0); (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)) |
(flags & I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0);
*cs++ = lower_32_bits(offset); *cs++ = lower_32_bits(offset);
*cs++ = upper_32_bits(offset); *cs++ = upper_32_bits(offset);
*cs++ = MI_NOOP; *cs++ = MI_NOOP;