mirror of https://gitee.com/openkylin/linux.git
[POWERPC] Celleb: Support PCI bus and base of I/O
This patch includes support for pci buses, base of Celleb specific devices, and etc. It works on of_platform bus. Signed-off-by: Kou Ishizaki <kou.ishizaki@toshiba.co.jp> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Ishizaki Kou
Paul Mackerras
parent
983e3f6027
commit
551a3d8785
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@ -0,0 +1,481 @@
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/*
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* Support for PCI on Celleb platform.
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*
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* (C) Copyright 2006-2007 TOSHIBA CORPORATION
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*
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* This code is based on arch/powerpc/kernel/rtas_pci.c:
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* Copyright (C) 2001 Dave Engebretsen, IBM Corporation
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* Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/threads.h>
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#include <linux/pci.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/bootmem.h>
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#include <linux/pci_regs.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/prom.h>
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#include <asm/machdep.h>
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#include <asm/pci-bridge.h>
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#include <asm/ppc-pci.h>
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#include "pci.h"
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#include "interrupt.h"
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#define MAX_PCI_DEVICES 32
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#define MAX_PCI_FUNCTIONS 8
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#define MAX_PCI_BASE_ADDRS 3 /* use 64 bit address */
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/* definition for fake pci configuration area for GbE, .... ,and etc. */
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struct celleb_pci_resource {
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struct resource r[MAX_PCI_BASE_ADDRS];
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};
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struct celleb_pci_private {
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unsigned char *fake_config[MAX_PCI_DEVICES][MAX_PCI_FUNCTIONS];
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struct celleb_pci_resource *res[MAX_PCI_DEVICES][MAX_PCI_FUNCTIONS];
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};
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static inline u8 celleb_fake_config_readb(void *addr)
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{
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u8 *p = addr;
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return *p;
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}
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static inline u16 celleb_fake_config_readw(void *addr)
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{
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u16 *p = addr;
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return le16_to_cpu(*p);
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}
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static inline u32 celleb_fake_config_readl(void *addr)
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{
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u32 *p = addr;
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return le32_to_cpu(*p);
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}
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static inline void celleb_fake_config_writeb(u32 val, void *addr)
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{
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u8 *p = addr;
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*p = val;
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}
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static inline void celleb_fake_config_writew(u32 val, void *addr)
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{
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u16 val16;
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u16 *p = addr;
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val16 = cpu_to_le16(val);
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*p = val16;
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}
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static inline void celleb_fake_config_writel(u32 val, void *addr)
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{
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u32 val32;
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u32 *p = addr;
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val32 = cpu_to_le32(val);
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*p = val32;
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}
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static unsigned char *get_fake_config_start(struct pci_controller *hose,
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int devno, int fn)
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{
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struct celleb_pci_private *private = hose->private_data;
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if (private == NULL)
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return NULL;
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return private->fake_config[devno][fn];
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}
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static struct celleb_pci_resource *get_resource_start(
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struct pci_controller *hose,
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int devno, int fn)
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{
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struct celleb_pci_private *private = hose->private_data;
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if (private == NULL)
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return NULL;
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return private->res[devno][fn];
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}
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static void celleb_config_read_fake(unsigned char *config, int where,
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int size, u32 *val)
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{
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char *p = config + where;
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switch (size) {
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case 1:
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*val = celleb_fake_config_readb(p);
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break;
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case 2:
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*val = celleb_fake_config_readw(p);
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break;
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case 4:
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*val = celleb_fake_config_readl(p);
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break;
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}
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return;
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}
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static void celleb_config_write_fake(unsigned char *config, int where,
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int size, u32 val)
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{
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char *p = config + where;
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switch (size) {
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case 1:
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celleb_fake_config_writeb(val, p);
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break;
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case 2:
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celleb_fake_config_writew(val, p);
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break;
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case 4:
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celleb_fake_config_writel(val, p);
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break;
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}
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return;
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}
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static int celleb_fake_pci_read_config(struct pci_bus *bus,
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unsigned int devfn, int where, int size, u32 *val)
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{
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char *config;
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struct device_node *node;
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struct pci_controller *hose;
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unsigned int devno = devfn >> 3;
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unsigned int fn = devfn & 0x7;
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/* allignment check */
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BUG_ON(where % size);
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pr_debug(" fake read: bus=0x%x, ", bus->number);
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node = (struct device_node *)bus->sysdata;
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hose = pci_find_hose_for_OF_device(node);
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config = get_fake_config_start(hose, devno, fn);
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pr_debug("devno=0x%x, where=0x%x, size=0x%x, ", devno, where, size);
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if (!config) {
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pr_debug("failed\n");
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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celleb_config_read_fake(config, where, size, val);
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pr_debug("val=0x%x\n", *val);
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return PCIBIOS_SUCCESSFUL;
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}
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static int celleb_fake_pci_write_config(struct pci_bus *bus,
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unsigned int devfn, int where, int size, u32 val)
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{
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char *config;
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struct device_node *node;
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struct pci_controller *hose;
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struct celleb_pci_resource *res;
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unsigned int devno = devfn >> 3;
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unsigned int fn = devfn & 0x7;
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/* allignment check */
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BUG_ON(where % size);
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node = (struct device_node *)bus->sysdata;
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hose = pci_find_hose_for_OF_device(node);
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config = get_fake_config_start(hose, devno, fn);
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if (!config)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (val == ~0) {
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int i = (where - PCI_BASE_ADDRESS_0) >> 3;
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switch (where) {
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case PCI_BASE_ADDRESS_0:
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case PCI_BASE_ADDRESS_2:
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if (size != 4)
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return PCIBIOS_DEVICE_NOT_FOUND;
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res = get_resource_start(hose, devno, fn);
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if (!res)
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return PCIBIOS_DEVICE_NOT_FOUND;
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celleb_config_write_fake(config, where, size,
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(res->r[i].end - res->r[i].start));
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return PCIBIOS_SUCCESSFUL;
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case PCI_BASE_ADDRESS_1:
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case PCI_BASE_ADDRESS_3:
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case PCI_BASE_ADDRESS_4:
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case PCI_BASE_ADDRESS_5:
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break;
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default:
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break;
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}
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}
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celleb_config_write_fake(config, where, size, val);
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pr_debug(" fake write: where=%x, size=%d, val=%x\n",
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where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops celleb_fake_pci_ops = {
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celleb_fake_pci_read_config,
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celleb_fake_pci_write_config
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};
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static inline void celleb_setup_pci_base_addrs(struct pci_controller *hose,
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unsigned int devno, unsigned int fn,
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unsigned int num_base_addr)
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{
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u32 val;
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unsigned char *config;
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struct celleb_pci_resource *res;
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config = get_fake_config_start(hose, devno, fn);
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res = get_resource_start(hose, devno, fn);
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if (!config || !res)
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return;
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switch (num_base_addr) {
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case 3:
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val = (res->r[2].start & 0xfffffff0)
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| PCI_BASE_ADDRESS_MEM_TYPE_64;
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celleb_config_write_fake(config, PCI_BASE_ADDRESS_4, 4, val);
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val = res->r[2].start >> 32;
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celleb_config_write_fake(config, PCI_BASE_ADDRESS_5, 4, val);
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/* FALLTHROUGH */
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case 2:
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val = (res->r[1].start & 0xfffffff0)
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| PCI_BASE_ADDRESS_MEM_TYPE_64;
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celleb_config_write_fake(config, PCI_BASE_ADDRESS_2, 4, val);
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val = res->r[1].start >> 32;
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celleb_config_write_fake(config, PCI_BASE_ADDRESS_3, 4, val);
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/* FALLTHROUGH */
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case 1:
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val = (res->r[0].start & 0xfffffff0)
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| PCI_BASE_ADDRESS_MEM_TYPE_64;
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celleb_config_write_fake(config, PCI_BASE_ADDRESS_0, 4, val);
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val = res->r[0].start >> 32;
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celleb_config_write_fake(config, PCI_BASE_ADDRESS_1, 4, val);
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break;
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}
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val = PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
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celleb_config_write_fake(config, PCI_COMMAND, 2, val);
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}
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static int __devinit celleb_setup_fake_pci_device(struct device_node *node,
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struct pci_controller *hose)
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{
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unsigned int rlen;
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int num_base_addr = 0;
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u32 val;
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const u32 *wi0, *wi1, *wi2, *wi3, *wi4;
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unsigned int devno, fn;
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struct celleb_pci_private *private = hose->private_data;
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unsigned char **config = NULL;
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struct celleb_pci_resource **res = NULL;
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const char *name;
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const unsigned long *li;
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int size, result;
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if (private == NULL) {
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printk(KERN_ERR "PCI: "
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"memory space for pci controller is not assigned\n");
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goto error;
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}
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name = get_property(node, "model", &rlen);
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if (!name) {
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printk(KERN_ERR "PCI: model property not found.\n");
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goto error;
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}
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wi4 = get_property(node, "reg", &rlen);
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if (wi4 == NULL)
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goto error;
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devno = ((wi4[0] >> 8) & 0xff) >> 3;
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fn = (wi4[0] >> 8) & 0x7;
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pr_debug("PCI: celleb_setup_fake_pci() %s devno=%x fn=%x\n", name,
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devno, fn);
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size = 256;
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config = &private->fake_config[devno][fn];
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if (mem_init_done)
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*config = kzalloc(size, GFP_KERNEL);
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else
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*config = alloc_bootmem(size);
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if (*config == NULL) {
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printk(KERN_ERR "PCI: "
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"not enough memory for fake configuration space\n");
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goto error;
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}
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pr_debug("PCI: fake config area assigned 0x%016lx\n",
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(unsigned long)*config);
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size = sizeof(struct celleb_pci_resource);
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res = &private->res[devno][fn];
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if (mem_init_done)
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*res = kzalloc(size, GFP_KERNEL);
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else
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*res = alloc_bootmem(size);
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if (*res == NULL) {
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printk(KERN_ERR
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"PCI: not enough memory for resource data space\n");
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goto error;
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}
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pr_debug("PCI: res assigned 0x%016lx\n", (unsigned long)*res);
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wi0 = get_property(node, "device-id", NULL);
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wi1 = get_property(node, "vendor-id", NULL);
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wi2 = get_property(node, "class-code", NULL);
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wi3 = get_property(node, "revision-id", NULL);
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celleb_config_write_fake(*config, PCI_DEVICE_ID, 2, wi0[0] & 0xffff);
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celleb_config_write_fake(*config, PCI_VENDOR_ID, 2, wi1[0] & 0xffff);
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pr_debug("class-code = 0x%08x\n", wi2[0]);
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celleb_config_write_fake(*config, PCI_CLASS_PROG, 1, wi2[0] & 0xff);
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celleb_config_write_fake(*config, PCI_CLASS_DEVICE, 2,
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(wi2[0] >> 8) & 0xffff);
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celleb_config_write_fake(*config, PCI_REVISION_ID, 1, wi3[0]);
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while (num_base_addr < MAX_PCI_BASE_ADDRS) {
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result = of_address_to_resource(node,
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num_base_addr, &(*res)->r[num_base_addr]);
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if (result)
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break;
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num_base_addr++;
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}
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celleb_setup_pci_base_addrs(hose, devno, fn, num_base_addr);
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li = get_property(node, "interrupts", &rlen);
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val = li[0];
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celleb_config_write_fake(*config, PCI_INTERRUPT_PIN, 1, 1);
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celleb_config_write_fake(*config, PCI_INTERRUPT_LINE, 1, val);
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#ifdef DEBUG
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pr_debug("PCI: %s irq=%ld\n", name, li[0]);
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for (i = 0; i < 6; i++) {
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celleb_config_read_fake(*config,
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PCI_BASE_ADDRESS_0 + 0x4 * i, 4,
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&val);
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pr_debug("PCI: %s fn=%d base_address_%d=0x%x\n",
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name, fn, i, val);
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}
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#endif
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celleb_config_write_fake(*config, PCI_HEADER_TYPE, 1,
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PCI_HEADER_TYPE_NORMAL);
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return 0;
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error:
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if (mem_init_done) {
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if (config && *config)
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kfree(*config);
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if (res && *res)
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kfree(*res);
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} else {
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if (config && *config) {
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size = 256;
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free_bootmem((unsigned long)(*config), size);
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}
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if (res && *res) {
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size = sizeof(struct celleb_pci_resource);
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free_bootmem((unsigned long)(*res), size);
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}
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}
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return 1;
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}
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static int __devinit phb_set_bus_ranges(struct device_node *dev,
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struct pci_controller *phb)
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{
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const int *bus_range;
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unsigned int len;
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bus_range = get_property(dev, "bus-range", &len);
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if (bus_range == NULL || len < 2 * sizeof(int))
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return 1;
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phb->first_busno = bus_range[0];
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phb->last_busno = bus_range[1];
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return 0;
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}
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static void __devinit celleb_alloc_private_mem(struct pci_controller *hose)
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{
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if (mem_init_done)
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hose->private_data =
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kzalloc(sizeof(struct celleb_pci_private), GFP_KERNEL);
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else
|
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hose->private_data =
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alloc_bootmem(sizeof(struct celleb_pci_private));
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}
|
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int __devinit celleb_setup_phb(struct pci_controller *phb)
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{
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const char *name;
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struct device_node *dev = phb->arch_data;
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struct device_node *node;
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unsigned int rlen;
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name = get_property(dev, "name", &rlen);
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if (!name)
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return 1;
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pr_debug("PCI: celleb_setup_phb() %s\n", name);
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phb_set_bus_ranges(dev, phb);
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|
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if (strcmp(name, "epci") == 0) {
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phb->ops = &celleb_epci_ops;
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return celleb_setup_epci(dev, phb);
|
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|
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} else if (strcmp(name, "pci-pseudo") == 0) {
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phb->ops = &celleb_fake_pci_ops;
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celleb_alloc_private_mem(phb);
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for (node = of_get_next_child(dev, NULL);
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node != NULL; node = of_get_next_child(dev, node))
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celleb_setup_fake_pci_device(node, phb);
|
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|
||||
} else
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int celleb_pci_probe_mode(struct pci_bus *bus)
|
||||
{
|
||||
return PCI_PROBE_DEVTREE;
|
||||
}
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* pci prototypes for Celleb platform
|
||||
*
|
||||
* (C) Copyright 2006-2007 TOSHIBA CORPORATION
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#ifndef _CELLEB_PCI_H
|
||||
#define _CELLEB_PCI_H
|
||||
|
||||
#include <linux/pci.h>
|
||||
|
||||
#include <asm/pci-bridge.h>
|
||||
#include <asm/prom.h>
|
||||
|
||||
extern int celleb_setup_phb(struct pci_controller *);
|
||||
extern int celleb_pci_probe_mode(struct pci_bus *);
|
||||
|
||||
extern struct pci_ops celleb_epci_ops;
|
||||
extern int celleb_setup_epci(struct device_node *, struct pci_controller *);
|
||||
|
||||
#endif /* _CELLEB_PCI_H */
|
||||
|
|
@ -0,0 +1,409 @@
|
|||
/*
|
||||
* Support for SCC external PCI
|
||||
*
|
||||
* (C) Copyright 2004-2007 TOSHIBA CORPORATION
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#undef DEBUG
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/threads.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/pci_regs.h>
|
||||
#include <linux/bootmem.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/pci-bridge.h>
|
||||
#include <asm/ppc-pci.h>
|
||||
|
||||
#include "scc.h"
|
||||
#include "pci.h"
|
||||
#include "interrupt.h"
|
||||
|
||||
#define MAX_PCI_DEVICES 32
|
||||
#define MAX_PCI_FUNCTIONS 8
|
||||
|
||||
#define iob() __asm__ __volatile__("eieio; sync":::"memory")
|
||||
|
||||
|
||||
#if 0 /* test code for epci dummy read */
|
||||
static void celleb_epci_dummy_read(struct pci_dev *dev)
|
||||
{
|
||||
void *epci_base;
|
||||
struct device_node *node;
|
||||
struct pci_controller *hose;
|
||||
u32 val;
|
||||
|
||||
node = (struct device_node *)dev->bus->sysdata;
|
||||
hose = pci_find_hose_for_OF_device(node);
|
||||
|
||||
if (!hose)
|
||||
return;
|
||||
|
||||
epci_base = (void *)hose->cfg_addr;
|
||||
|
||||
val = in_be32(epci_base + SCC_EPCI_WATRP);
|
||||
iosync();
|
||||
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline void clear_and_disable_master_abort_interrupt(
|
||||
struct pci_controller *hose)
|
||||
{
|
||||
void __iomem *addr;
|
||||
addr = (void *)hose->cfg_addr + PCI_COMMAND;
|
||||
out_be32(addr, in_be32(addr) | (PCI_STATUS_REC_MASTER_ABORT << 16));
|
||||
}
|
||||
|
||||
static int celleb_epci_check_abort(struct pci_controller *hose,
|
||||
unsigned long addr)
|
||||
{
|
||||
void __iomem *reg, *epci_base;
|
||||
u32 val;
|
||||
|
||||
iob();
|
||||
epci_base = (void *)hose->cfg_addr;
|
||||
|
||||
reg = epci_base + PCI_COMMAND;
|
||||
val = in_be32(reg);
|
||||
|
||||
if (val & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
|
||||
out_be32(reg,
|
||||
(val & 0xffff) | (PCI_STATUS_REC_MASTER_ABORT << 16));
|
||||
|
||||
/* clear PCI Controller error, FRE, PMFE */
|
||||
reg = epci_base + SCC_EPCI_STATUS;
|
||||
out_be32(reg, SCC_EPCI_INT_PAI);
|
||||
|
||||
reg = epci_base + SCC_EPCI_VCSR;
|
||||
val = in_be32(reg) & 0xffff;
|
||||
val |= SCC_EPCI_VCSR_FRE;
|
||||
out_be32(reg, val);
|
||||
|
||||
reg = epci_base + SCC_EPCI_VISTAT;
|
||||
out_be32(reg, SCC_EPCI_VISTAT_PMFE);
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
}
|
||||
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
static unsigned long celleb_epci_make_config_addr(struct pci_controller *hose,
|
||||
unsigned int devfn, int where)
|
||||
{
|
||||
unsigned long addr;
|
||||
struct pci_bus *bus = hose->bus;
|
||||
|
||||
if (bus->self)
|
||||
addr = (unsigned long)hose->cfg_data +
|
||||
(((bus->number & 0xff) << 16)
|
||||
| ((devfn & 0xff) << 8)
|
||||
| (where & 0xff)
|
||||
| 0x01000000);
|
||||
else
|
||||
addr = (unsigned long)hose->cfg_data +
|
||||
(((devfn & 0xff) << 8) | (where & 0xff));
|
||||
|
||||
pr_debug("EPCI: config_addr = 0x%016lx\n", addr);
|
||||
|
||||
return addr;
|
||||
}
|
||||
|
||||
static int celleb_epci_read_config(struct pci_bus *bus,
|
||||
unsigned int devfn, int where, int size, u32 * val)
|
||||
{
|
||||
unsigned long addr;
|
||||
struct device_node *node;
|
||||
struct pci_controller *hose;
|
||||
|
||||
/* allignment check */
|
||||
BUG_ON(where % size);
|
||||
|
||||
node = (struct device_node *)bus->sysdata;
|
||||
hose = pci_find_hose_for_OF_device(node);
|
||||
|
||||
if (!hose->cfg_data)
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
|
||||
if (bus->number == hose->first_busno && devfn == 0) {
|
||||
/* EPCI controller self */
|
||||
|
||||
addr = (unsigned long)hose->cfg_addr + where;
|
||||
|
||||
switch (size) {
|
||||
case 1:
|
||||
*val = in_8((u8 *)addr);
|
||||
break;
|
||||
case 2:
|
||||
*val = in_be16((u16 *)addr);
|
||||
break;
|
||||
case 4:
|
||||
*val = in_be32((u32 *)addr);
|
||||
break;
|
||||
default:
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
}
|
||||
|
||||
} else {
|
||||
|
||||
clear_and_disable_master_abort_interrupt(hose);
|
||||
addr = celleb_epci_make_config_addr(hose, devfn, where);
|
||||
|
||||
switch (size) {
|
||||
case 1:
|
||||
*val = in_8((u8 *)addr);
|
||||
break;
|
||||
case 2:
|
||||
*val = in_le16((u16 *)addr);
|
||||
break;
|
||||
case 4:
|
||||
*val = in_le32((u32 *)addr);
|
||||
break;
|
||||
default:
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
}
|
||||
}
|
||||
|
||||
pr_debug("EPCI: "
|
||||
"addr=0x%lx, devfn=0x%x, where=0x%x, size=0x%x, val=0x%x\n",
|
||||
addr, devfn, where, size, *val);
|
||||
|
||||
return celleb_epci_check_abort(hose, 0);
|
||||
}
|
||||
|
||||
static int celleb_epci_write_config(struct pci_bus *bus,
|
||||
unsigned int devfn, int where, int size, u32 val)
|
||||
{
|
||||
unsigned long addr;
|
||||
struct device_node *node;
|
||||
struct pci_controller *hose;
|
||||
|
||||
/* allignment check */
|
||||
BUG_ON(where % size);
|
||||
|
||||
node = (struct device_node *)bus->sysdata;
|
||||
hose = pci_find_hose_for_OF_device(node);
|
||||
|
||||
if (!hose->cfg_data)
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
|
||||
if (bus->number == hose->first_busno && devfn == 0) {
|
||||
/* EPCI controller self */
|
||||
|
||||
addr = (unsigned long)hose->cfg_addr + where;
|
||||
|
||||
switch (size) {
|
||||
case 1:
|
||||
out_8((u8 *)addr, val);
|
||||
break;
|
||||
case 2:
|
||||
out_be16((u16 *)addr, val);
|
||||
break;
|
||||
case 4:
|
||||
out_be32((u32 *)addr, val);
|
||||
break;
|
||||
default:
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
}
|
||||
|
||||
} else {
|
||||
|
||||
clear_and_disable_master_abort_interrupt(hose);
|
||||
addr = celleb_epci_make_config_addr(hose, devfn, where);
|
||||
|
||||
switch (size) {
|
||||
case 1:
|
||||
out_8((u8 *)addr, val);
|
||||
break;
|
||||
case 2:
|
||||
out_le16((u16 *)addr, val);
|
||||
break;
|
||||
case 4:
|
||||
out_le32((u32 *)addr, val);
|
||||
break;
|
||||
default:
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
}
|
||||
}
|
||||
|
||||
return celleb_epci_check_abort(hose, addr);
|
||||
}
|
||||
|
||||
struct pci_ops celleb_epci_ops = {
|
||||
celleb_epci_read_config,
|
||||
celleb_epci_write_config,
|
||||
};
|
||||
|
||||
/* to be moved in FW */
|
||||
static int __devinit celleb_epci_init(struct pci_controller *hose)
|
||||
{
|
||||
u32 val;
|
||||
void __iomem *reg, *epci_base;
|
||||
int hwres = 0;
|
||||
|
||||
epci_base = (void *)hose->cfg_addr;
|
||||
|
||||
/* PCI core reset(Internal bus and PCI clock) */
|
||||
reg = epci_base + SCC_EPCI_CKCTRL;
|
||||
val = in_be32(reg);
|
||||
if (val == 0x00030101)
|
||||
hwres = 1;
|
||||
else {
|
||||
val &= ~(SCC_EPCI_CKCTRL_CRST0 | SCC_EPCI_CKCTRL_CRST1);
|
||||
out_be32(reg, val);
|
||||
|
||||
/* set PCI core clock */
|
||||
val = in_be32(reg);
|
||||
val |= (SCC_EPCI_CKCTRL_OCLKEN | SCC_EPCI_CKCTRL_LCLKEN);
|
||||
out_be32(reg, val);
|
||||
|
||||
/* release PCI core reset (internal bus) */
|
||||
val = in_be32(reg);
|
||||
val |= SCC_EPCI_CKCTRL_CRST0;
|
||||
out_be32(reg, val);
|
||||
|
||||
/* set PCI clock select */
|
||||
reg = epci_base + SCC_EPCI_CLKRST;
|
||||
val = in_be32(reg);
|
||||
val &= ~SCC_EPCI_CLKRST_CKS_MASK;
|
||||
val |= SCC_EPCI_CLKRST_CKS_2;
|
||||
out_be32(reg, val);
|
||||
|
||||
/* set arbiter */
|
||||
reg = epci_base + SCC_EPCI_ABTSET;
|
||||
out_be32(reg, 0x0f1f001f); /* temporary value */
|
||||
|
||||
/* buffer on */
|
||||
reg = epci_base + SCC_EPCI_CLKRST;
|
||||
val = in_be32(reg);
|
||||
val |= SCC_EPCI_CLKRST_BC;
|
||||
out_be32(reg, val);
|
||||
|
||||
/* PCI clock enable */
|
||||
val = in_be32(reg);
|
||||
val |= SCC_EPCI_CLKRST_PCKEN;
|
||||
out_be32(reg, val);
|
||||
|
||||
/* release PCI core reset (all) */
|
||||
reg = epci_base + SCC_EPCI_CKCTRL;
|
||||
val = in_be32(reg);
|
||||
val |= (SCC_EPCI_CKCTRL_CRST0 | SCC_EPCI_CKCTRL_CRST1);
|
||||
out_be32(reg, val);
|
||||
|
||||
/* set base translation registers. (already set by Beat) */
|
||||
|
||||
/* set base address masks. (already set by Beat) */
|
||||
}
|
||||
|
||||
/* release interrupt masks and clear all interrupts */
|
||||
reg = epci_base + SCC_EPCI_INTSET;
|
||||
out_be32(reg, 0x013f011f); /* all interrupts enable */
|
||||
reg = epci_base + SCC_EPCI_VIENAB;
|
||||
val = SCC_EPCI_VIENAB_PMPEE | SCC_EPCI_VIENAB_PMFEE;
|
||||
out_be32(reg, val);
|
||||
reg = epci_base + SCC_EPCI_STATUS;
|
||||
out_be32(reg, 0xffffffff);
|
||||
reg = epci_base + SCC_EPCI_VISTAT;
|
||||
out_be32(reg, 0xffffffff);
|
||||
|
||||
/* disable PCI->IB address translation */
|
||||
reg = epci_base + SCC_EPCI_VCSR;
|
||||
val = in_be32(reg);
|
||||
val &= ~(SCC_EPCI_VCSR_DR | SCC_EPCI_VCSR_AT);
|
||||
out_be32(reg, val);
|
||||
|
||||
/* set base addresses. (no need to set?) */
|
||||
|
||||
/* memory space, bus master enable */
|
||||
reg = epci_base + PCI_COMMAND;
|
||||
val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
|
||||
out_be32(reg, val);
|
||||
|
||||
/* endian mode setup */
|
||||
reg = epci_base + SCC_EPCI_ECMODE;
|
||||
val = 0x00550155;
|
||||
out_be32(reg, val);
|
||||
|
||||
/* set control option */
|
||||
reg = epci_base + SCC_EPCI_CNTOPT;
|
||||
val = in_be32(reg);
|
||||
val |= SCC_EPCI_CNTOPT_O2PMB;
|
||||
out_be32(reg, val);
|
||||
|
||||
/* XXX: temporay: set registers for address conversion setup */
|
||||
reg = epci_base + SCC_EPCI_CNF10_REG;
|
||||
out_be32(reg, 0x80000008);
|
||||
reg = epci_base + SCC_EPCI_CNF14_REG;
|
||||
out_be32(reg, 0x40000008);
|
||||
|
||||
reg = epci_base + SCC_EPCI_BAM0;
|
||||
out_be32(reg, 0x80000000);
|
||||
reg = epci_base + SCC_EPCI_BAM1;
|
||||
out_be32(reg, 0xe0000000);
|
||||
|
||||
reg = epci_base + SCC_EPCI_PVBAT;
|
||||
out_be32(reg, 0x80000000);
|
||||
|
||||
if (!hwres) {
|
||||
/* release external PCI reset */
|
||||
reg = epci_base + SCC_EPCI_CLKRST;
|
||||
val = in_be32(reg);
|
||||
val |= SCC_EPCI_CLKRST_PCIRST;
|
||||
out_be32(reg, val);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int __devinit celleb_setup_epci(struct device_node *node,
|
||||
struct pci_controller *hose)
|
||||
{
|
||||
struct resource r;
|
||||
|
||||
pr_debug("PCI: celleb_setup_epci()\n");
|
||||
|
||||
if (of_address_to_resource(node, 0, &r))
|
||||
goto error;
|
||||
hose->cfg_addr = ioremap(r.start, (r.end - r.start + 1));
|
||||
if (!hose->cfg_addr)
|
||||
goto error;
|
||||
pr_debug("EPCI: cfg_addr map 0x%016lx->0x%016lx + 0x%016lx\n",
|
||||
r.start, (unsigned long)hose->cfg_addr,
|
||||
(r.end - r.start + 1));
|
||||
|
||||
if (of_address_to_resource(node, 2, &r))
|
||||
goto error;
|
||||
hose->cfg_data = ioremap(r.start, (r.end - r.start + 1));
|
||||
if (!hose->cfg_data)
|
||||
goto error;
|
||||
pr_debug("EPCI: cfg_data map 0x%016lx->0x%016lx + 0x%016lx\n",
|
||||
r.start, (unsigned long)hose->cfg_data,
|
||||
(r.end - r.start + 1));
|
||||
|
||||
celleb_epci_init(hose);
|
||||
|
||||
return 0;
|
||||
|
||||
error:
|
||||
return 1;
|
||||
}
|
||||
Loading…
Reference in New Issue