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Blackfin: bf54x: add kconfig for UART2/3 DMA channel assignments 

The BF54x lacks dedicated DMA channels for the UART peripherals and need
to be muxed between others.  So add a kconfig option so people can select
which channels the UARTs will use so they can pick between SPORTs and the
less commonly used EPPI/PIXC peripherals.

Signed-off-by: steven miao <realmz6@gmail.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
steven miao 2010-10-22 08:48:41 +00:00 committed by Mike Frysinger
parent 6ce0466d63
commit 55835175a0
4 changed files with 102 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
arch/blackfin/kernel/bfin_dma_5xx.c
View File

@ -84,6 +84,24 @@ static int __init proc_dma_init(void)
late_initcall(proc_dma_init);
#endif
static void set_dma_peripheral_map(unsigned int channel, const char *device_id)
{
#ifdef CONFIG_BF54x
unsigned int per_map;
switch (channel) {
case CH_UART2_RX: per_map = 0xC << 12; break;
case CH_UART2_TX: per_map = 0xD << 12; break;
case CH_UART3_RX: per_map = 0xE << 12; break;
case CH_UART3_TX: per_map = 0xF << 12; break;
default: return;
}
if (strncmp(device_id, "BFIN_UART", 9) == 0)
dma_ch[channel].regs->peripheral_map = per_map;
#endif
}
/**
* request_dma - request a DMA channel
*
@ -111,19 +129,7 @@ int request_dma(unsigned int channel, const char *device_id)
return -EBUSY;
}
#ifdef CONFIG_BF54x
if (channel >= CH_UART2_RX && channel <= CH_UART3_TX) {
unsigned int per_map;
per_map = dma_ch[channel].regs->peripheral_map & 0xFFF;
if (strncmp(device_id, "BFIN_UART", 9) == 0)
dma_ch[channel].regs->peripheral_map = per_map |
((channel - CH_UART2_RX + 0xC)<<12);
else
dma_ch[channel].regs->peripheral_map = per_map |
((channel - CH_UART2_RX + 0x6)<<12);
}
#endif
set_dma_peripheral_map(channel, device_id);
dma_ch[channel].device_id = device_id;
dma_ch[channel].irq = 0;

59
arch/blackfin/mach-bf548/Kconfig
View File

@ -42,6 +42,65 @@ config BF548_ATAPI_ALTERNATIVE_PORT
async address or GPIO port F and G. Select y to route it
to GPIO.
choice
prompt "UART2 DMA channel selection"
depends on SERIAL_BFIN_UART2
default UART2_DMA_RX_ON_DMA18
help
UART2 DMA channel selection
RX -> DMA18
TX -> DMA19
or
RX -> DMA13
TX -> DMA14
config UART2_DMA_RX_ON_DMA18
bool "UART2 DMA RX -> DMA18 TX -> DMA19"
help
UART2 DMA channel assignment
RX -> DMA18
TX -> DMA19
use SPORT2 default DMA channel
config UART2_DMA_RX_ON_DMA13
bool "UART2 DMA RX -> DMA13 TX -> DMA14"
help
UART2 DMA channel assignment
RX -> DMA13
TX -> DMA14
use EPPI1 EPPI2 default DMA channel
endchoice
choice
prompt "UART3 DMA channel selection"
depends on SERIAL_BFIN_UART3
default UART3_DMA_RX_ON_DMA20
help
UART3 DMA channel selection
RX -> DMA20
TX -> DMA21
or
RX -> DMA15
TX -> DMA16
config UART3_DMA_RX_ON_DMA20
bool "UART3 DMA RX -> DMA20 TX -> DMA21"
help
UART3 DMA channel assignment
RX -> DMA20
TX -> DMA21
use SPORT3 default DMA channel
config UART3_DMA_RX_ON_DMA15
bool "UART3 DMA RX -> DMA15 TX -> DMA16"
help
UART3 DMA channel assignment
RX -> DMA15
TX -> DMA16
use PIXC default DMA channel
endchoice
comment "Interrupt Priority Assignment"
menu "Priority"

28
arch/blackfin/mach-bf548/include/mach/dma.h
View File

@ -27,17 +27,37 @@
#define CH_PIXC_OVERLAY 16
#define CH_PIXC_OUTPUT 17
#define CH_SPORT2_RX 18
#define CH_UART2_RX 18
#define CH_SPORT2_TX 19
#define CH_UART2_TX 19
#define CH_SPORT3_RX 20
#define CH_UART3_RX 20
#define CH_SPORT3_TX 21
#define CH_UART3_TX 21
#define CH_SDH 22
#define CH_NFC 22
#define CH_SPI2 23
#if defined(CONFIG_UART2_DMA_RX_ON_DMA13)
#define CH_UART2_RX 13
#define IRQ_UART2_RX BFIN_IRQ(37) /* UART2 RX USE EPP1 (DMA13) Interrupt */
#define CH_UART2_TX 14
#define IRQ_UART2_TX BFIN_IRQ(38) /* UART2 RX USE EPP1 (DMA14) Interrupt */
#else /* Default USE SPORT2's DMA Channel */
#define CH_UART2_RX 18
#define IRQ_UART2_RX BFIN_IRQ(33) /* UART2 RX (DMA18) Interrupt */
#define CH_UART2_TX 19
#define IRQ_UART2_TX BFIN_IRQ(34) /* UART2 TX (DMA19) Interrupt */
#endif
#if defined(CONFIG_UART3_DMA_RX_ON_DMA15)
#define CH_UART3_RX 15
#define IRQ_UART3_RX BFIN_IRQ(64) /* UART3 RX USE PIXC IN0 (DMA15) Interrupt */
#define CH_UART3_TX 16
#define IRQ_UART3_TX BFIN_IRQ(65) /* UART3 TX USE PIXC IN1 (DMA16) Interrupt */
#else /* Default USE SPORT3's DMA Channel */
#define CH_UART3_RX 20
#define IRQ_UART3_RX BFIN_IRQ(35) /* UART3 RX (DMA20) Interrupt */
#define CH_UART3_TX 21
#define IRQ_UART3_TX BFIN_IRQ(36) /* UART3 TX (DMA21) Interrupt */
#endif
#define CH_MEM_STREAM0_DEST 24
#define CH_MEM_STREAM0_SRC 25
#define CH_MEM_STREAM1_DEST 26

4
arch/blackfin/mach-bf548/include/mach/irq.h
View File

@ -74,13 +74,9 @@ Events (highest priority) EMU 0
#define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */
#define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */
#define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */
#define IRQ_UART2_RX BFIN_IRQ(33) /* UART2 RX (DMA18) Interrupt */
#define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */
#define IRQ_UART2_TX BFIN_IRQ(34) /* UART2 TX (DMA19) Interrupt */
#define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */
#define IRQ_UART3_RX BFIN_IRQ(35) /* UART3 RX (DMA20) Interrupt */
#define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */
#define IRQ_UART3_TX BFIN_IRQ(36) /* UART3 TX (DMA21) Interrupt */
#define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */
#define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */
#define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */