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ARM: dts: add GSBI8 defines to the MSM8660 family 

This defines the memory location and interrupt used by the GSBI8
I2C adapter on the MSM8660 SoCs. We add it as "disabled" by
default so that boards using this I2C can enable it.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This commit is contained in:
Linus Walleij 2017-05-15 09:50:12 +02:00 committed by Andy Gross
parent 567cf21350
commit 5594207294
1 changed files with 25 additions and 0 deletions
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25
arch/arm/boot/dts/qcom-msm8660.dtsi
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@ -123,6 +123,31 @@ gcc: clock-controller@900000 {
reg = <0x900000 0x4000>;
};
gsbi8: gsbi@19800000 {
compatible = "qcom,gsbi-v1.0.0";
cell-index = <12>;
reg = <0x19800000 0x100>;
clocks = <&gcc GSBI8_H_CLK>;
clock-names = "iface";
#address-cells = <1>;
#size-cells = <1>;
ranges;
syscon-tcsr = <&tcsr>;
gsbi8_i2c: i2c@19880000 {
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x19880000 0x1000>;
interrupts = <GIC_SPI 161 IRQ_TYPE_NONE>;
clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>;
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
gsbi12: gsbi@19c00000 {
compatible = "qcom,gsbi-v1.0.0";
cell-index = <12>;