mirror of https://gitee.com/openkylin/linux.git
x86: clean up aperture_64.c
1. use symbolic register names where appropriate. 2. num to bus or slot changing 3. handle for new opteron for bus other than 0 Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Yinghai Lu
Ingo Molnar
parent
7677b2ef6c
commit
55c0d721df
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@ -35,6 +35,18 @@ int fallback_aper_force __initdata;
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int fix_aperture __initdata = 1;
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struct bus_dev_range {
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int bus;
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int dev_base;
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int dev_limit;
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};
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static struct bus_dev_range bus_dev_ranges[] __initdata = {
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{ 0x00, 0x18, 0x20},
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{ 0xff, 0x00, 0x20},
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{ 0xfe, 0x00, 0x20}
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};
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static struct resource gart_resource = {
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.name = "GART",
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.flags = IORESOURCE_MEM,
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@ -120,33 +132,33 @@ static int __init aperture_valid(u64 aper_base, u32 aper_size, u32 min_size)
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}
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/* Find a PCI capability */
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static __u32 __init find_cap(int num, int slot, int func, int cap)
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static __u32 __init find_cap(int bus, int slot, int func, int cap)
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{
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int bytes;
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u8 pos;
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if (!(read_pci_config_16(num, slot, func, PCI_STATUS) &
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if (!(read_pci_config_16(bus, slot, func, PCI_STATUS) &
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PCI_STATUS_CAP_LIST))
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return 0;
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pos = read_pci_config_byte(num, slot, func, PCI_CAPABILITY_LIST);
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pos = read_pci_config_byte(bus, slot, func, PCI_CAPABILITY_LIST);
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for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) {
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u8 id;
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pos &= ~3;
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id = read_pci_config_byte(num, slot, func, pos+PCI_CAP_LIST_ID);
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id = read_pci_config_byte(bus, slot, func, pos+PCI_CAP_LIST_ID);
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if (id == 0xff)
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break;
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if (id == cap)
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return pos;
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pos = read_pci_config_byte(num, slot, func,
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pos = read_pci_config_byte(bus, slot, func,
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pos+PCI_CAP_LIST_NEXT);
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}
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return 0;
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}
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/* Read a standard AGPv3 bridge header */
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static __u32 __init read_agp(int num, int slot, int func, int cap, u32 *order)
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static __u32 __init read_agp(int bus, int slot, int func, int cap, u32 *order)
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{
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u32 apsize;
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u32 apsizereg;
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@ -155,8 +167,8 @@ static __u32 __init read_agp(int num, int slot, int func, int cap, u32 *order)
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u64 aper;
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u32 old_order;
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printk(KERN_INFO "AGP bridge at %02x:%02x:%02x\n", num, slot, func);
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apsizereg = read_pci_config_16(num, slot, func, cap + 0x14);
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printk(KERN_INFO "AGP bridge at %02x:%02x:%02x\n", bus, slot, func);
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apsizereg = read_pci_config_16(bus, slot, func, cap + 0x14);
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if (apsizereg == 0xffffffff) {
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printk(KERN_ERR "APSIZE in AGP bridge unreadable\n");
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return 0;
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@ -174,8 +186,8 @@ static __u32 __init read_agp(int num, int slot, int func, int cap, u32 *order)
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if ((int)*order < 0) /* < 32MB */
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*order = 0;
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aper_low = read_pci_config(num, slot, func, 0x10);
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aper_hi = read_pci_config(num, slot, func, 0x14);
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aper_low = read_pci_config(bus, slot, func, 0x10);
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aper_hi = read_pci_config(bus, slot, func, 0x14);
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aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
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/*
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@ -213,15 +225,15 @@ static __u32 __init read_agp(int num, int slot, int func, int cap, u32 *order)
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*/
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static __u32 __init search_agp_bridge(u32 *order, int *valid_agp)
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{
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int num, slot, func;
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int bus, slot, func;
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/* Poor man's PCI discovery */
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for (num = 0; num < 256; num++) {
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for (bus = 0; bus < 256; bus++) {
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for (slot = 0; slot < 32; slot++) {
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for (func = 0; func < 8; func++) {
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u32 class, cap;
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u8 type;
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class = read_pci_config(num, slot, func,
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class = read_pci_config(bus, slot, func,
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PCI_CLASS_REVISION);
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if (class == 0xffffffff)
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break;
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@ -230,17 +242,17 @@ static __u32 __init search_agp_bridge(u32 *order, int *valid_agp)
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case PCI_CLASS_BRIDGE_HOST:
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case PCI_CLASS_BRIDGE_OTHER: /* needed? */
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/* AGP bridge? */
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cap = find_cap(num, slot, func,
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cap = find_cap(bus, slot, func,
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PCI_CAP_ID_AGP);
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if (!cap)
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break;
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*valid_agp = 1;
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return read_agp(num, slot, func, cap,
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return read_agp(bus, slot, func, cap,
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order);
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}
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/* No multi-function device? */
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type = read_pci_config_byte(num, slot, func,
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type = read_pci_config_byte(bus, slot, func,
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PCI_HEADER_TYPE);
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if (!(type & 0x80))
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break;
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@ -280,38 +292,49 @@ void __init early_gart_iommu_check(void)
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* or BIOS forget to put that in reserved.
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* try to update e820 to make that region as reserved.
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*/
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int fix, num;
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int fix, slot;
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u32 ctl;
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u32 aper_size = 0, aper_order = 0, last_aper_order = 0;
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u64 aper_base = 0, last_aper_base = 0;
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int aper_enabled = 0, last_aper_enabled = 0;
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int i;
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if (!early_pci_allowed())
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return;
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fix = 0;
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for (num = 24; num < 32; num++) {
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if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
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continue;
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for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
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int bus;
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int dev_base, dev_limit;
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ctl = read_pci_config(0, num, 3, 0x90);
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aper_enabled = ctl & 1;
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aper_order = (ctl >> 1) & 7;
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aper_size = (32 * 1024 * 1024) << aper_order;
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aper_base = read_pci_config(0, num, 3, 0x94) & 0x7fff;
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aper_base <<= 25;
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bus = bus_dev_ranges[i].bus;
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dev_base = bus_dev_ranges[i].dev_base;
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dev_limit = bus_dev_ranges[i].dev_limit;
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if ((last_aper_order && aper_order != last_aper_order) ||
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(last_aper_base && aper_base != last_aper_base) ||
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(last_aper_enabled && aper_enabled != last_aper_enabled)) {
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fix = 1;
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break;
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for (slot = dev_base; slot < dev_limit; slot++) {
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if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00)))
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continue;
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ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
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aper_enabled = ctl & AMD64_GARTEN;
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aper_order = (ctl >> 1) & 7;
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aper_size = (32 * 1024 * 1024) << aper_order;
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aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;
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aper_base <<= 25;
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if ((last_aper_order && aper_order != last_aper_order) ||
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(last_aper_base && aper_base != last_aper_base) ||
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(last_aper_enabled && aper_enabled != last_aper_enabled)) {
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fix = 1;
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goto out;
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}
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last_aper_order = aper_order;
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last_aper_base = aper_base;
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last_aper_enabled = aper_enabled;
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}
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last_aper_order = aper_order;
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last_aper_base = aper_base;
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last_aper_enabled = aper_enabled;
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}
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out:
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if (!fix && !aper_enabled)
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return;
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@ -330,13 +353,22 @@ void __init early_gart_iommu_check(void)
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}
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/* different nodes have different setting, disable them all at first*/
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for (num = 24; num < 32; num++) {
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if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
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continue;
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for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
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int bus;
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int dev_base, dev_limit;
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ctl = read_pci_config(0, num, 3, 0x90);
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ctl &= ~1;
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write_pci_config(0, num, 3, 0x90, ctl);
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bus = bus_dev_ranges[i].bus;
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dev_base = bus_dev_ranges[i].dev_base;
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dev_limit = bus_dev_ranges[i].dev_limit;
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for (slot = dev_base; slot < dev_limit; slot++) {
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if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00)))
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continue;
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ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
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ctl &= ~AMD64_GARTEN;
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write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
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}
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}
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}
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@ -348,8 +380,8 @@ void __init gart_iommu_hole_init(void)
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u32 agp_aper_base = 0, agp_aper_order = 0;
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u32 aper_size, aper_alloc = 0, aper_order = 0, last_aper_order = 0;
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u64 aper_base, last_aper_base = 0;
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int fix, num, valid_agp = 0;
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int node;
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int fix, slot, valid_agp = 0;
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int i, node;
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if (gart_iommu_aperture_disabled || !fix_aperture ||
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!early_pci_allowed())
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@ -362,48 +394,58 @@ void __init gart_iommu_hole_init(void)
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fix = 0;
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node = 0;
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for (num = 24; num < 32; num++) {
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if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
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continue;
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for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
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int bus;
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int dev_base, dev_limit;
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iommu_detected = 1;
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gart_iommu_aperture = 1;
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bus = bus_dev_ranges[i].bus;
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dev_base = bus_dev_ranges[i].dev_base;
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dev_limit = bus_dev_ranges[i].dev_limit;
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aper_order = (read_pci_config(0, num, 3, 0x90) >> 1) & 7;
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aper_size = (32 * 1024 * 1024) << aper_order;
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aper_base = read_pci_config(0, num, 3, 0x94) & 0x7fff;
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aper_base <<= 25;
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for (slot = dev_base; slot < dev_limit; slot++) {
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if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00)))
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continue;
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printk(KERN_INFO "Node %d: aperture @ %Lx size %u MB\n",
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node, aper_base, aper_size >> 20);
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node++;
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iommu_detected = 1;
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gart_iommu_aperture = 1;
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if (!aperture_valid(aper_base, aper_size, 64<<20)) {
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if (valid_agp && agp_aper_base &&
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agp_aper_base == aper_base &&
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agp_aper_order == aper_order) {
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/* the same between two setting from NB and agp */
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if (!no_iommu && end_pfn > MAX_DMA32_PFN && !printed_gart_size_msg) {
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printk(KERN_ERR "you are using iommu with agp, but GART size is less than 64M\n");
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printk(KERN_ERR "please increase GART size in your BIOS setup\n");
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printk(KERN_ERR "if BIOS doesn't have that option, contact your HW vendor!\n");
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printed_gart_size_msg = 1;
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aper_order = (read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL) >> 1) & 7;
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aper_size = (32 * 1024 * 1024) << aper_order;
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aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;
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aper_base <<= 25;
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printk(KERN_INFO "Node %d: aperture @ %Lx size %u MB\n",
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node, aper_base, aper_size >> 20);
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node++;
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if (!aperture_valid(aper_base, aper_size, 64<<20)) {
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if (valid_agp && agp_aper_base &&
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agp_aper_base == aper_base &&
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agp_aper_order == aper_order) {
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/* the same between two setting from NB and agp */
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if (!no_iommu && end_pfn > MAX_DMA32_PFN && !printed_gart_size_msg) {
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printk(KERN_ERR "you are using iommu with agp, but GART size is less than 64M\n");
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printk(KERN_ERR "please increase GART size in your BIOS setup\n");
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printk(KERN_ERR "if BIOS doesn't have that option, contact your HW vendor!\n");
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printed_gart_size_msg = 1;
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}
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} else {
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fix = 1;
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goto out;
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}
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} else {
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fix = 1;
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break;
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}
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}
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if ((last_aper_order && aper_order != last_aper_order) ||
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(last_aper_base && aper_base != last_aper_base)) {
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fix = 1;
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break;
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if ((last_aper_order && aper_order != last_aper_order) ||
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(last_aper_base && aper_base != last_aper_base)) {
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fix = 1;
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goto out;
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}
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last_aper_order = aper_order;
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last_aper_base = aper_base;
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}
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last_aper_order = aper_order;
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last_aper_base = aper_base;
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}
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out:
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if (!fix && !fallback_aper_force) {
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if (last_aper_base) {
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unsigned long n = (32 * 1024 * 1024) << last_aper_order;
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@ -452,16 +494,22 @@ void __init gart_iommu_hole_init(void)
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}
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/* Fix up the north bridges */
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for (num = 24; num < 32; num++) {
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if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
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continue;
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for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
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int bus;
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int dev_base, dev_limit;
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/*
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* Don't enable translation yet. That is done later.
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* Assume this BIOS didn't initialise the GART so
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* just overwrite all previous bits
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*/
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write_pci_config(0, num, 3, 0x90, aper_order<<1);
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write_pci_config(0, num, 3, 0x94, aper_alloc>>25);
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bus = bus_dev_ranges[i].bus;
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dev_base = bus_dev_ranges[i].dev_base;
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dev_limit = bus_dev_ranges[i].dev_limit;
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for (slot = dev_base; slot < dev_limit; slot++) {
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if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00)))
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continue;
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/* Don't enable translation yet. That is done later.
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Assume this BIOS didn't initialise the GART so
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just overwrite all previous bits */
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write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, aper_order << 1);
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write_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE, aper_alloc >> 25);
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}
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}
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}
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